source: mainline/uspace/drv/bus/usb/uhci/hc.c@ ba4a03a5

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ba4a03a5 was ba4a03a5, checked in by Jan Vesely <jano.vesely@…>, 11 years ago

usb host: Use all hw resources when generating irq code.
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File size: 15.3 KB
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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34
35#include <adt/list.h>
36#include <assert.h>
37#include <async.h>
38#include <ddi.h>
39#include <device/hw_res_parsed.h>
40#include <fibril.h>
41#include <errno.h>
42#include <macros.h>
43#include <mem.h>
44#include <stdlib.h>
45#include <str_error.h>
46#include <sys/types.h>
47
48#include <usb/debug.h>
49#include <usb/usb.h>
50
51#include "uhci_batch.h"
52#include "utils/malloc32.h"
53#include "hc.h"
54
55#define UHCI_INTR_ALLOW_INTERRUPTS \
56 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
57#define UHCI_STATUS_USED_INTERRUPTS \
58 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
59
60static const irq_pio_range_t uhci_irq_pio_ranges[] = {
61 {
62 .base = 0,
63 .size = sizeof(uhci_regs_t)
64 }
65};
66
67static const irq_cmd_t uhci_irq_commands[] = {
68 {
69 .cmd = CMD_PIO_READ_16,
70 .dstarg = 1,
71 .addr = NULL
72 },
73 {
74 .cmd = CMD_AND,
75 .srcarg = 1,
76 .dstarg = 2,
77 .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS
78 },
79 {
80 .cmd = CMD_PREDICATE,
81 .srcarg = 2,
82 .value = 2
83 },
84 {
85 .cmd = CMD_PIO_WRITE_A_16,
86 .srcarg = 1,
87 .addr = NULL
88 },
89 {
90 .cmd = CMD_ACCEPT
91 }
92};
93
94static void hc_init_hw(const hc_t *instance);
95static int hc_init_mem_structures(hc_t *instance);
96static int hc_init_transfer_lists(hc_t *instance);
97
98static int hc_interrupt_emulator(void *arg);
99static int hc_debug_checker(void *arg);
100
101
102/** Generate IRQ code.
103 * @param[out] code IRQ code structure.
104 * @param[in] hw_res Device's resources.
105 *
106 * @return Error code.
107 */
108int hc_gen_irq_code(irq_code_t *code, const hw_res_list_parsed_t *hw_res)
109{
110 assert(code);
111 assert(hw_res);
112
113 if (hw_res->irqs.count != 1 || hw_res->io_ranges.count != 1)
114 return EINVAL;
115 const addr_range_t regs = hw_res->io_ranges.ranges[0];
116
117 if (RNGSZ(regs) < sizeof(uhci_regs_t))
118 return EOVERFLOW;
119
120 code->ranges = malloc(sizeof(uhci_irq_pio_ranges));
121 if (code->ranges == NULL)
122 return ENOMEM;
123
124 code->cmds = malloc(sizeof(uhci_irq_commands));
125 if (code->cmds == NULL) {
126 free(code->ranges);
127 return ENOMEM;
128 }
129
130 code->rangecount = ARRAY_SIZE(uhci_irq_pio_ranges);
131 code->cmdcount = ARRAY_SIZE(uhci_irq_commands);
132
133 memcpy(code->ranges, uhci_irq_pio_ranges, sizeof(uhci_irq_pio_ranges));
134 code->ranges[0].base = RNGABS(regs);
135
136 memcpy(code->cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
137 uhci_regs_t *registers = (uhci_regs_t *) RNGABSPTR(regs);
138 code->cmds[0].addr = (void*)&registers->usbsts;
139 code->cmds[3].addr = (void*)&registers->usbsts;
140
141 usb_log_debug("I/O regs at %p (size %zu), IRQ %d.\n",
142 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
143
144 return hw_res->irqs.irqs[0];
145}
146
147/** Take action based on the interrupt cause.
148 *
149 * @param[in] instance UHCI structure to use.
150 * @param[in] status Value of the status register at the time of interrupt.
151 *
152 * Interrupt might indicate:
153 * - transaction completed, either by triggering IOC, SPD, or an error
154 * - some kind of device error
155 * - resume from suspend state (not implemented)
156 */
157void hc_interrupt(hc_t *instance, uint16_t status)
158{
159 assert(instance);
160 /* Lower 2 bits are transaction error and transaction complete */
161 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
162 LIST_INITIALIZE(done);
163 transfer_list_remove_finished(
164 &instance->transfers_interrupt, &done);
165 transfer_list_remove_finished(
166 &instance->transfers_control_slow, &done);
167 transfer_list_remove_finished(
168 &instance->transfers_control_full, &done);
169 transfer_list_remove_finished(
170 &instance->transfers_bulk_full, &done);
171
172 list_foreach_safe(done, current, next) {
173 list_remove(current);
174 uhci_transfer_batch_t *batch =
175 uhci_transfer_batch_from_link(current);
176 uhci_transfer_batch_finish_dispose(batch);
177 }
178 }
179 /* Resume interrupts are not supported */
180 if (status & UHCI_STATUS_RESUME) {
181 usb_log_error("Resume interrupt!\n");
182 }
183
184 /* Bits 4 and 5 indicate hc error */
185 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
186 usb_log_error("UHCI hardware failure!.\n");
187 ++instance->hw_failures;
188 transfer_list_abort_all(&instance->transfers_interrupt);
189 transfer_list_abort_all(&instance->transfers_control_slow);
190 transfer_list_abort_all(&instance->transfers_control_full);
191 transfer_list_abort_all(&instance->transfers_bulk_full);
192
193 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
194 /* reinitialize hw, this triggers virtual disconnect*/
195 hc_init_hw(instance);
196 } else {
197 usb_log_fatal("Too many UHCI hardware failures!.\n");
198 hc_fini(instance);
199 }
200 }
201}
202
203/** Initialize UHCI hc driver structure
204 *
205 * @param[in] instance Memory place to initialize.
206 * @param[in] regs Range of device's I/O control registers.
207 * @param[in] interrupts True if hw interrupts should be used.
208 * @return Error code.
209 * @note Should be called only once on any structure.
210 *
211 * Initializes memory structures, starts up hw, and launches debugger and
212 * interrupt fibrils.
213 */
214int hc_init(hc_t *instance, addr_range_t *regs, bool interrupts)
215{
216 assert(instance);
217 assert(regs);
218 assert(regs->size >= sizeof(uhci_regs_t));
219
220 instance->hw_interrupts = interrupts;
221 instance->hw_failures = 0;
222
223 /* allow access to hc control registers */
224 uhci_regs_t *io;
225 int ret = pio_enable_range(regs, (void **) &io);
226 if (ret != EOK) {
227 usb_log_error("Failed to gain access to registers at %p: %s.\n",
228 io, str_error(ret));
229 return ret;
230 }
231 instance->registers = io;
232
233 usb_log_debug(
234 "Device registers at %p (%zuB) accessible.\n", io, regs->size);
235
236 ret = hc_init_mem_structures(instance);
237 if (ret != EOK) {
238 usb_log_error("Failed to init UHCI memory structures: %s.\n",
239 str_error(ret));
240 // TODO: we should disable pio here
241 return ret;
242 }
243
244 hc_init_hw(instance);
245 if (!interrupts) {
246 instance->interrupt_emulator =
247 fibril_create(hc_interrupt_emulator, instance);
248 fibril_add_ready(instance->interrupt_emulator);
249 }
250 (void)hc_debug_checker;
251
252 uhci_rh_init(&instance->rh, instance->registers->ports, "uhci");
253
254 return EOK;
255}
256
257/** Initialize UHCI hc hw resources.
258 *
259 * @param[in] instance UHCI structure to use.
260 * For magic values see UHCI Design Guide
261 */
262void hc_init_hw(const hc_t *instance)
263{
264 assert(instance);
265 uhci_regs_t *registers = instance->registers;
266
267 /* Reset everything, who knows what touched it before us */
268 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
269 async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
270 pio_write_16(&registers->usbcmd, 0);
271
272 /* Reset hc, all states and counters. Hope that hw is not broken */
273 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
274 do { async_usleep(10); }
275 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
276
277 /* Set frame to exactly 1ms */
278 pio_write_8(&registers->sofmod, 64);
279
280 /* Set frame list pointer */
281 const uint32_t pa = addr_to_phys(instance->frame_list);
282 pio_write_32(&registers->flbaseadd, pa);
283
284 if (instance->hw_interrupts) {
285 /* Enable all interrupts, but resume interrupt */
286 pio_write_16(&instance->registers->usbintr,
287 UHCI_INTR_ALLOW_INTERRUPTS);
288 }
289
290 const uint16_t cmd = pio_read_16(&registers->usbcmd);
291 if (cmd != 0)
292 usb_log_warning("Previous command value: %x.\n", cmd);
293
294 /* Start the hc with large(64B) packet FSBR */
295 pio_write_16(&registers->usbcmd,
296 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
297}
298
299/** Initialize UHCI hc memory structures.
300 *
301 * @param[in] instance UHCI structure to use.
302 * @return Error code
303 * @note Should be called only once on any structure.
304 *
305 * Structures:
306 * - transfer lists (queue heads need to be accessible by the hw)
307 * - frame list page (needs to be one UHCI hw accessible 4K page)
308 */
309int hc_init_mem_structures(hc_t *instance)
310{
311 assert(instance);
312
313 /* Init USB frame list page */
314 instance->frame_list = get_page();
315 if (!instance->frame_list) {
316 return ENOMEM;
317 }
318 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
319
320 /* Init transfer lists */
321 int ret = hc_init_transfer_lists(instance);
322 if (ret != EOK) {
323 usb_log_error("Failed to initialize transfer lists.\n");
324 return_page(instance->frame_list);
325 return ENOMEM;
326 }
327 usb_log_debug("Initialized transfer lists.\n");
328
329
330 /* Set all frames to point to the first queue head */
331 const uint32_t queue = LINK_POINTER_QH(
332 addr_to_phys(instance->transfers_interrupt.queue_head));
333
334 for (unsigned i = 0; i < UHCI_FRAME_LIST_COUNT; ++i) {
335 instance->frame_list[i] = queue;
336 }
337
338 return EOK;
339}
340
341/** Initialize UHCI hc transfer lists.
342 *
343 * @param[in] instance UHCI structure to use.
344 * @return Error code
345 * @note Should be called only once on any structure.
346 *
347 * Initializes transfer lists and sets them in one chain to support proper
348 * USB scheduling. Sets pointer table for quick access.
349 */
350int hc_init_transfer_lists(hc_t *instance)
351{
352 assert(instance);
353#define SETUP_TRANSFER_LIST(type, name) \
354do { \
355 int ret = transfer_list_init(&instance->transfers_##type, name); \
356 if (ret != EOK) { \
357 usb_log_error("Failed to setup %s transfer list: %s.\n", \
358 name, str_error(ret)); \
359 transfer_list_fini(&instance->transfers_bulk_full); \
360 transfer_list_fini(&instance->transfers_control_full); \
361 transfer_list_fini(&instance->transfers_control_slow); \
362 transfer_list_fini(&instance->transfers_interrupt); \
363 return ret; \
364 } \
365} while (0)
366
367 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
368 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
369 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
370 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
371#undef SETUP_TRANSFER_LIST
372 /* Connect lists into one schedule */
373 transfer_list_set_next(&instance->transfers_control_full,
374 &instance->transfers_bulk_full);
375 transfer_list_set_next(&instance->transfers_control_slow,
376 &instance->transfers_control_full);
377 transfer_list_set_next(&instance->transfers_interrupt,
378 &instance->transfers_control_slow);
379
380 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
381 * buggy on certain hw, enable at your own risk. */
382#ifdef FSBR
383 transfer_list_set_next(&instance->transfers_bulk_full,
384 &instance->transfers_control_full);
385#endif
386
387 /* Assign pointers to be used during scheduling */
388 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
389 &instance->transfers_interrupt;
390 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
391 &instance->transfers_interrupt;
392 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
393 &instance->transfers_control_full;
394 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
395 &instance->transfers_control_slow;
396 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
397 &instance->transfers_bulk_full;
398
399 return EOK;
400}
401
402/** Schedule batch for execution.
403 *
404 * @param[in] instance UHCI structure to use.
405 * @param[in] batch Transfer batch to schedule.
406 * @return Error code
407 *
408 * Checks for bandwidth availability and appends the batch to the proper queue.
409 */
410int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
411{
412 assert(hcd);
413 hc_t *instance = hcd->driver.data;
414 assert(instance);
415 assert(batch);
416
417 if (batch->ep->address == uhci_rh_get_address(&instance->rh))
418 return uhci_rh_schedule(&instance->rh, batch);
419
420 uhci_transfer_batch_t *uhci_batch = uhci_transfer_batch_get(batch);
421 if (!uhci_batch) {
422 usb_log_error("Failed to create UHCI transfer structures.\n");
423 return ENOMEM;
424 }
425
426 transfer_list_t *list =
427 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
428 assert(list);
429 transfer_list_add_batch(list, uhci_batch);
430
431 return EOK;
432}
433
434/** Polling function, emulates interrupts.
435 *
436 * @param[in] arg UHCI hc structure to use.
437 * @return EOK (should never return)
438 */
439int hc_interrupt_emulator(void* arg)
440{
441 usb_log_debug("Started interrupt emulator.\n");
442 hc_t *instance = arg;
443 assert(instance);
444
445 while (1) {
446 /* Read and clear status register */
447 uint16_t status = pio_read_16(&instance->registers->usbsts);
448 pio_write_16(&instance->registers->usbsts, status);
449 if (status != 0)
450 usb_log_debug2("UHCI status: %x.\n", status);
451 hc_interrupt(instance, status);
452 async_usleep(UHCI_INT_EMULATOR_TIMEOUT);
453 }
454 return EOK;
455}
456
457/** Debug function, checks consistency of memory structures.
458 *
459 * @param[in] arg UHCI structure to use.
460 * @return EOK (should never return)
461 */
462int hc_debug_checker(void *arg)
463{
464 hc_t *instance = arg;
465 assert(instance);
466
467#define QH(queue) \
468 instance->transfers_##queue.queue_head
469
470 while (1) {
471 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
472 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
473 const uint16_t intr =
474 pio_read_16(&instance->registers->usbintr);
475
476 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
477 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
478 cmd, sts, intr);
479 }
480
481 const uintptr_t frame_list =
482 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
483 if (frame_list != addr_to_phys(instance->frame_list)) {
484 usb_log_debug("Framelist address: %p vs. %p.\n",
485 (void *) frame_list,
486 (void *) addr_to_phys(instance->frame_list));
487 }
488
489 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
490
491 uintptr_t expected_pa = instance->frame_list[frnum]
492 & LINK_POINTER_ADDRESS_MASK;
493 uintptr_t real_pa = addr_to_phys(QH(interrupt));
494 if (expected_pa != real_pa) {
495 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
496 (void *) expected_pa, frnum, (void *) real_pa);
497 }
498
499 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
500 real_pa = addr_to_phys(QH(control_slow));
501 if (expected_pa != real_pa) {
502 usb_log_debug("Control Slow QH: %p vs. %p.\n",
503 (void *) expected_pa, (void *) real_pa);
504 }
505
506 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
507 real_pa = addr_to_phys(QH(control_full));
508 if (expected_pa != real_pa) {
509 usb_log_debug("Control Full QH: %p vs. %p.\n",
510 (void *) expected_pa, (void *) real_pa);
511 }
512
513 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
514 real_pa = addr_to_phys(QH(bulk_full));
515 if (expected_pa != real_pa ) {
516 usb_log_debug("Bulk QH: %p vs. %p.\n",
517 (void *) expected_pa, (void *) real_pa);
518 }
519 async_usleep(UHCI_DEBUGER_TIMEOUT);
520 }
521 return EOK;
522#undef QH
523}
524/**
525 * @}
526 */
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