source: mainline/uspace/drv/bus/usb/uhci/hc.c@ ad5f149

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ad5f149 was ad5f149, checked in by Jan Vesely <jano.vesely@…>, 11 years ago

uhci: Use foreach_safe to iterate through list.
  • Property mode set to 100644
File size: 15.0 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34
35#include <adt/list.h>
36#include <assert.h>
37#include <async.h>
38#include <ddi.h>
39#include <device/hw_res_parsed.h>
40#include <fibril.h>
41#include <errno.h>
42#include <macros.h>
43#include <mem.h>
44#include <stdlib.h>
45#include <str_error.h>
46#include <sys/types.h>
47
48#include <usb/debug.h>
49#include <usb/usb.h>
50
51#include "uhci_batch.h"
52#include "utils/malloc32.h"
53#include "hc.h"
54
55#define UHCI_INTR_ALLOW_INTERRUPTS \
56 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
57#define UHCI_STATUS_USED_INTERRUPTS \
58 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
59
60static const irq_pio_range_t uhci_irq_pio_ranges[] = {
61 {
62 .base = 0,
63 .size = sizeof(uhci_regs_t)
64 }
65};
66
67static const irq_cmd_t uhci_irq_commands[] = {
68 {
69 .cmd = CMD_PIO_READ_16,
70 .dstarg = 1,
71 .addr = NULL
72 },
73 {
74 .cmd = CMD_AND,
75 .srcarg = 1,
76 .dstarg = 2,
77 .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS
78 },
79 {
80 .cmd = CMD_PREDICATE,
81 .srcarg = 2,
82 .value = 2
83 },
84 {
85 .cmd = CMD_PIO_WRITE_A_16,
86 .srcarg = 1,
87 .addr = NULL
88 },
89 {
90 .cmd = CMD_ACCEPT
91 }
92};
93
94static void hc_init_hw(const hc_t *instance);
95static int hc_init_mem_structures(hc_t *instance);
96static int hc_init_transfer_lists(hc_t *instance);
97
98static int hc_interrupt_emulator(void *arg);
99static int hc_debug_checker(void *arg);
100
101
102/** Generate IRQ code.
103 * @param[out] code IRQ code structure.
104 * @param[in] regs Device's register range.
105 *
106 * @return Error code.
107 */
108int hc_gen_irq_code(irq_code_t *code, addr_range_t *regs)
109{
110 assert(code);
111
112 if (RNGSZ(*regs) < sizeof(uhci_regs_t))
113 return EOVERFLOW;
114
115 code->ranges = malloc(sizeof(uhci_irq_pio_ranges));
116 if (code->ranges == NULL)
117 return ENOMEM;
118
119 code->cmds = malloc(sizeof(uhci_irq_commands));
120 if (code->cmds == NULL) {
121 free(code->ranges);
122 return ENOMEM;
123 }
124
125 code->rangecount = ARRAY_SIZE(uhci_irq_pio_ranges);
126 code->cmdcount = ARRAY_SIZE(uhci_irq_commands);
127
128 memcpy(code->ranges, uhci_irq_pio_ranges, sizeof(uhci_irq_pio_ranges));
129 code->ranges[0].base = RNGABS(*regs);
130
131 memcpy(code->cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
132 uhci_regs_t *registers = (uhci_regs_t *) RNGABSPTR(*regs);
133 code->cmds[0].addr = (void*)&registers->usbsts;
134 code->cmds[3].addr = (void*)&registers->usbsts;
135
136 return EOK;
137}
138
139/** Take action based on the interrupt cause.
140 *
141 * @param[in] instance UHCI structure to use.
142 * @param[in] status Value of the status register at the time of interrupt.
143 *
144 * Interrupt might indicate:
145 * - transaction completed, either by triggering IOC, SPD, or an error
146 * - some kind of device error
147 * - resume from suspend state (not implemented)
148 */
149void hc_interrupt(hc_t *instance, uint16_t status)
150{
151 assert(instance);
152 /* Lower 2 bits are transaction error and transaction complete */
153 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
154 LIST_INITIALIZE(done);
155 transfer_list_remove_finished(
156 &instance->transfers_interrupt, &done);
157 transfer_list_remove_finished(
158 &instance->transfers_control_slow, &done);
159 transfer_list_remove_finished(
160 &instance->transfers_control_full, &done);
161 transfer_list_remove_finished(
162 &instance->transfers_bulk_full, &done);
163
164 list_foreach_safe(done, current, next) {
165 list_remove(current);
166 uhci_transfer_batch_t *batch =
167 uhci_transfer_batch_from_link(current);
168 uhci_transfer_batch_finish_dispose(batch);
169 }
170 }
171 /* Resume interrupts are not supported */
172 if (status & UHCI_STATUS_RESUME) {
173 usb_log_error("Resume interrupt!\n");
174 }
175
176 /* Bits 4 and 5 indicate hc error */
177 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
178 usb_log_error("UHCI hardware failure!.\n");
179 ++instance->hw_failures;
180 transfer_list_abort_all(&instance->transfers_interrupt);
181 transfer_list_abort_all(&instance->transfers_control_slow);
182 transfer_list_abort_all(&instance->transfers_control_full);
183 transfer_list_abort_all(&instance->transfers_bulk_full);
184
185 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
186 /* reinitialize hw, this triggers virtual disconnect*/
187 hc_init_hw(instance);
188 } else {
189 usb_log_fatal("Too many UHCI hardware failures!.\n");
190 hc_fini(instance);
191 }
192 }
193}
194
195/** Initialize UHCI hc driver structure
196 *
197 * @param[in] instance Memory place to initialize.
198 * @param[in] regs Range of device's I/O control registers.
199 * @param[in] interrupts True if hw interrupts should be used.
200 * @return Error code.
201 * @note Should be called only once on any structure.
202 *
203 * Initializes memory structures, starts up hw, and launches debugger and
204 * interrupt fibrils.
205 */
206int hc_init(hc_t *instance, addr_range_t *regs, bool interrupts)
207{
208 assert(instance);
209 assert(regs);
210 assert(regs->size >= sizeof(uhci_regs_t));
211
212 instance->hw_interrupts = interrupts;
213 instance->hw_failures = 0;
214
215 /* allow access to hc control registers */
216 uhci_regs_t *io;
217 int ret = pio_enable_range(regs, (void **) &io);
218 if (ret != EOK) {
219 usb_log_error("Failed to gain access to registers at %p: %s.\n",
220 io, str_error(ret));
221 return ret;
222 }
223 instance->registers = io;
224
225 usb_log_debug(
226 "Device registers at %p (%zuB) accessible.\n", io, regs->size);
227
228 ret = hc_init_mem_structures(instance);
229 if (ret != EOK) {
230 usb_log_error("Failed to init UHCI memory structures: %s.\n",
231 str_error(ret));
232 // TODO: we should disable pio here
233 return ret;
234 }
235
236 hc_init_hw(instance);
237 if (!interrupts) {
238 instance->interrupt_emulator =
239 fibril_create(hc_interrupt_emulator, instance);
240 fibril_add_ready(instance->interrupt_emulator);
241 }
242 (void)hc_debug_checker;
243
244 uhci_rh_init(&instance->rh, instance->registers->ports, "uhci");
245
246 return EOK;
247}
248
249/** Initialize UHCI hc hw resources.
250 *
251 * @param[in] instance UHCI structure to use.
252 * For magic values see UHCI Design Guide
253 */
254void hc_init_hw(const hc_t *instance)
255{
256 assert(instance);
257 uhci_regs_t *registers = instance->registers;
258
259 /* Reset everything, who knows what touched it before us */
260 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
261 async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
262 pio_write_16(&registers->usbcmd, 0);
263
264 /* Reset hc, all states and counters. Hope that hw is not broken */
265 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
266 do { async_usleep(10); }
267 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
268
269 /* Set frame to exactly 1ms */
270 pio_write_8(&registers->sofmod, 64);
271
272 /* Set frame list pointer */
273 const uint32_t pa = addr_to_phys(instance->frame_list);
274 pio_write_32(&registers->flbaseadd, pa);
275
276 if (instance->hw_interrupts) {
277 /* Enable all interrupts, but resume interrupt */
278 pio_write_16(&instance->registers->usbintr,
279 UHCI_INTR_ALLOW_INTERRUPTS);
280 }
281
282 const uint16_t cmd = pio_read_16(&registers->usbcmd);
283 if (cmd != 0)
284 usb_log_warning("Previous command value: %x.\n", cmd);
285
286 /* Start the hc with large(64B) packet FSBR */
287 pio_write_16(&registers->usbcmd,
288 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
289}
290
291/** Initialize UHCI hc memory structures.
292 *
293 * @param[in] instance UHCI structure to use.
294 * @return Error code
295 * @note Should be called only once on any structure.
296 *
297 * Structures:
298 * - transfer lists (queue heads need to be accessible by the hw)
299 * - frame list page (needs to be one UHCI hw accessible 4K page)
300 */
301int hc_init_mem_structures(hc_t *instance)
302{
303 assert(instance);
304
305 /* Init USB frame list page */
306 instance->frame_list = get_page();
307 if (!instance->frame_list) {
308 return ENOMEM;
309 }
310 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
311
312 /* Init transfer lists */
313 int ret = hc_init_transfer_lists(instance);
314 if (ret != EOK) {
315 usb_log_error("Failed to initialize transfer lists.\n");
316 return_page(instance->frame_list);
317 return ENOMEM;
318 }
319 usb_log_debug("Initialized transfer lists.\n");
320
321
322 /* Set all frames to point to the first queue head */
323 const uint32_t queue = LINK_POINTER_QH(
324 addr_to_phys(instance->transfers_interrupt.queue_head));
325
326 for (unsigned i = 0; i < UHCI_FRAME_LIST_COUNT; ++i) {
327 instance->frame_list[i] = queue;
328 }
329
330 return EOK;
331}
332
333/** Initialize UHCI hc transfer lists.
334 *
335 * @param[in] instance UHCI structure to use.
336 * @return Error code
337 * @note Should be called only once on any structure.
338 *
339 * Initializes transfer lists and sets them in one chain to support proper
340 * USB scheduling. Sets pointer table for quick access.
341 */
342int hc_init_transfer_lists(hc_t *instance)
343{
344 assert(instance);
345#define SETUP_TRANSFER_LIST(type, name) \
346do { \
347 int ret = transfer_list_init(&instance->transfers_##type, name); \
348 if (ret != EOK) { \
349 usb_log_error("Failed to setup %s transfer list: %s.\n", \
350 name, str_error(ret)); \
351 transfer_list_fini(&instance->transfers_bulk_full); \
352 transfer_list_fini(&instance->transfers_control_full); \
353 transfer_list_fini(&instance->transfers_control_slow); \
354 transfer_list_fini(&instance->transfers_interrupt); \
355 return ret; \
356 } \
357} while (0)
358
359 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
360 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
361 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
362 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
363#undef SETUP_TRANSFER_LIST
364 /* Connect lists into one schedule */
365 transfer_list_set_next(&instance->transfers_control_full,
366 &instance->transfers_bulk_full);
367 transfer_list_set_next(&instance->transfers_control_slow,
368 &instance->transfers_control_full);
369 transfer_list_set_next(&instance->transfers_interrupt,
370 &instance->transfers_control_slow);
371
372 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
373 * buggy on certain hw, enable at your own risk. */
374#ifdef FSBR
375 transfer_list_set_next(&instance->transfers_bulk_full,
376 &instance->transfers_control_full);
377#endif
378
379 /* Assign pointers to be used during scheduling */
380 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
381 &instance->transfers_interrupt;
382 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
383 &instance->transfers_interrupt;
384 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
385 &instance->transfers_control_full;
386 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
387 &instance->transfers_control_slow;
388 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
389 &instance->transfers_bulk_full;
390
391 return EOK;
392}
393
394/** Schedule batch for execution.
395 *
396 * @param[in] instance UHCI structure to use.
397 * @param[in] batch Transfer batch to schedule.
398 * @return Error code
399 *
400 * Checks for bandwidth availability and appends the batch to the proper queue.
401 */
402int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
403{
404 assert(hcd);
405 hc_t *instance = hcd->driver.data;
406 assert(instance);
407 assert(batch);
408
409 if (batch->ep->address == uhci_rh_get_address(&instance->rh))
410 return uhci_rh_schedule(&instance->rh, batch);
411
412 uhci_transfer_batch_t *uhci_batch = uhci_transfer_batch_get(batch);
413 if (!uhci_batch) {
414 usb_log_error("Failed to create UHCI transfer structures.\n");
415 return ENOMEM;
416 }
417
418 transfer_list_t *list =
419 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
420 assert(list);
421 transfer_list_add_batch(list, uhci_batch);
422
423 return EOK;
424}
425
426/** Polling function, emulates interrupts.
427 *
428 * @param[in] arg UHCI hc structure to use.
429 * @return EOK (should never return)
430 */
431int hc_interrupt_emulator(void* arg)
432{
433 usb_log_debug("Started interrupt emulator.\n");
434 hc_t *instance = arg;
435 assert(instance);
436
437 while (1) {
438 /* Read and clear status register */
439 uint16_t status = pio_read_16(&instance->registers->usbsts);
440 pio_write_16(&instance->registers->usbsts, status);
441 if (status != 0)
442 usb_log_debug2("UHCI status: %x.\n", status);
443 hc_interrupt(instance, status);
444 async_usleep(UHCI_INT_EMULATOR_TIMEOUT);
445 }
446 return EOK;
447}
448
449/** Debug function, checks consistency of memory structures.
450 *
451 * @param[in] arg UHCI structure to use.
452 * @return EOK (should never return)
453 */
454int hc_debug_checker(void *arg)
455{
456 hc_t *instance = arg;
457 assert(instance);
458
459#define QH(queue) \
460 instance->transfers_##queue.queue_head
461
462 while (1) {
463 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
464 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
465 const uint16_t intr =
466 pio_read_16(&instance->registers->usbintr);
467
468 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
469 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
470 cmd, sts, intr);
471 }
472
473 const uintptr_t frame_list =
474 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
475 if (frame_list != addr_to_phys(instance->frame_list)) {
476 usb_log_debug("Framelist address: %p vs. %p.\n",
477 (void *) frame_list,
478 (void *) addr_to_phys(instance->frame_list));
479 }
480
481 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
482
483 uintptr_t expected_pa = instance->frame_list[frnum]
484 & LINK_POINTER_ADDRESS_MASK;
485 uintptr_t real_pa = addr_to_phys(QH(interrupt));
486 if (expected_pa != real_pa) {
487 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
488 (void *) expected_pa, frnum, (void *) real_pa);
489 }
490
491 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
492 real_pa = addr_to_phys(QH(control_slow));
493 if (expected_pa != real_pa) {
494 usb_log_debug("Control Slow QH: %p vs. %p.\n",
495 (void *) expected_pa, (void *) real_pa);
496 }
497
498 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
499 real_pa = addr_to_phys(QH(control_full));
500 if (expected_pa != real_pa) {
501 usb_log_debug("Control Full QH: %p vs. %p.\n",
502 (void *) expected_pa, (void *) real_pa);
503 }
504
505 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
506 real_pa = addr_to_phys(QH(bulk_full));
507 if (expected_pa != real_pa ) {
508 usb_log_debug("Bulk QH: %p vs. %p.\n",
509 (void *) expected_pa, (void *) real_pa);
510 }
511 async_usleep(UHCI_DEBUGER_TIMEOUT);
512 }
513 return EOK;
514#undef QH
515}
516/**
517 * @}
518 */
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