source: mainline/uspace/drv/bus/usb/uhci/hc.c@ ad22fa4

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ad22fa4 was b5111c46, checked in by Jiri Svoboda <jiri@…>, 11 years ago

Convert OHCI and UHCI away from DDF_DATA_IMPLANT.
  • Property mode set to 100644
File size: 16.4 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41
42#include "hc.h"
43#include "uhci_batch.h"
44
45#define UHCI_INTR_ALLOW_INTERRUPTS \
46 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
47#define UHCI_STATUS_USED_INTERRUPTS \
48 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
49
50static const irq_pio_range_t uhci_irq_pio_ranges[] = {
51 {
52 .base = 0,
53 .size = sizeof(uhci_regs_t)
54 }
55};
56
57static const irq_cmd_t uhci_irq_commands[] = {
58 {
59 .cmd = CMD_PIO_READ_16,
60 .dstarg = 1,
61 .addr = NULL
62 },
63 {
64 .cmd = CMD_AND,
65 .srcarg = 1,
66 .dstarg = 2,
67 .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS
68 },
69 {
70 .cmd = CMD_PREDICATE,
71 .srcarg = 2,
72 .value = 2
73 },
74 {
75 .cmd = CMD_PIO_WRITE_A_16,
76 .srcarg = 1,
77 .addr = NULL
78 },
79 {
80 .cmd = CMD_ACCEPT
81 }
82};
83
84static void hc_init_hw(const hc_t *instance);
85static int hc_init_mem_structures(hc_t *instance);
86static int hc_init_transfer_lists(hc_t *instance);
87static int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch);
88
89static int hc_interrupt_emulator(void *arg);
90static int hc_debug_checker(void *arg);
91
92enum {
93 /** Number of PIO ranges used in IRQ code */
94 hc_irq_pio_range_count =
95 sizeof(uhci_irq_pio_ranges) / sizeof(irq_pio_range_t),
96
97 /* Number of commands used in IRQ code */
98 hc_irq_cmd_count =
99 sizeof(uhci_irq_commands) / sizeof(irq_cmd_t)
100};
101
102/** Generate IRQ code.
103 * @param[out] ranges PIO ranges buffer.
104 * @param[in] ranges_size Size of the ranges buffer (bytes).
105 * @param[out] cmds Commands buffer.
106 * @param[in] cmds_size Size of the commands buffer (bytes).
107 * @param[in] regs Device's register range.
108 *
109 * @return Error code.
110 */
111int
112hc_get_irq_code(irq_pio_range_t ranges[], size_t ranges_size, irq_cmd_t cmds[],
113 size_t cmds_size, addr_range_t *regs)
114{
115 if ((ranges_size < sizeof(uhci_irq_pio_ranges)) ||
116 (cmds_size < sizeof(uhci_irq_commands)) ||
117 (RNGSZ(*regs) < sizeof(uhci_regs_t)))
118 return EOVERFLOW;
119
120 memcpy(ranges, uhci_irq_pio_ranges, sizeof(uhci_irq_pio_ranges));
121 ranges[0].base = RNGABS(*regs);
122
123 memcpy(cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
124 uhci_regs_t *registers = (uhci_regs_t *) RNGABSPTR(*regs);
125 cmds[0].addr = (void *) &registers->usbsts;
126 cmds[3].addr = (void *) &registers->usbsts;
127
128 return EOK;
129}
130
131/** Register interrupt handler.
132 *
133 * @param[in] device Host controller DDF device
134 * @param[in] regs Register range
135 * @param[in] irq Interrupt number
136 * @paran[in] handler Interrupt handler
137 *
138 * @return EOK on success or negative error code
139 */
140int hc_register_irq_handler(ddf_dev_t *device, addr_range_t *regs, int irq,
141 interrupt_handler_t handler)
142{
143 int rc;
144 irq_pio_range_t irq_ranges[hc_irq_pio_range_count];
145 irq_cmd_t irq_cmds[hc_irq_cmd_count];
146 rc = hc_get_irq_code(irq_ranges, sizeof(irq_ranges), irq_cmds,
147 sizeof(irq_cmds), regs);
148 if (rc != EOK) {
149 usb_log_error("Failed to generate IRQ commands: %s.\n",
150 str_error(rc));
151 return rc;
152 }
153
154 irq_code_t irq_code = {
155 .rangecount = hc_irq_pio_range_count,
156 .ranges = irq_ranges,
157 .cmdcount = hc_irq_cmd_count,
158 .cmds = irq_cmds
159 };
160
161 /* Register handler to avoid interrupt lockup */
162 rc = register_interrupt_handler(device, irq, handler, &irq_code);
163 if (rc != EOK) {
164 usb_log_error("Failed to register interrupt handler: %s.\n",
165 str_error(rc));
166 return rc;
167 }
168
169 return EOK;
170}
171
172/** Take action based on the interrupt cause.
173 *
174 * @param[in] instance UHCI structure to use.
175 * @param[in] status Value of the status register at the time of interrupt.
176 *
177 * Interrupt might indicate:
178 * - transaction completed, either by triggering IOC, SPD, or an error
179 * - some kind of device error
180 * - resume from suspend state (not implemented)
181 */
182void hc_interrupt(hc_t *instance, uint16_t status)
183{
184 assert(instance);
185 /* Lower 2 bits are transaction error and transaction complete */
186 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
187 LIST_INITIALIZE(done);
188 transfer_list_remove_finished(
189 &instance->transfers_interrupt, &done);
190 transfer_list_remove_finished(
191 &instance->transfers_control_slow, &done);
192 transfer_list_remove_finished(
193 &instance->transfers_control_full, &done);
194 transfer_list_remove_finished(
195 &instance->transfers_bulk_full, &done);
196
197 while (!list_empty(&done)) {
198 link_t *item = list_first(&done);
199 list_remove(item);
200 uhci_transfer_batch_t *batch =
201 uhci_transfer_batch_from_link(item);
202 uhci_transfer_batch_finish_dispose(batch);
203 }
204 }
205 /* Resume interrupts are not supported */
206 if (status & UHCI_STATUS_RESUME) {
207 usb_log_error("Resume interrupt!\n");
208 }
209
210 /* Bits 4 and 5 indicate hc error */
211 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
212 usb_log_error("UHCI hardware failure!.\n");
213 ++instance->hw_failures;
214 transfer_list_abort_all(&instance->transfers_interrupt);
215 transfer_list_abort_all(&instance->transfers_control_slow);
216 transfer_list_abort_all(&instance->transfers_control_full);
217 transfer_list_abort_all(&instance->transfers_bulk_full);
218
219 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
220 /* reinitialize hw, this triggers virtual disconnect*/
221 hc_init_hw(instance);
222 } else {
223 usb_log_fatal("Too many UHCI hardware failures!.\n");
224 hc_fini(instance);
225 }
226 }
227}
228
229/** Initialize UHCI hc driver structure
230 *
231 * @param[in] instance Memory place to initialize.
232 * @param[in] HC function node
233 * @param[in] regs Range of device's I/O control registers.
234 * @param[in] interrupts True if hw interrupts should be used.
235 * @return Error code.
236 * @note Should be called only once on any structure.
237 *
238 * Initializes memory structures, starts up hw, and launches debugger and
239 * interrupt fibrils.
240 */
241int hc_init(hc_t *instance, ddf_fun_t *fun, addr_range_t *regs, bool interrupts)
242{
243 assert(regs->size >= sizeof(uhci_regs_t));
244 int rc;
245
246 instance->hw_interrupts = interrupts;
247 instance->hw_failures = 0;
248
249 /* allow access to hc control registers */
250 uhci_regs_t *io;
251 rc = pio_enable_range(regs, (void **) &io);
252 if (rc != EOK) {
253 usb_log_error("Failed to gain access to registers at %p: %s.\n",
254 io, str_error(rc));
255 return rc;
256 }
257
258 instance->registers = io;
259 usb_log_debug(
260 "Device registers at %p (%zuB) accessible.\n", io, regs->size);
261
262 rc = hc_init_mem_structures(instance);
263 if (rc != EOK) {
264 usb_log_error("Failed to initialize UHCI memory structures: %s.\n",
265 str_error(rc));
266 return rc;
267 }
268
269 instance->generic = ddf_fun_data_alloc(fun, sizeof(hcd_t));
270 if (instance->generic == NULL) {
271 usb_log_error("Out of memory.\n");
272 return ENOMEM;
273 }
274
275 hcd_init(instance->generic, USB_SPEED_FULL,
276 BANDWIDTH_AVAILABLE_USB11, bandwidth_count_usb11);
277
278 instance->generic->private_data = instance;
279 instance->generic->schedule = hc_schedule;
280 instance->generic->ep_add_hook = NULL;
281
282 hc_init_hw(instance);
283 if (!interrupts) {
284 instance->interrupt_emulator =
285 fibril_create(hc_interrupt_emulator, instance);
286 fibril_add_ready(instance->interrupt_emulator);
287 }
288 (void)hc_debug_checker;
289
290 return EOK;
291}
292
293/** Initialize UHCI hc hw resources.
294 *
295 * @param[in] instance UHCI structure to use.
296 * For magic values see UHCI Design Guide
297 */
298void hc_init_hw(const hc_t *instance)
299{
300 assert(instance);
301 uhci_regs_t *registers = instance->registers;
302
303 /* Reset everything, who knows what touched it before us */
304 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
305 async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
306 pio_write_16(&registers->usbcmd, 0);
307
308 /* Reset hc, all states and counters. Hope that hw is not broken */
309 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
310 do { async_usleep(10); }
311 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
312
313 /* Set frame to exactly 1ms */
314 pio_write_8(&registers->sofmod, 64);
315
316 /* Set frame list pointer */
317 const uint32_t pa = addr_to_phys(instance->frame_list);
318 pio_write_32(&registers->flbaseadd, pa);
319
320 if (instance->hw_interrupts) {
321 /* Enable all interrupts, but resume interrupt */
322 pio_write_16(&instance->registers->usbintr,
323 UHCI_INTR_ALLOW_INTERRUPTS);
324 }
325
326 const uint16_t cmd = pio_read_16(&registers->usbcmd);
327 if (cmd != 0)
328 usb_log_warning("Previous command value: %x.\n", cmd);
329
330 /* Start the hc with large(64B) packet FSBR */
331 pio_write_16(&registers->usbcmd,
332 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
333}
334
335/** Initialize UHCI hc memory structures.
336 *
337 * @param[in] instance UHCI structure to use.
338 * @return Error code
339 * @note Should be called only once on any structure.
340 *
341 * Structures:
342 * - transfer lists (queue heads need to be accessible by the hw)
343 * - frame list page (needs to be one UHCI hw accessible 4K page)
344 */
345int hc_init_mem_structures(hc_t *instance)
346{
347 assert(instance);
348
349 /* Init USB frame list page */
350 instance->frame_list = get_page();
351 if (!instance->frame_list) {
352 return ENOMEM;
353 }
354 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
355
356 /* Init transfer lists */
357 int ret = hc_init_transfer_lists(instance);
358 if (ret != EOK) {
359 usb_log_error("Failed to initialize transfer lists.\n");
360 return_page(instance->frame_list);
361 return ENOMEM;
362 }
363 usb_log_debug("Initialized transfer lists.\n");
364
365
366 /* Set all frames to point to the first queue head */
367 const uint32_t queue = LINK_POINTER_QH(
368 addr_to_phys(instance->transfers_interrupt.queue_head));
369
370 for (unsigned i = 0; i < UHCI_FRAME_LIST_COUNT; ++i) {
371 instance->frame_list[i] = queue;
372 }
373
374 return EOK;
375}
376
377/** Initialize UHCI hc transfer lists.
378 *
379 * @param[in] instance UHCI structure to use.
380 * @return Error code
381 * @note Should be called only once on any structure.
382 *
383 * Initializes transfer lists and sets them in one chain to support proper
384 * USB scheduling. Sets pointer table for quick access.
385 */
386int hc_init_transfer_lists(hc_t *instance)
387{
388 assert(instance);
389#define SETUP_TRANSFER_LIST(type, name) \
390do { \
391 int ret = transfer_list_init(&instance->transfers_##type, name); \
392 if (ret != EOK) { \
393 usb_log_error("Failed to setup %s transfer list: %s.\n", \
394 name, str_error(ret)); \
395 transfer_list_fini(&instance->transfers_bulk_full); \
396 transfer_list_fini(&instance->transfers_control_full); \
397 transfer_list_fini(&instance->transfers_control_slow); \
398 transfer_list_fini(&instance->transfers_interrupt); \
399 return ret; \
400 } \
401} while (0)
402
403 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
404 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
405 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
406 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
407#undef SETUP_TRANSFER_LIST
408 /* Connect lists into one schedule */
409 transfer_list_set_next(&instance->transfers_control_full,
410 &instance->transfers_bulk_full);
411 transfer_list_set_next(&instance->transfers_control_slow,
412 &instance->transfers_control_full);
413 transfer_list_set_next(&instance->transfers_interrupt,
414 &instance->transfers_control_slow);
415
416 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
417 * buggy on certain hw, enable at your own risk. */
418#ifdef FSBR
419 transfer_list_set_next(&instance->transfers_bulk_full,
420 &instance->transfers_control_full);
421#endif
422
423 /* Assign pointers to be used during scheduling */
424 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
425 &instance->transfers_interrupt;
426 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
427 &instance->transfers_interrupt;
428 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
429 &instance->transfers_control_full;
430 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
431 &instance->transfers_control_slow;
432 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
433 &instance->transfers_bulk_full;
434
435 return EOK;
436}
437
438/** Schedule batch for execution.
439 *
440 * @param[in] instance UHCI structure to use.
441 * @param[in] batch Transfer batch to schedule.
442 * @return Error code
443 *
444 * Checks for bandwidth availability and appends the batch to the proper queue.
445 */
446int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
447{
448 assert(hcd);
449 hc_t *instance = hcd->private_data;
450 assert(instance);
451 assert(batch);
452 uhci_transfer_batch_t *uhci_batch = uhci_transfer_batch_get(batch);
453 if (!uhci_batch) {
454 usb_log_error("Failed to create UHCI transfer structures.\n");
455 return ENOMEM;
456 }
457
458 transfer_list_t *list =
459 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
460 assert(list);
461 transfer_list_add_batch(list, uhci_batch);
462
463 return EOK;
464}
465
466/** Polling function, emulates interrupts.
467 *
468 * @param[in] arg UHCI hc structure to use.
469 * @return EOK (should never return)
470 */
471int hc_interrupt_emulator(void* arg)
472{
473 usb_log_debug("Started interrupt emulator.\n");
474 hc_t *instance = arg;
475 assert(instance);
476
477 while (1) {
478 /* Read and clear status register */
479 uint16_t status = pio_read_16(&instance->registers->usbsts);
480 pio_write_16(&instance->registers->usbsts, status);
481 if (status != 0)
482 usb_log_debug2("UHCI status: %x.\n", status);
483 hc_interrupt(instance, status);
484 async_usleep(UHCI_INT_EMULATOR_TIMEOUT);
485 }
486 return EOK;
487}
488
489/** Debug function, checks consistency of memory structures.
490 *
491 * @param[in] arg UHCI structure to use.
492 * @return EOK (should never return)
493 */
494int hc_debug_checker(void *arg)
495{
496 hc_t *instance = arg;
497 assert(instance);
498
499#define QH(queue) \
500 instance->transfers_##queue.queue_head
501
502 while (1) {
503 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
504 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
505 const uint16_t intr =
506 pio_read_16(&instance->registers->usbintr);
507
508 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
509 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
510 cmd, sts, intr);
511 }
512
513 const uintptr_t frame_list =
514 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
515 if (frame_list != addr_to_phys(instance->frame_list)) {
516 usb_log_debug("Framelist address: %p vs. %p.\n",
517 (void *) frame_list,
518 (void *) addr_to_phys(instance->frame_list));
519 }
520
521 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
522
523 uintptr_t expected_pa = instance->frame_list[frnum]
524 & LINK_POINTER_ADDRESS_MASK;
525 uintptr_t real_pa = addr_to_phys(QH(interrupt));
526 if (expected_pa != real_pa) {
527 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
528 (void *) expected_pa, frnum, (void *) real_pa);
529 }
530
531 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
532 real_pa = addr_to_phys(QH(control_slow));
533 if (expected_pa != real_pa) {
534 usb_log_debug("Control Slow QH: %p vs. %p.\n",
535 (void *) expected_pa, (void *) real_pa);
536 }
537
538 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
539 real_pa = addr_to_phys(QH(control_full));
540 if (expected_pa != real_pa) {
541 usb_log_debug("Control Full QH: %p vs. %p.\n",
542 (void *) expected_pa, (void *) real_pa);
543 }
544
545 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
546 real_pa = addr_to_phys(QH(bulk_full));
547 if (expected_pa != real_pa ) {
548 usb_log_debug("Bulk QH: %p vs. %p.\n",
549 (void *) expected_pa, (void *) real_pa);
550 }
551 async_usleep(UHCI_DEBUGER_TIMEOUT);
552 }
553 return EOK;
554#undef QH
555}
556/**
557 * @}
558 */
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