source: mainline/uspace/drv/bus/usb/uhci/hc.c@ 99c2c69e

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 99c2c69e was 7de1988c, checked in by Jakub Jermar <jakub@…>, 12 years ago

Adapt drivers using parsed HW resources to use the new interface.
  • Property mode set to 100644
File size: 16.1 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41
42#include "hc.h"
43#include "uhci_batch.h"
44
45#define UHCI_INTR_ALLOW_INTERRUPTS \
46 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
47#define UHCI_STATUS_USED_INTERRUPTS \
48 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
49
50static const irq_pio_range_t uhci_irq_pio_ranges[] = {
51 {
52 .base = 0,
53 .size = sizeof(uhci_regs_t)
54 }
55};
56
57static const irq_cmd_t uhci_irq_commands[] = {
58 {
59 .cmd = CMD_PIO_READ_16,
60 .dstarg = 1,
61 .addr = NULL
62 },
63 {
64 .cmd = CMD_AND,
65 .srcarg = 1,
66 .dstarg = 2,
67 .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS
68 },
69 {
70 .cmd = CMD_PREDICATE,
71 .srcarg = 2,
72 .value = 2
73 },
74 {
75 .cmd = CMD_PIO_WRITE_A_16,
76 .srcarg = 1,
77 .addr = NULL
78 },
79 {
80 .cmd = CMD_ACCEPT
81 }
82};
83
84static void hc_init_hw(const hc_t *instance);
85static int hc_init_mem_structures(hc_t *instance);
86static int hc_init_transfer_lists(hc_t *instance);
87static int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch);
88
89static int hc_interrupt_emulator(void *arg);
90static int hc_debug_checker(void *arg);
91
92enum {
93 /** Number of PIO ranges used in IRQ code */
94 hc_irq_pio_range_count =
95 sizeof(uhci_irq_pio_ranges) / sizeof(irq_pio_range_t),
96
97 /* Number of commands used in IRQ code */
98 hc_irq_cmd_count =
99 sizeof(uhci_irq_commands) / sizeof(irq_cmd_t)
100};
101
102/** Generate IRQ code.
103 * @param[out] ranges PIO ranges buffer.
104 * @param[in] ranges_size Size of the ranges buffer (bytes).
105 * @param[out] cmds Commands buffer.
106 * @param[in] cmds_size Size of the commands buffer (bytes).
107 * @param[in] regs Device's register range.
108 *
109 * @return Error code.
110 */
111int
112hc_get_irq_code(irq_pio_range_t ranges[], size_t ranges_size, irq_cmd_t cmds[],
113 size_t cmds_size, addr_range_t *regs)
114{
115 if ((ranges_size < sizeof(uhci_irq_pio_ranges)) ||
116 (cmds_size < sizeof(uhci_irq_commands)) ||
117 (RNGSZ(*regs) < sizeof(uhci_regs_t)))
118 return EOVERFLOW;
119
120 memcpy(ranges, uhci_irq_pio_ranges, sizeof(uhci_irq_pio_ranges));
121 ranges[0].base = RNGABS(*regs);
122
123 memcpy(cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
124 uhci_regs_t *registers = (uhci_regs_t *) RNGABSPTR(*regs);
125 cmds[0].addr = &registers->usbsts;
126 cmds[3].addr = &registers->usbsts;
127
128 return EOK;
129}
130
131/** Register interrupt handler.
132 *
133 * @param[in] device Host controller DDF device
134 * @param[in] regs Register range
135 * @param[in] irq Interrupt number
136 * @paran[in] handler Interrupt handler
137 *
138 * @return EOK on success or negative error code
139 */
140int hc_register_irq_handler(ddf_dev_t *device, addr_range_t *regs, int irq,
141 interrupt_handler_t handler)
142{
143 int rc;
144 irq_pio_range_t irq_ranges[hc_irq_pio_range_count];
145 irq_cmd_t irq_cmds[hc_irq_cmd_count];
146 rc = hc_get_irq_code(irq_ranges, sizeof(irq_ranges), irq_cmds,
147 sizeof(irq_cmds), regs);
148 if (rc != EOK) {
149 usb_log_error("Failed to generate IRQ commands: %s.\n",
150 str_error(rc));
151 return rc;
152 }
153
154 irq_code_t irq_code = {
155 .rangecount = hc_irq_pio_range_count,
156 .ranges = irq_ranges,
157 .cmdcount = hc_irq_cmd_count,
158 .cmds = irq_cmds
159 };
160
161 /* Register handler to avoid interrupt lockup */
162 rc = register_interrupt_handler(device, irq, handler, &irq_code);
163 if (rc != EOK) {
164 usb_log_error("Failed to register interrupt handler: %s.\n",
165 str_error(rc));
166 return rc;
167 }
168
169 return EOK;
170}
171
172/** Take action based on the interrupt cause.
173 *
174 * @param[in] instance UHCI structure to use.
175 * @param[in] status Value of the status register at the time of interrupt.
176 *
177 * Interrupt might indicate:
178 * - transaction completed, either by triggering IOC, SPD, or an error
179 * - some kind of device error
180 * - resume from suspend state (not implemented)
181 */
182void hc_interrupt(hc_t *instance, uint16_t status)
183{
184 assert(instance);
185 /* Lower 2 bits are transaction error and transaction complete */
186 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
187 LIST_INITIALIZE(done);
188 transfer_list_remove_finished(
189 &instance->transfers_interrupt, &done);
190 transfer_list_remove_finished(
191 &instance->transfers_control_slow, &done);
192 transfer_list_remove_finished(
193 &instance->transfers_control_full, &done);
194 transfer_list_remove_finished(
195 &instance->transfers_bulk_full, &done);
196
197 while (!list_empty(&done)) {
198 link_t *item = list_first(&done);
199 list_remove(item);
200 uhci_transfer_batch_t *batch =
201 uhci_transfer_batch_from_link(item);
202 uhci_transfer_batch_finish_dispose(batch);
203 }
204 }
205 /* Resume interrupts are not supported */
206 if (status & UHCI_STATUS_RESUME) {
207 usb_log_error("Resume interrupt!\n");
208 }
209
210 /* Bits 4 and 5 indicate hc error */
211 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
212 usb_log_error("UHCI hardware failure!.\n");
213 ++instance->hw_failures;
214 transfer_list_abort_all(&instance->transfers_interrupt);
215 transfer_list_abort_all(&instance->transfers_control_slow);
216 transfer_list_abort_all(&instance->transfers_control_full);
217 transfer_list_abort_all(&instance->transfers_bulk_full);
218
219 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
220 /* reinitialize hw, this triggers virtual disconnect*/
221 hc_init_hw(instance);
222 } else {
223 usb_log_fatal("Too many UHCI hardware failures!.\n");
224 hc_fini(instance);
225 }
226 }
227}
228
229/** Initialize UHCI hc driver structure
230 *
231 * @param[in] instance Memory place to initialize.
232 * @param[in] regs Range of device's I/O control registers.
233 * @param[in] interrupts True if hw interrupts should be used.
234 * @return Error code.
235 * @note Should be called only once on any structure.
236 *
237 * Initializes memory structures, starts up hw, and launches debugger and
238 * interrupt fibrils.
239 */
240int hc_init(hc_t *instance, addr_range_t *regs, bool interrupts)
241{
242 assert(regs->size >= sizeof(uhci_regs_t));
243 int rc;
244
245 instance->hw_interrupts = interrupts;
246 instance->hw_failures = 0;
247
248 /* allow access to hc control registers */
249 uhci_regs_t *io;
250 rc = pio_enable_range(regs, (void **) &io);
251 if (rc != EOK) {
252 usb_log_error("Failed to gain access to registers at %p: %s.\n",
253 io, str_error(rc));
254 return rc;
255 }
256
257 instance->registers = io;
258 usb_log_debug(
259 "Device registers at %p (%zuB) accessible.\n", io, regs->size);
260
261 rc = hc_init_mem_structures(instance);
262 if (rc != EOK) {
263 usb_log_error("Failed to initialize UHCI memory structures: %s.\n",
264 str_error(rc));
265 return rc;
266 }
267
268 hcd_init(&instance->generic, USB_SPEED_FULL,
269 BANDWIDTH_AVAILABLE_USB11, bandwidth_count_usb11);
270
271 instance->generic.private_data = instance;
272 instance->generic.schedule = hc_schedule;
273 instance->generic.ep_add_hook = NULL;
274
275 hc_init_hw(instance);
276 if (!interrupts) {
277 instance->interrupt_emulator =
278 fibril_create(hc_interrupt_emulator, instance);
279 fibril_add_ready(instance->interrupt_emulator);
280 }
281 (void)hc_debug_checker;
282
283 return EOK;
284}
285
286/** Initialize UHCI hc hw resources.
287 *
288 * @param[in] instance UHCI structure to use.
289 * For magic values see UHCI Design Guide
290 */
291void hc_init_hw(const hc_t *instance)
292{
293 assert(instance);
294 uhci_regs_t *registers = instance->registers;
295
296 /* Reset everything, who knows what touched it before us */
297 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
298 async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
299 pio_write_16(&registers->usbcmd, 0);
300
301 /* Reset hc, all states and counters. Hope that hw is not broken */
302 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
303 do { async_usleep(10); }
304 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
305
306 /* Set frame to exactly 1ms */
307 pio_write_8(&registers->sofmod, 64);
308
309 /* Set frame list pointer */
310 const uint32_t pa = addr_to_phys(instance->frame_list);
311 pio_write_32(&registers->flbaseadd, pa);
312
313 if (instance->hw_interrupts) {
314 /* Enable all interrupts, but resume interrupt */
315 pio_write_16(&instance->registers->usbintr,
316 UHCI_INTR_ALLOW_INTERRUPTS);
317 }
318
319 const uint16_t cmd = pio_read_16(&registers->usbcmd);
320 if (cmd != 0)
321 usb_log_warning("Previous command value: %x.\n", cmd);
322
323 /* Start the hc with large(64B) packet FSBR */
324 pio_write_16(&registers->usbcmd,
325 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
326}
327
328/** Initialize UHCI hc memory structures.
329 *
330 * @param[in] instance UHCI structure to use.
331 * @return Error code
332 * @note Should be called only once on any structure.
333 *
334 * Structures:
335 * - transfer lists (queue heads need to be accessible by the hw)
336 * - frame list page (needs to be one UHCI hw accessible 4K page)
337 */
338int hc_init_mem_structures(hc_t *instance)
339{
340 assert(instance);
341
342 /* Init USB frame list page */
343 instance->frame_list = get_page();
344 if (!instance->frame_list) {
345 return ENOMEM;
346 }
347 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
348
349 /* Init transfer lists */
350 int ret = hc_init_transfer_lists(instance);
351 if (ret != EOK) {
352 usb_log_error("Failed to initialize transfer lists.\n");
353 return_page(instance->frame_list);
354 return ENOMEM;
355 }
356 usb_log_debug("Initialized transfer lists.\n");
357
358
359 /* Set all frames to point to the first queue head */
360 const uint32_t queue = LINK_POINTER_QH(
361 addr_to_phys(instance->transfers_interrupt.queue_head));
362
363 for (unsigned i = 0; i < UHCI_FRAME_LIST_COUNT; ++i) {
364 instance->frame_list[i] = queue;
365 }
366
367 return EOK;
368}
369
370/** Initialize UHCI hc transfer lists.
371 *
372 * @param[in] instance UHCI structure to use.
373 * @return Error code
374 * @note Should be called only once on any structure.
375 *
376 * Initializes transfer lists and sets them in one chain to support proper
377 * USB scheduling. Sets pointer table for quick access.
378 */
379int hc_init_transfer_lists(hc_t *instance)
380{
381 assert(instance);
382#define SETUP_TRANSFER_LIST(type, name) \
383do { \
384 int ret = transfer_list_init(&instance->transfers_##type, name); \
385 if (ret != EOK) { \
386 usb_log_error("Failed to setup %s transfer list: %s.\n", \
387 name, str_error(ret)); \
388 transfer_list_fini(&instance->transfers_bulk_full); \
389 transfer_list_fini(&instance->transfers_control_full); \
390 transfer_list_fini(&instance->transfers_control_slow); \
391 transfer_list_fini(&instance->transfers_interrupt); \
392 return ret; \
393 } \
394} while (0)
395
396 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
397 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
398 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
399 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
400#undef SETUP_TRANSFER_LIST
401 /* Connect lists into one schedule */
402 transfer_list_set_next(&instance->transfers_control_full,
403 &instance->transfers_bulk_full);
404 transfer_list_set_next(&instance->transfers_control_slow,
405 &instance->transfers_control_full);
406 transfer_list_set_next(&instance->transfers_interrupt,
407 &instance->transfers_control_slow);
408
409 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
410 * buggy on certain hw, enable at your own risk. */
411#ifdef FSBR
412 transfer_list_set_next(&instance->transfers_bulk_full,
413 &instance->transfers_control_full);
414#endif
415
416 /* Assign pointers to be used during scheduling */
417 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
418 &instance->transfers_interrupt;
419 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
420 &instance->transfers_interrupt;
421 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
422 &instance->transfers_control_full;
423 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
424 &instance->transfers_control_slow;
425 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
426 &instance->transfers_bulk_full;
427
428 return EOK;
429}
430
431/** Schedule batch for execution.
432 *
433 * @param[in] instance UHCI structure to use.
434 * @param[in] batch Transfer batch to schedule.
435 * @return Error code
436 *
437 * Checks for bandwidth availability and appends the batch to the proper queue.
438 */
439int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
440{
441 assert(hcd);
442 hc_t *instance = hcd->private_data;
443 assert(instance);
444 assert(batch);
445 uhci_transfer_batch_t *uhci_batch = uhci_transfer_batch_get(batch);
446 if (!uhci_batch) {
447 usb_log_error("Failed to create UHCI transfer structures.\n");
448 return ENOMEM;
449 }
450
451 transfer_list_t *list =
452 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
453 assert(list);
454 transfer_list_add_batch(list, uhci_batch);
455
456 return EOK;
457}
458
459/** Polling function, emulates interrupts.
460 *
461 * @param[in] arg UHCI hc structure to use.
462 * @return EOK (should never return)
463 */
464int hc_interrupt_emulator(void* arg)
465{
466 usb_log_debug("Started interrupt emulator.\n");
467 hc_t *instance = arg;
468 assert(instance);
469
470 while (1) {
471 /* Read and clear status register */
472 uint16_t status = pio_read_16(&instance->registers->usbsts);
473 pio_write_16(&instance->registers->usbsts, status);
474 if (status != 0)
475 usb_log_debug2("UHCI status: %x.\n", status);
476 hc_interrupt(instance, status);
477 async_usleep(UHCI_INT_EMULATOR_TIMEOUT);
478 }
479 return EOK;
480}
481
482/** Debug function, checks consistency of memory structures.
483 *
484 * @param[in] arg UHCI structure to use.
485 * @return EOK (should never return)
486 */
487int hc_debug_checker(void *arg)
488{
489 hc_t *instance = arg;
490 assert(instance);
491
492#define QH(queue) \
493 instance->transfers_##queue.queue_head
494
495 while (1) {
496 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
497 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
498 const uint16_t intr =
499 pio_read_16(&instance->registers->usbintr);
500
501 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
502 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
503 cmd, sts, intr);
504 }
505
506 const uintptr_t frame_list =
507 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
508 if (frame_list != addr_to_phys(instance->frame_list)) {
509 usb_log_debug("Framelist address: %p vs. %p.\n",
510 (void *) frame_list,
511 (void *) addr_to_phys(instance->frame_list));
512 }
513
514 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
515
516 uintptr_t expected_pa = instance->frame_list[frnum]
517 & LINK_POINTER_ADDRESS_MASK;
518 uintptr_t real_pa = addr_to_phys(QH(interrupt));
519 if (expected_pa != real_pa) {
520 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
521 (void *) expected_pa, frnum, (void *) real_pa);
522 }
523
524 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
525 real_pa = addr_to_phys(QH(control_slow));
526 if (expected_pa != real_pa) {
527 usb_log_debug("Control Slow QH: %p vs. %p.\n",
528 (void *) expected_pa, (void *) real_pa);
529 }
530
531 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
532 real_pa = addr_to_phys(QH(control_full));
533 if (expected_pa != real_pa) {
534 usb_log_debug("Control Full QH: %p vs. %p.\n",
535 (void *) expected_pa, (void *) real_pa);
536 }
537
538 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
539 real_pa = addr_to_phys(QH(bulk_full));
540 if (expected_pa != real_pa ) {
541 usb_log_debug("Bulk QH: %p vs. %p.\n",
542 (void *) expected_pa, (void *) real_pa);
543 }
544 async_usleep(UHCI_DEBUGER_TIMEOUT);
545 }
546 return EOK;
547#undef QH
548}
549/**
550 * @}
551 */
Note: See TracBrowser for help on using the repository browser.