source: mainline/uspace/drv/bus/usb/uhci/hc.c@ 92900e2

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 92900e2 was 9f6cb910, checked in by Jan Vesely <jano.vesely@…>, 12 years ago

uhci: Add uhci_ prefix to driver interface functions.
  • Property mode set to 100644
File size: 15.2 KB
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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34
35#include <adt/list.h>
36#include <assert.h>
37#include <async.h>
38#include <ddi.h>
39#include <device/hw_res_parsed.h>
40#include <fibril.h>
41#include <errno.h>
42#include <macros.h>
43#include <mem.h>
44#include <stdlib.h>
45#include <str_error.h>
46#include <sys/types.h>
47
48#include <usb/debug.h>
49#include <usb/usb.h>
50
51#include "uhci_batch.h"
52#include "utils/malloc32.h"
53#include "hc.h"
54
55#define UHCI_INTR_ALLOW_INTERRUPTS \
56 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
57#define UHCI_STATUS_USED_INTERRUPTS \
58 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
59
60static const irq_pio_range_t uhci_irq_pio_ranges[] = {
61 {
62 .base = 0,
63 .size = sizeof(uhci_regs_t)
64 }
65};
66
67static const irq_cmd_t uhci_irq_commands[] = {
68 {
69 .cmd = CMD_PIO_READ_16,
70 .dstarg = 1,
71 .addr = NULL
72 },
73 {
74 .cmd = CMD_AND,
75 .srcarg = 1,
76 .dstarg = 2,
77 .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS
78 },
79 {
80 .cmd = CMD_PREDICATE,
81 .srcarg = 2,
82 .value = 2
83 },
84 {
85 .cmd = CMD_PIO_WRITE_A_16,
86 .srcarg = 1,
87 .addr = NULL
88 },
89 {
90 .cmd = CMD_ACCEPT
91 }
92};
93
94static void hc_init_hw(const hc_t *instance);
95static int hc_init_mem_structures(hc_t *instance);
96static int hc_init_transfer_lists(hc_t *instance);
97
98static int hc_debug_checker(void *arg);
99
100
101/** Generate IRQ code.
102 * @param[out] code IRQ code structure.
103 * @param[in] hw_res Device's resources.
104 *
105 * @return Error code.
106 */
107int uhci_hc_gen_irq_code(irq_code_t *code, const hw_res_list_parsed_t *hw_res)
108{
109 assert(code);
110 assert(hw_res);
111
112 if (hw_res->irqs.count != 1 || hw_res->io_ranges.count != 1)
113 return EINVAL;
114 const addr_range_t regs = hw_res->io_ranges.ranges[0];
115
116 if (RNGSZ(regs) < sizeof(uhci_regs_t))
117 return EOVERFLOW;
118
119 code->ranges = malloc(sizeof(uhci_irq_pio_ranges));
120 if (code->ranges == NULL)
121 return ENOMEM;
122
123 code->cmds = malloc(sizeof(uhci_irq_commands));
124 if (code->cmds == NULL) {
125 free(code->ranges);
126 return ENOMEM;
127 }
128
129 code->rangecount = ARRAY_SIZE(uhci_irq_pio_ranges);
130 code->cmdcount = ARRAY_SIZE(uhci_irq_commands);
131
132 memcpy(code->ranges, uhci_irq_pio_ranges, sizeof(uhci_irq_pio_ranges));
133 code->ranges[0].base = RNGABS(regs);
134
135 memcpy(code->cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
136 uhci_regs_t *registers = (uhci_regs_t *) RNGABSPTR(regs);
137 code->cmds[0].addr = (void*)&registers->usbsts;
138 code->cmds[3].addr = (void*)&registers->usbsts;
139
140 usb_log_debug("I/O regs at %p (size %zu), IRQ %d.\n",
141 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
142
143 return hw_res->irqs.irqs[0];
144}
145
146/** Take action based on the interrupt cause.
147 *
148 * @param[in] hcd HCD structure to use.
149 * @param[in] status Value of the status register at the time of interrupt.
150 *
151 * Interrupt might indicate:
152 * - transaction completed, either by triggering IOC, SPD, or an error
153 * - some kind of device error
154 * - resume from suspend state (not implemented)
155 */
156void uhci_hc_interrupt(hcd_t *hcd, uint32_t status)
157{
158 assert(hcd);
159 hc_t *instance = hcd->driver.data;
160 assert(instance);
161 /* Lower 2 bits are transaction error and transaction complete */
162 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
163 LIST_INITIALIZE(done);
164 transfer_list_remove_finished(
165 &instance->transfers_interrupt, &done);
166 transfer_list_remove_finished(
167 &instance->transfers_control_slow, &done);
168 transfer_list_remove_finished(
169 &instance->transfers_control_full, &done);
170 transfer_list_remove_finished(
171 &instance->transfers_bulk_full, &done);
172
173 list_foreach_safe(done, current, next) {
174 list_remove(current);
175 uhci_transfer_batch_t *batch =
176 uhci_transfer_batch_from_link(current);
177 uhci_transfer_batch_finish_dispose(batch);
178 }
179 }
180 /* Resume interrupts are not supported */
181 if (status & UHCI_STATUS_RESUME) {
182 usb_log_error("Resume interrupt!\n");
183 }
184
185 /* Bits 4 and 5 indicate hc error */
186 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
187 usb_log_error("UHCI hardware failure!.\n");
188 ++instance->hw_failures;
189 transfer_list_abort_all(&instance->transfers_interrupt);
190 transfer_list_abort_all(&instance->transfers_control_slow);
191 transfer_list_abort_all(&instance->transfers_control_full);
192 transfer_list_abort_all(&instance->transfers_bulk_full);
193
194 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
195 /* reinitialize hw, this triggers virtual disconnect*/
196 hc_init_hw(instance);
197 } else {
198 usb_log_fatal("Too many UHCI hardware failures!.\n");
199 hc_fini(instance);
200 }
201 }
202}
203
204/** Initialize UHCI hc driver structure
205 *
206 * @param[in] instance Memory place to initialize.
207 * @param[in] regs Range of device's I/O control registers.
208 * @param[in] interrupts True if hw interrupts should be used.
209 * @return Error code.
210 * @note Should be called only once on any structure.
211 *
212 * Initializes memory structures, starts up hw, and launches debugger and
213 * interrupt fibrils.
214 */
215int hc_init(hc_t *instance, const hw_res_list_parsed_t *hw_res, bool interrupts)
216{
217 assert(instance);
218 assert(hw_res);
219 if (hw_res->io_ranges.count != 1 ||
220 hw_res->io_ranges.ranges[0].size < sizeof(uhci_regs_t))
221 return EINVAL;
222
223 instance->hw_interrupts = interrupts;
224 instance->hw_failures = 0;
225
226 /* allow access to hc control registers */
227 int ret = pio_enable_range(&hw_res->io_ranges.ranges[0],
228 (void **) &instance->registers);
229 if (ret != EOK) {
230 usb_log_error("Failed to gain access to registers: %s.\n",
231 str_error(ret));
232 return ret;
233 }
234
235 usb_log_debug("Device registers at %" PRIx64 " (%zuB) accessible.\n",
236 hw_res->io_ranges.ranges[0].address.absolute,
237 hw_res->io_ranges.ranges[0].size);
238
239 ret = hc_init_mem_structures(instance);
240 if (ret != EOK) {
241 usb_log_error("Failed to init UHCI memory structures: %s.\n",
242 str_error(ret));
243 // TODO: we should disable pio here
244 return ret;
245 }
246
247 hc_init_hw(instance);
248 (void)hc_debug_checker;
249
250 uhci_rh_init(&instance->rh, instance->registers->ports, "uhci");
251
252 return EOK;
253}
254
255/** Safely dispose host controller internal structures
256 *
257 * @param[in] instance Host controller structure to use.
258 */
259void hc_fini(hc_t *instance)
260{
261 assert(instance);
262 //TODO Implement
263}
264
265/** Initialize UHCI hc hw resources.
266 *
267 * @param[in] instance UHCI structure to use.
268 * For magic values see UHCI Design Guide
269 */
270void hc_init_hw(const hc_t *instance)
271{
272 assert(instance);
273 uhci_regs_t *registers = instance->registers;
274
275 /* Reset everything, who knows what touched it before us */
276 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
277 async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
278 pio_write_16(&registers->usbcmd, 0);
279
280 /* Reset hc, all states and counters. Hope that hw is not broken */
281 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
282 do { async_usleep(10); }
283 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
284
285 /* Set frame to exactly 1ms */
286 pio_write_8(&registers->sofmod, 64);
287
288 /* Set frame list pointer */
289 const uint32_t pa = addr_to_phys(instance->frame_list);
290 pio_write_32(&registers->flbaseadd, pa);
291
292 if (instance->hw_interrupts) {
293 /* Enable all interrupts, but resume interrupt */
294 pio_write_16(&instance->registers->usbintr,
295 UHCI_INTR_ALLOW_INTERRUPTS);
296 }
297
298 const uint16_t cmd = pio_read_16(&registers->usbcmd);
299 if (cmd != 0)
300 usb_log_warning("Previous command value: %x.\n", cmd);
301
302 /* Start the hc with large(64B) packet FSBR */
303 pio_write_16(&registers->usbcmd,
304 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
305}
306
307/** Initialize UHCI hc memory structures.
308 *
309 * @param[in] instance UHCI structure to use.
310 * @return Error code
311 * @note Should be called only once on any structure.
312 *
313 * Structures:
314 * - transfer lists (queue heads need to be accessible by the hw)
315 * - frame list page (needs to be one UHCI hw accessible 4K page)
316 */
317int hc_init_mem_structures(hc_t *instance)
318{
319 assert(instance);
320
321 /* Init USB frame list page */
322 instance->frame_list = get_page();
323 if (!instance->frame_list) {
324 return ENOMEM;
325 }
326 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
327
328 /* Init transfer lists */
329 int ret = hc_init_transfer_lists(instance);
330 if (ret != EOK) {
331 usb_log_error("Failed to initialize transfer lists.\n");
332 return_page(instance->frame_list);
333 return ENOMEM;
334 }
335 usb_log_debug("Initialized transfer lists.\n");
336
337
338 /* Set all frames to point to the first queue head */
339 const uint32_t queue = LINK_POINTER_QH(
340 addr_to_phys(instance->transfers_interrupt.queue_head));
341
342 for (unsigned i = 0; i < UHCI_FRAME_LIST_COUNT; ++i) {
343 instance->frame_list[i] = queue;
344 }
345
346 return EOK;
347}
348
349/** Initialize UHCI hc transfer lists.
350 *
351 * @param[in] instance UHCI structure to use.
352 * @return Error code
353 * @note Should be called only once on any structure.
354 *
355 * Initializes transfer lists and sets them in one chain to support proper
356 * USB scheduling. Sets pointer table for quick access.
357 */
358int hc_init_transfer_lists(hc_t *instance)
359{
360 assert(instance);
361#define SETUP_TRANSFER_LIST(type, name) \
362do { \
363 int ret = transfer_list_init(&instance->transfers_##type, name); \
364 if (ret != EOK) { \
365 usb_log_error("Failed to setup %s transfer list: %s.\n", \
366 name, str_error(ret)); \
367 transfer_list_fini(&instance->transfers_bulk_full); \
368 transfer_list_fini(&instance->transfers_control_full); \
369 transfer_list_fini(&instance->transfers_control_slow); \
370 transfer_list_fini(&instance->transfers_interrupt); \
371 return ret; \
372 } \
373} while (0)
374
375 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
376 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
377 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
378 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
379#undef SETUP_TRANSFER_LIST
380 /* Connect lists into one schedule */
381 transfer_list_set_next(&instance->transfers_control_full,
382 &instance->transfers_bulk_full);
383 transfer_list_set_next(&instance->transfers_control_slow,
384 &instance->transfers_control_full);
385 transfer_list_set_next(&instance->transfers_interrupt,
386 &instance->transfers_control_slow);
387
388 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
389 * buggy on certain hw, enable at your own risk. */
390#ifdef FSBR
391 transfer_list_set_next(&instance->transfers_bulk_full,
392 &instance->transfers_control_full);
393#endif
394
395 /* Assign pointers to be used during scheduling */
396 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
397 &instance->transfers_interrupt;
398 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
399 &instance->transfers_interrupt;
400 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
401 &instance->transfers_control_full;
402 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
403 &instance->transfers_control_slow;
404 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
405 &instance->transfers_bulk_full;
406
407 return EOK;
408}
409
410int uhci_hc_status(hcd_t *hcd, uint32_t *status)
411{
412 assert(hcd);
413 assert(status);
414 hc_t *instance = hcd->driver.data;
415 assert(instance);
416
417 *status = 0;
418 if (instance->registers) {
419 uint16_t s = pio_read_16(&instance->registers->usbsts);
420 pio_write_16(&instance->registers->usbsts, s);
421 *status = s;
422 }
423 return EOK;
424}
425
426/** Schedule batch for execution.
427 *
428 * @param[in] instance UHCI structure to use.
429 * @param[in] batch Transfer batch to schedule.
430 * @return Error code
431 *
432 * Checks for bandwidth availability and appends the batch to the proper queue.
433 */
434int uhci_hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
435{
436 assert(hcd);
437 hc_t *instance = hcd->driver.data;
438 assert(instance);
439 assert(batch);
440
441 if (batch->ep->address == uhci_rh_get_address(&instance->rh))
442 return uhci_rh_schedule(&instance->rh, batch);
443
444 uhci_transfer_batch_t *uhci_batch = uhci_transfer_batch_get(batch);
445 if (!uhci_batch) {
446 usb_log_error("Failed to create UHCI transfer structures.\n");
447 return ENOMEM;
448 }
449
450 transfer_list_t *list =
451 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
452 assert(list);
453 transfer_list_add_batch(list, uhci_batch);
454
455 return EOK;
456}
457
458/** Debug function, checks consistency of memory structures.
459 *
460 * @param[in] arg UHCI structure to use.
461 * @return EOK (should never return)
462 */
463int hc_debug_checker(void *arg)
464{
465 hc_t *instance = arg;
466 assert(instance);
467
468#define QH(queue) \
469 instance->transfers_##queue.queue_head
470
471 while (1) {
472 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
473 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
474 const uint16_t intr =
475 pio_read_16(&instance->registers->usbintr);
476
477 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
478 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
479 cmd, sts, intr);
480 }
481
482 const uintptr_t frame_list =
483 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
484 if (frame_list != addr_to_phys(instance->frame_list)) {
485 usb_log_debug("Framelist address: %p vs. %p.\n",
486 (void *) frame_list,
487 (void *) addr_to_phys(instance->frame_list));
488 }
489
490 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
491
492 uintptr_t expected_pa = instance->frame_list[frnum]
493 & LINK_POINTER_ADDRESS_MASK;
494 uintptr_t real_pa = addr_to_phys(QH(interrupt));
495 if (expected_pa != real_pa) {
496 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
497 (void *) expected_pa, frnum, (void *) real_pa);
498 }
499
500 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
501 real_pa = addr_to_phys(QH(control_slow));
502 if (expected_pa != real_pa) {
503 usb_log_debug("Control Slow QH: %p vs. %p.\n",
504 (void *) expected_pa, (void *) real_pa);
505 }
506
507 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
508 real_pa = addr_to_phys(QH(control_full));
509 if (expected_pa != real_pa) {
510 usb_log_debug("Control Full QH: %p vs. %p.\n",
511 (void *) expected_pa, (void *) real_pa);
512 }
513
514 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
515 real_pa = addr_to_phys(QH(bulk_full));
516 if (expected_pa != real_pa ) {
517 usb_log_debug("Bulk QH: %p vs. %p.\n",
518 (void *) expected_pa, (void *) real_pa);
519 }
520 async_usleep(UHCI_DEBUGER_TIMEOUT);
521 }
522 return EOK;
523#undef QH
524}
525/**
526 * @}
527 */
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