source: mainline/uspace/drv/bus/usb/uhci/hc.c@ 8d2dd7f2

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 8d2dd7f2 was 8d2dd7f2, checked in by Jakub Jermar <jakub@…>, 8 years ago

Reduce the number of files that include <sys/types.h>
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File size: 15.3 KB
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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbuhcihc
30 * @{
31 */
32/** @file
33 * @brief UHCI Host controller driver routines
34 */
35
36#include <adt/list.h>
37#include <assert.h>
38#include <async.h>
39#include <ddi.h>
40#include <device/hw_res_parsed.h>
41#include <fibril.h>
42#include <errno.h>
43#include <macros.h>
44#include <mem.h>
45#include <stdlib.h>
46#include <stdint.h>
47#include <str_error.h>
48
49#include <usb/debug.h>
50#include <usb/usb.h>
51#include <usb/host/utils/malloc32.h>
52
53#include "uhci_batch.h"
54#include "hc.h"
55
56#define UHCI_INTR_ALLOW_INTERRUPTS \
57 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
58#define UHCI_STATUS_USED_INTERRUPTS \
59 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
60
61static const irq_pio_range_t uhci_irq_pio_ranges[] = {
62 {
63 .base = 0,
64 .size = sizeof(uhci_regs_t)
65 }
66};
67
68static const irq_cmd_t uhci_irq_commands[] = {
69 {
70 .cmd = CMD_PIO_READ_16,
71 .dstarg = 1,
72 .addr = NULL
73 },
74 {
75 .cmd = CMD_AND,
76 .srcarg = 1,
77 .dstarg = 2,
78 .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS
79 },
80 {
81 .cmd = CMD_PREDICATE,
82 .srcarg = 2,
83 .value = 2
84 },
85 {
86 .cmd = CMD_PIO_WRITE_A_16,
87 .srcarg = 1,
88 .addr = NULL
89 },
90 {
91 .cmd = CMD_ACCEPT
92 }
93};
94
95static void hc_init_hw(const hc_t *instance);
96static int hc_init_mem_structures(hc_t *instance);
97static int hc_init_transfer_lists(hc_t *instance);
98
99static int hc_debug_checker(void *arg);
100
101
102/** Generate IRQ code.
103 * @param[out] code IRQ code structure.
104 * @param[in] hw_res Device's resources.
105 *
106 * @return Error code.
107 */
108int uhci_hc_gen_irq_code(irq_code_t *code, const hw_res_list_parsed_t *hw_res)
109{
110 assert(code);
111 assert(hw_res);
112
113 if (hw_res->irqs.count != 1 || hw_res->io_ranges.count != 1)
114 return EINVAL;
115 const addr_range_t regs = hw_res->io_ranges.ranges[0];
116
117 if (RNGSZ(regs) < sizeof(uhci_regs_t))
118 return EOVERFLOW;
119
120 code->ranges = malloc(sizeof(uhci_irq_pio_ranges));
121 if (code->ranges == NULL)
122 return ENOMEM;
123
124 code->cmds = malloc(sizeof(uhci_irq_commands));
125 if (code->cmds == NULL) {
126 free(code->ranges);
127 return ENOMEM;
128 }
129
130 code->rangecount = ARRAY_SIZE(uhci_irq_pio_ranges);
131 code->cmdcount = ARRAY_SIZE(uhci_irq_commands);
132
133 memcpy(code->ranges, uhci_irq_pio_ranges, sizeof(uhci_irq_pio_ranges));
134 code->ranges[0].base = RNGABS(regs);
135
136 memcpy(code->cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
137 uhci_regs_t *registers = (uhci_regs_t *) RNGABSPTR(regs);
138 code->cmds[0].addr = (void*)&registers->usbsts;
139 code->cmds[3].addr = (void*)&registers->usbsts;
140
141 usb_log_debug("I/O regs at %p (size %zu), IRQ %d.\n",
142 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
143
144 return hw_res->irqs.irqs[0];
145}
146
147/** Take action based on the interrupt cause.
148 *
149 * @param[in] hcd HCD structure to use.
150 * @param[in] status Value of the status register at the time of interrupt.
151 *
152 * Interrupt might indicate:
153 * - transaction completed, either by triggering IOC, SPD, or an error
154 * - some kind of device error
155 * - resume from suspend state (not implemented)
156 */
157void uhci_hc_interrupt(hcd_t *hcd, uint32_t status)
158{
159 assert(hcd);
160 hc_t *instance = hcd_get_driver_data(hcd);
161 assert(instance);
162 /* Lower 2 bits are transaction error and transaction complete */
163 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
164 LIST_INITIALIZE(done);
165 transfer_list_remove_finished(
166 &instance->transfers_interrupt, &done);
167 transfer_list_remove_finished(
168 &instance->transfers_control_slow, &done);
169 transfer_list_remove_finished(
170 &instance->transfers_control_full, &done);
171 transfer_list_remove_finished(
172 &instance->transfers_bulk_full, &done);
173
174 list_foreach_safe(done, current, next) {
175 list_remove(current);
176 uhci_transfer_batch_t *batch =
177 uhci_transfer_batch_from_link(current);
178 uhci_transfer_batch_finish_dispose(batch);
179 }
180 }
181 /* Resume interrupts are not supported */
182 if (status & UHCI_STATUS_RESUME) {
183 usb_log_error("Resume interrupt!\n");
184 }
185
186 /* Bits 4 and 5 indicate hc error */
187 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
188 usb_log_error("UHCI hardware failure!.\n");
189 ++instance->hw_failures;
190 transfer_list_abort_all(&instance->transfers_interrupt);
191 transfer_list_abort_all(&instance->transfers_control_slow);
192 transfer_list_abort_all(&instance->transfers_control_full);
193 transfer_list_abort_all(&instance->transfers_bulk_full);
194
195 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
196 /* reinitialize hw, this triggers virtual disconnect*/
197 hc_init_hw(instance);
198 } else {
199 usb_log_fatal("Too many UHCI hardware failures!.\n");
200 hc_fini(instance);
201 }
202 }
203}
204
205/** Initialize UHCI hc driver structure
206 *
207 * @param[in] instance Memory place to initialize.
208 * @param[in] regs Range of device's I/O control registers.
209 * @param[in] interrupts True if hw interrupts should be used.
210 * @return Error code.
211 * @note Should be called only once on any structure.
212 *
213 * Initializes memory structures, starts up hw, and launches debugger and
214 * interrupt fibrils.
215 */
216int hc_init(hc_t *instance, const hw_res_list_parsed_t *hw_res, bool interrupts)
217{
218 assert(instance);
219 assert(hw_res);
220 if (hw_res->io_ranges.count != 1 ||
221 hw_res->io_ranges.ranges[0].size < sizeof(uhci_regs_t))
222 return EINVAL;
223
224 instance->hw_interrupts = interrupts;
225 instance->hw_failures = 0;
226
227 /* allow access to hc control registers */
228 int ret = pio_enable_range(&hw_res->io_ranges.ranges[0],
229 (void **) &instance->registers);
230 if (ret != EOK) {
231 usb_log_error("Failed to gain access to registers: %s.\n",
232 str_error(ret));
233 return ret;
234 }
235
236 usb_log_debug("Device registers at %" PRIx64 " (%zuB) accessible.\n",
237 hw_res->io_ranges.ranges[0].address.absolute,
238 hw_res->io_ranges.ranges[0].size);
239
240 ret = hc_init_mem_structures(instance);
241 if (ret != EOK) {
242 usb_log_error("Failed to init UHCI memory structures: %s.\n",
243 str_error(ret));
244 // TODO: we should disable pio here
245 return ret;
246 }
247
248 hc_init_hw(instance);
249 (void)hc_debug_checker;
250
251 uhci_rh_init(&instance->rh, instance->registers->ports, "uhci");
252
253 return EOK;
254}
255
256/** Safely dispose host controller internal structures
257 *
258 * @param[in] instance Host controller structure to use.
259 */
260void hc_fini(hc_t *instance)
261{
262 assert(instance);
263 //TODO Implement
264}
265
266/** Initialize UHCI hc hw resources.
267 *
268 * @param[in] instance UHCI structure to use.
269 * For magic values see UHCI Design Guide
270 */
271void hc_init_hw(const hc_t *instance)
272{
273 assert(instance);
274 uhci_regs_t *registers = instance->registers;
275
276 /* Reset everything, who knows what touched it before us */
277 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
278 async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
279 pio_write_16(&registers->usbcmd, 0);
280
281 /* Reset hc, all states and counters. Hope that hw is not broken */
282 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
283 do { async_usleep(10); }
284 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
285
286 /* Set frame to exactly 1ms */
287 pio_write_8(&registers->sofmod, 64);
288
289 /* Set frame list pointer */
290 const uint32_t pa = addr_to_phys(instance->frame_list);
291 pio_write_32(&registers->flbaseadd, pa);
292
293 if (instance->hw_interrupts) {
294 /* Enable all interrupts, but resume interrupt */
295 pio_write_16(&instance->registers->usbintr,
296 UHCI_INTR_ALLOW_INTERRUPTS);
297 }
298
299 const uint16_t cmd = pio_read_16(&registers->usbcmd);
300 if (cmd != 0)
301 usb_log_warning("Previous command value: %x.\n", cmd);
302
303 /* Start the hc with large(64B) packet FSBR */
304 pio_write_16(&registers->usbcmd,
305 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
306}
307
308/** Initialize UHCI hc memory structures.
309 *
310 * @param[in] instance UHCI structure to use.
311 * @return Error code
312 * @note Should be called only once on any structure.
313 *
314 * Structures:
315 * - transfer lists (queue heads need to be accessible by the hw)
316 * - frame list page (needs to be one UHCI hw accessible 4K page)
317 */
318int hc_init_mem_structures(hc_t *instance)
319{
320 assert(instance);
321
322 /* Init USB frame list page */
323 instance->frame_list = get_page();
324 if (!instance->frame_list) {
325 return ENOMEM;
326 }
327 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
328
329 /* Init transfer lists */
330 int ret = hc_init_transfer_lists(instance);
331 if (ret != EOK) {
332 usb_log_error("Failed to initialize transfer lists.\n");
333 return_page(instance->frame_list);
334 return ENOMEM;
335 }
336 usb_log_debug("Initialized transfer lists.\n");
337
338
339 /* Set all frames to point to the first queue head */
340 const uint32_t queue = LINK_POINTER_QH(
341 addr_to_phys(instance->transfers_interrupt.queue_head));
342
343 for (unsigned i = 0; i < UHCI_FRAME_LIST_COUNT; ++i) {
344 instance->frame_list[i] = queue;
345 }
346
347 return EOK;
348}
349
350/** Initialize UHCI hc transfer lists.
351 *
352 * @param[in] instance UHCI structure to use.
353 * @return Error code
354 * @note Should be called only once on any structure.
355 *
356 * Initializes transfer lists and sets them in one chain to support proper
357 * USB scheduling. Sets pointer table for quick access.
358 */
359int hc_init_transfer_lists(hc_t *instance)
360{
361 assert(instance);
362#define SETUP_TRANSFER_LIST(type, name) \
363do { \
364 int ret = transfer_list_init(&instance->transfers_##type, name); \
365 if (ret != EOK) { \
366 usb_log_error("Failed to setup %s transfer list: %s.\n", \
367 name, str_error(ret)); \
368 transfer_list_fini(&instance->transfers_bulk_full); \
369 transfer_list_fini(&instance->transfers_control_full); \
370 transfer_list_fini(&instance->transfers_control_slow); \
371 transfer_list_fini(&instance->transfers_interrupt); \
372 return ret; \
373 } \
374} while (0)
375
376 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
377 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
378 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
379 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
380#undef SETUP_TRANSFER_LIST
381 /* Connect lists into one schedule */
382 transfer_list_set_next(&instance->transfers_control_full,
383 &instance->transfers_bulk_full);
384 transfer_list_set_next(&instance->transfers_control_slow,
385 &instance->transfers_control_full);
386 transfer_list_set_next(&instance->transfers_interrupt,
387 &instance->transfers_control_slow);
388
389 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
390 * buggy on certain hw, enable at your own risk. */
391#ifdef FSBR
392 transfer_list_set_next(&instance->transfers_bulk_full,
393 &instance->transfers_control_full);
394#endif
395
396 /* Assign pointers to be used during scheduling */
397 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
398 &instance->transfers_interrupt;
399 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
400 &instance->transfers_interrupt;
401 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
402 &instance->transfers_control_full;
403 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
404 &instance->transfers_control_slow;
405 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
406 &instance->transfers_bulk_full;
407
408 return EOK;
409}
410
411int uhci_hc_status(hcd_t *hcd, uint32_t *status)
412{
413 assert(hcd);
414 assert(status);
415 hc_t *instance = hcd_get_driver_data(hcd);
416 assert(instance);
417
418 *status = 0;
419 if (instance->registers) {
420 uint16_t s = pio_read_16(&instance->registers->usbsts);
421 pio_write_16(&instance->registers->usbsts, s);
422 *status = s;
423 }
424 return EOK;
425}
426
427/** Schedule batch for execution.
428 *
429 * @param[in] instance UHCI structure to use.
430 * @param[in] batch Transfer batch to schedule.
431 * @return Error code
432 *
433 * Checks for bandwidth availability and appends the batch to the proper queue.
434 */
435int uhci_hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
436{
437 assert(hcd);
438 hc_t *instance = hcd_get_driver_data(hcd);
439 assert(instance);
440 assert(batch);
441
442 if (batch->ep->address == uhci_rh_get_address(&instance->rh))
443 return uhci_rh_schedule(&instance->rh, batch);
444
445 uhci_transfer_batch_t *uhci_batch = uhci_transfer_batch_get(batch);
446 if (!uhci_batch) {
447 usb_log_error("Failed to create UHCI transfer structures.\n");
448 return ENOMEM;
449 }
450
451 transfer_list_t *list =
452 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
453 assert(list);
454 transfer_list_add_batch(list, uhci_batch);
455
456 return EOK;
457}
458
459/** Debug function, checks consistency of memory structures.
460 *
461 * @param[in] arg UHCI structure to use.
462 * @return EOK (should never return)
463 */
464int hc_debug_checker(void *arg)
465{
466 hc_t *instance = arg;
467 assert(instance);
468
469#define QH(queue) \
470 instance->transfers_##queue.queue_head
471
472 while (1) {
473 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
474 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
475 const uint16_t intr =
476 pio_read_16(&instance->registers->usbintr);
477
478 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
479 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
480 cmd, sts, intr);
481 }
482
483 const uintptr_t frame_list =
484 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
485 if (frame_list != addr_to_phys(instance->frame_list)) {
486 usb_log_debug("Framelist address: %p vs. %p.\n",
487 (void *) frame_list,
488 (void *) addr_to_phys(instance->frame_list));
489 }
490
491 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
492
493 uintptr_t expected_pa = instance->frame_list[frnum]
494 & LINK_POINTER_ADDRESS_MASK;
495 uintptr_t real_pa = addr_to_phys(QH(interrupt));
496 if (expected_pa != real_pa) {
497 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
498 (void *) expected_pa, frnum, (void *) real_pa);
499 }
500
501 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
502 real_pa = addr_to_phys(QH(control_slow));
503 if (expected_pa != real_pa) {
504 usb_log_debug("Control Slow QH: %p vs. %p.\n",
505 (void *) expected_pa, (void *) real_pa);
506 }
507
508 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
509 real_pa = addr_to_phys(QH(control_full));
510 if (expected_pa != real_pa) {
511 usb_log_debug("Control Full QH: %p vs. %p.\n",
512 (void *) expected_pa, (void *) real_pa);
513 }
514
515 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
516 real_pa = addr_to_phys(QH(bulk_full));
517 if (expected_pa != real_pa ) {
518 usb_log_debug("Bulk QH: %p vs. %p.\n",
519 (void *) expected_pa, (void *) real_pa);
520 }
521 async_usleep(UHCI_DEBUGER_TIMEOUT);
522 }
523 return EOK;
524#undef QH
525}
526/**
527 * @}
528 */
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