source: mainline/uspace/drv/bus/usb/uhci/hc.c@ 83c3123

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 83c3123 was 75f9dcd, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

uhci: Declare iteration variables inside for loops.

Fix typo.
  • Property mode set to 100644
File size: 15.8 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41
42#include "hc.h"
43#include "uhci_batch.h"
44
45#define UHCI_INTR_ALLOW_INTERRUPTS \
46 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
47#define UHCI_STATUS_USED_INTERRUPTS \
48 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
49
50
51static const irq_cmd_t uhci_irq_commands[] =
52{
53 { .cmd = CMD_PIO_READ_16, .dstarg = 1, .addr = NULL/*filled later*/},
54 { .cmd = CMD_BTEST, .srcarg = 1, .dstarg = 2,
55 .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS },
56 { .cmd = CMD_PREDICATE, .srcarg = 2, .value = 2 },
57 { .cmd = CMD_PIO_WRITE_A_16, .srcarg = 1, .addr = NULL/*filled later*/},
58 { .cmd = CMD_ACCEPT },
59};
60
61static void hc_init_hw(const hc_t *instance);
62static int hc_init_mem_structures(hc_t *instance);
63static int hc_init_transfer_lists(hc_t *instance);
64static int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch);
65
66static int hc_interrupt_emulator(void *arg);
67static int hc_debug_checker(void *arg);
68
69/*----------------------------------------------------------------------------*/
70/** Get number of commands used in IRQ code.
71 * @return Number of commands.
72 */
73size_t hc_irq_cmd_count(void)
74{
75 return sizeof(uhci_irq_commands) / sizeof(irq_cmd_t);
76}
77/*----------------------------------------------------------------------------*/
78/** Generate IRQ code commands.
79 * @param[out] cmds Place to store the commands.
80 * @param[in] cmd_size Size of the place (bytes).
81 * @param[in] regs Physical address of device's registers.
82 * @param[in] reg_size Size of the register area (bytes).
83 *
84 * @return Error code.
85 */
86int hc_get_irq_commands(
87 irq_cmd_t cmds[], size_t cmd_size, uintptr_t regs, size_t reg_size)
88{
89 if (cmd_size < sizeof(uhci_irq_commands)
90 || reg_size < sizeof(uhci_regs_t))
91 return EOVERFLOW;
92
93 uhci_regs_t *registers = (uhci_regs_t*)regs;
94
95 memcpy(cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
96
97 cmds[0].addr = (void*)&registers->usbsts;
98 cmds[3].addr = (void*)&registers->usbsts;
99 return EOK;
100}
101/*----------------------------------------------------------------------------*/
102/** Take action based on the interrupt cause.
103 *
104 * @param[in] instance UHCI structure to use.
105 * @param[in] status Value of the status register at the time of interrupt.
106 *
107 * Interrupt might indicate:
108 * - transaction completed, either by triggering IOC, SPD, or an error
109 * - some kind of device error
110 * - resume from suspend state (not implemented)
111 */
112void hc_interrupt(hc_t *instance, uint16_t status)
113{
114 assert(instance);
115 /* Lower 2 bits are transaction error and transaction complete */
116 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
117 LIST_INITIALIZE(done);
118 transfer_list_remove_finished(
119 &instance->transfers_interrupt, &done);
120 transfer_list_remove_finished(
121 &instance->transfers_control_slow, &done);
122 transfer_list_remove_finished(
123 &instance->transfers_control_full, &done);
124 transfer_list_remove_finished(
125 &instance->transfers_bulk_full, &done);
126
127 while (!list_empty(&done)) {
128 link_t *item = list_first(&done);
129 list_remove(item);
130 uhci_transfer_batch_t *batch =
131 uhci_transfer_batch_from_link(item);
132 uhci_transfer_batch_call_dispose(batch);
133 }
134 }
135 /* Resume interrupts are not supported */
136 if (status & UHCI_STATUS_RESUME) {
137 usb_log_error("Resume interrupt!\n");
138 }
139
140 /* Bits 4 and 5 indicate hc error */
141 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
142 usb_log_error("UHCI hardware failure!.\n");
143 ++instance->hw_failures;
144 transfer_list_abort_all(&instance->transfers_interrupt);
145 transfer_list_abort_all(&instance->transfers_control_slow);
146 transfer_list_abort_all(&instance->transfers_control_full);
147 transfer_list_abort_all(&instance->transfers_bulk_full);
148
149 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
150 /* reinitialize hw, this triggers virtual disconnect*/
151 hc_init_hw(instance);
152 } else {
153 usb_log_fatal("Too many UHCI hardware failures!.\n");
154 hc_fini(instance);
155 }
156 }
157}
158/*----------------------------------------------------------------------------*/
159/** Initialize UHCI hc driver structure
160 *
161 * @param[in] instance Memory place to initialize.
162 * @param[in] regs Address of I/O control registers.
163 * @param[in] reg_size Size of I/O control registers.
164 * @param[in] interrupts True if hw interrupts should be used.
165 * @return Error code.
166 * @note Should be called only once on any structure.
167 *
168 * Initializes memory structures, starts up hw, and launches debugger and
169 * interrupt fibrils.
170 */
171int hc_init(hc_t *instance, void *regs, size_t reg_size, bool interrupts)
172{
173 assert(reg_size >= sizeof(uhci_regs_t));
174 int ret;
175
176#define CHECK_RET_RETURN(ret, message...) \
177 if (ret != EOK) { \
178 usb_log_error(message); \
179 return ret; \
180 } else (void) 0
181
182 instance->hw_interrupts = interrupts;
183 instance->hw_failures = 0;
184
185 /* allow access to hc control registers */
186 uhci_regs_t *io;
187 ret = pio_enable(regs, reg_size, (void **)&io);
188 CHECK_RET_RETURN(ret, "Failed to gain access to registers at %p: %s.\n",
189 io, str_error(ret));
190 instance->registers = io;
191 usb_log_debug(
192 "Device registers at %p (%zuB) accessible.\n", io, reg_size);
193
194 ret = hcd_init(&instance->generic, BANDWIDTH_AVAILABLE_USB11,
195 bandwidth_count_usb11);
196 CHECK_RET_RETURN(ret, "Failed to initialize HCD generic driver: %s.\n",
197 str_error(ret));
198
199 instance->generic.private_data = instance;
200 instance->generic.schedule = hc_schedule;
201 instance->generic.ep_add_hook = NULL;
202
203#undef CHECK_RET_DEST_FUN_RETURN
204
205 ret = hc_init_mem_structures(instance);
206 if (ret != EOK) {
207 usb_log_error(
208 "Failed to initialize UHCI memory structures: %s.\n",
209 str_error(ret));
210 hcd_destroy(&instance->generic);
211 return ret;
212 }
213
214 hc_init_hw(instance);
215 if (!interrupts) {
216 instance->interrupt_emulator =
217 fibril_create(hc_interrupt_emulator, instance);
218 fibril_add_ready(instance->interrupt_emulator);
219 }
220 (void)hc_debug_checker;
221
222 return EOK;
223}
224/*----------------------------------------------------------------------------*/
225/** Initialize UHCI hc hw resources.
226 *
227 * @param[in] instance UHCI structure to use.
228 * For magic values see UHCI Design Guide
229 */
230void hc_init_hw(const hc_t *instance)
231{
232 assert(instance);
233 uhci_regs_t *registers = instance->registers;
234
235 /* Reset everything, who knows what touched it before us */
236 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
237 async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
238 pio_write_16(&registers->usbcmd, 0);
239
240 /* Reset hc, all states and counters. Hope that hw is not broken */
241 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
242 do { async_usleep(10); }
243 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
244
245 /* Set frame to exactly 1ms */
246 pio_write_8(&registers->sofmod, 64);
247
248 /* Set frame list pointer */
249 const uint32_t pa = addr_to_phys(instance->frame_list);
250 pio_write_32(&registers->flbaseadd, pa);
251
252 if (instance->hw_interrupts) {
253 /* Enable all interrupts, but resume interrupt */
254 pio_write_16(&instance->registers->usbintr,
255 UHCI_INTR_ALLOW_INTERRUPTS);
256 }
257
258 const uint16_t cmd = pio_read_16(&registers->usbcmd);
259 if (cmd != 0)
260 usb_log_warning("Previous command value: %x.\n", cmd);
261
262 /* Start the hc with large(64B) packet FSBR */
263 pio_write_16(&registers->usbcmd,
264 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
265}
266/*----------------------------------------------------------------------------*/
267/** Initialize UHCI hc memory structures.
268 *
269 * @param[in] instance UHCI structure to use.
270 * @return Error code
271 * @note Should be called only once on any structure.
272 *
273 * Structures:
274 * - transfer lists (queue heads need to be accessible by the hw)
275 * - frame list page (needs to be one UHCI hw accessible 4K page)
276 */
277int hc_init_mem_structures(hc_t *instance)
278{
279 assert(instance);
280
281 /* Init USB frame list page */
282 instance->frame_list = get_page();
283 if (!instance->frame_list) {
284 return ENOMEM;
285 }
286 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
287
288 /* Init transfer lists */
289 int ret = hc_init_transfer_lists(instance);
290 if (ret != EOK) {
291 usb_log_error("Failed to initialize transfer lists.\n");
292 return_page(instance->frame_list);
293 return ENOMEM;
294 }
295 usb_log_debug("Initialized transfer lists.\n");
296
297
298 /* Set all frames to point to the first queue head */
299 const uint32_t queue = LINK_POINTER_QH(
300 addr_to_phys(instance->transfers_interrupt.queue_head));
301
302 for (unsigned i = 0; i < UHCI_FRAME_LIST_COUNT; ++i) {
303 instance->frame_list[i] = queue;
304 }
305
306 return EOK;
307}
308/*----------------------------------------------------------------------------*/
309/** Initialize UHCI hc transfer lists.
310 *
311 * @param[in] instance UHCI structure to use.
312 * @return Error code
313 * @note Should be called only once on any structure.
314 *
315 * Initializes transfer lists and sets them in one chain to support proper
316 * USB scheduling. Sets pointer table for quick access.
317 */
318int hc_init_transfer_lists(hc_t *instance)
319{
320 assert(instance);
321#define SETUP_TRANSFER_LIST(type, name) \
322do { \
323 int ret = transfer_list_init(&instance->transfers_##type, name); \
324 if (ret != EOK) { \
325 usb_log_error("Failed to setup %s transfer list: %s.\n", \
326 name, str_error(ret)); \
327 transfer_list_fini(&instance->transfers_bulk_full); \
328 transfer_list_fini(&instance->transfers_control_full); \
329 transfer_list_fini(&instance->transfers_control_slow); \
330 transfer_list_fini(&instance->transfers_interrupt); \
331 return ret; \
332 } \
333} while (0)
334
335 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
336 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
337 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
338 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
339#undef SETUP_TRANSFER_LIST
340 /* Connect lists into one schedule */
341 transfer_list_set_next(&instance->transfers_control_full,
342 &instance->transfers_bulk_full);
343 transfer_list_set_next(&instance->transfers_control_slow,
344 &instance->transfers_control_full);
345 transfer_list_set_next(&instance->transfers_interrupt,
346 &instance->transfers_control_slow);
347
348 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
349 * buggy on certain hw, enable at your own risk. */
350#ifdef FSBR
351 transfer_list_set_next(&instance->transfers_bulk_full,
352 &instance->transfers_control_full);
353#endif
354
355 /* Assign pointers to be used during scheduling */
356 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
357 &instance->transfers_interrupt;
358 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
359 &instance->transfers_interrupt;
360 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
361 &instance->transfers_control_full;
362 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
363 &instance->transfers_control_slow;
364 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
365 &instance->transfers_bulk_full;
366
367 return EOK;
368#undef CHECK_RET_CLEAR_RETURN
369}
370/*----------------------------------------------------------------------------*/
371/** Schedule batch for execution.
372 *
373 * @param[in] instance UHCI structure to use.
374 * @param[in] batch Transfer batch to schedule.
375 * @return Error code
376 *
377 * Checks for bandwidth availability and appends the batch to the proper queue.
378 */
379int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
380{
381 assert(hcd);
382 hc_t *instance = hcd->private_data;
383 assert(instance);
384 assert(batch);
385 uhci_transfer_batch_t *uhci_batch = uhci_transfer_batch_get(batch);
386 if (!uhci_batch) {
387 usb_log_error("Failed to create UHCI transfer structures.\n");
388 return ENOMEM;
389 }
390
391 transfer_list_t *list =
392 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
393 assert(list);
394 transfer_list_add_batch(list, uhci_batch);
395
396 return EOK;
397}
398/*----------------------------------------------------------------------------*/
399/** Polling function, emulates interrupts.
400 *
401 * @param[in] arg UHCI hc structure to use.
402 * @return EOK (should never return)
403 */
404int hc_interrupt_emulator(void* arg)
405{
406 usb_log_debug("Started interrupt emulator.\n");
407 hc_t *instance = arg;
408 assert(instance);
409
410 while (1) {
411 /* Read and clear status register */
412 uint16_t status = pio_read_16(&instance->registers->usbsts);
413 pio_write_16(&instance->registers->usbsts, status);
414 if (status != 0)
415 usb_log_debug2("UHCI status: %x.\n", status);
416 hc_interrupt(instance, status);
417 async_usleep(UHCI_INT_EMULATOR_TIMEOUT);
418 }
419 return EOK;
420}
421/*----------------------------------------------------------------------------*/
422/** Debug function, checks consistency of memory structures.
423 *
424 * @param[in] arg UHCI structure to use.
425 * @return EOK (should never return)
426 */
427int hc_debug_checker(void *arg)
428{
429 hc_t *instance = arg;
430 assert(instance);
431
432#define QH(queue) \
433 instance->transfers_##queue.queue_head
434
435 while (1) {
436 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
437 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
438 const uint16_t intr =
439 pio_read_16(&instance->registers->usbintr);
440
441 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
442 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
443 cmd, sts, intr);
444 }
445
446 const uintptr_t frame_list =
447 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
448 if (frame_list != addr_to_phys(instance->frame_list)) {
449 usb_log_debug("Framelist address: %p vs. %p.\n",
450 (void *) frame_list,
451 (void *) addr_to_phys(instance->frame_list));
452 }
453
454 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
455
456 uintptr_t expected_pa = instance->frame_list[frnum]
457 & LINK_POINTER_ADDRESS_MASK;
458 uintptr_t real_pa = addr_to_phys(QH(interrupt));
459 if (expected_pa != real_pa) {
460 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
461 (void *) expected_pa, frnum, (void *) real_pa);
462 }
463
464 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
465 real_pa = addr_to_phys(QH(control_slow));
466 if (expected_pa != real_pa) {
467 usb_log_debug("Control Slow QH: %p vs. %p.\n",
468 (void *) expected_pa, (void *) real_pa);
469 }
470
471 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
472 real_pa = addr_to_phys(QH(control_full));
473 if (expected_pa != real_pa) {
474 usb_log_debug("Control Full QH: %p vs. %p.\n",
475 (void *) expected_pa, (void *) real_pa);
476 }
477
478 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
479 real_pa = addr_to_phys(QH(bulk_full));
480 if (expected_pa != real_pa ) {
481 usb_log_debug("Bulk QH: %p vs. %p.\n",
482 (void *) expected_pa, (void *) real_pa);
483 }
484 async_usleep(UHCI_DEBUGER_TIMEOUT);
485 }
486 return EOK;
487#undef QH
488}
489/**
490 * @}
491 */
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