source: mainline/uspace/drv/bus/usb/uhci/hc.c@ 8064c2f6

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 8064c2f6 was 8064c2f6, checked in by Jan Vesely <jano.vesely@…>, 12 years ago

uhci: Sanitize headers.

Include what you use.
  • Property mode set to 100644
File size: 15.0 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34
35#include <adt/list.h>
36#include <assert.h>
37#include <async.h>
38#include <ddi.h>
39#include <device/hw_res_parsed.h>
40#include <fibril.h>
41#include <errno.h>
42#include <macros.h>
43#include <mem.h>
44#include <stdlib.h>
45#include <str_error.h>
46#include <sys/types.h>
47
48#include <usb/debug.h>
49#include <usb/usb.h>
50
51#include "uhci_batch.h"
52#include "utils/malloc32.h"
53#include "hc.h"
54
55#define UHCI_INTR_ALLOW_INTERRUPTS \
56 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
57#define UHCI_STATUS_USED_INTERRUPTS \
58 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
59
60static const irq_pio_range_t uhci_irq_pio_ranges[] = {
61 {
62 .base = 0,
63 .size = sizeof(uhci_regs_t)
64 }
65};
66
67static const irq_cmd_t uhci_irq_commands[] = {
68 {
69 .cmd = CMD_PIO_READ_16,
70 .dstarg = 1,
71 .addr = NULL
72 },
73 {
74 .cmd = CMD_AND,
75 .srcarg = 1,
76 .dstarg = 2,
77 .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS
78 },
79 {
80 .cmd = CMD_PREDICATE,
81 .srcarg = 2,
82 .value = 2
83 },
84 {
85 .cmd = CMD_PIO_WRITE_A_16,
86 .srcarg = 1,
87 .addr = NULL
88 },
89 {
90 .cmd = CMD_ACCEPT
91 }
92};
93
94static void hc_init_hw(const hc_t *instance);
95static int hc_init_mem_structures(hc_t *instance);
96static int hc_init_transfer_lists(hc_t *instance);
97
98static int hc_interrupt_emulator(void *arg);
99static int hc_debug_checker(void *arg);
100
101
102/** Generate IRQ code.
103 * @param[out] code IRQ code structure.
104 * @param[in] regs Device's register range.
105 *
106 * @return Error code.
107 */
108int hc_gen_irq_code(irq_code_t *code, addr_range_t *regs)
109{
110 assert(code);
111
112 if (RNGSZ(*regs) < sizeof(uhci_regs_t))
113 return EOVERFLOW;
114
115 code->ranges = malloc(sizeof(uhci_irq_pio_ranges));
116 if (code->ranges == NULL)
117 return ENOMEM;
118
119 code->cmds = malloc(sizeof(uhci_irq_commands));
120 if (code->cmds == NULL) {
121 free(code->ranges);
122 return ENOMEM;
123 }
124
125 code->rangecount = ARRAY_SIZE(uhci_irq_pio_ranges);
126 code->cmdcount = ARRAY_SIZE(uhci_irq_commands);
127
128 memcpy(code->ranges, uhci_irq_pio_ranges, sizeof(uhci_irq_pio_ranges));
129 code->ranges[0].base = RNGABS(*regs);
130
131 memcpy(code->cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
132 uhci_regs_t *registers = (uhci_regs_t *) RNGABSPTR(*regs);
133 code->cmds[0].addr = (void*)&registers->usbsts;
134 code->cmds[3].addr = (void*)&registers->usbsts;
135
136 return EOK;
137}
138
139/** Take action based on the interrupt cause.
140 *
141 * @param[in] instance UHCI structure to use.
142 * @param[in] status Value of the status register at the time of interrupt.
143 *
144 * Interrupt might indicate:
145 * - transaction completed, either by triggering IOC, SPD, or an error
146 * - some kind of device error
147 * - resume from suspend state (not implemented)
148 */
149void hc_interrupt(hc_t *instance, uint16_t status)
150{
151 assert(instance);
152 /* Lower 2 bits are transaction error and transaction complete */
153 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
154 LIST_INITIALIZE(done);
155 transfer_list_remove_finished(
156 &instance->transfers_interrupt, &done);
157 transfer_list_remove_finished(
158 &instance->transfers_control_slow, &done);
159 transfer_list_remove_finished(
160 &instance->transfers_control_full, &done);
161 transfer_list_remove_finished(
162 &instance->transfers_bulk_full, &done);
163
164 while (!list_empty(&done)) {
165 link_t *item = list_first(&done);
166 list_remove(item);
167 uhci_transfer_batch_t *batch =
168 uhci_transfer_batch_from_link(item);
169 uhci_transfer_batch_finish_dispose(batch);
170 }
171 }
172 /* Resume interrupts are not supported */
173 if (status & UHCI_STATUS_RESUME) {
174 usb_log_error("Resume interrupt!\n");
175 }
176
177 /* Bits 4 and 5 indicate hc error */
178 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
179 usb_log_error("UHCI hardware failure!.\n");
180 ++instance->hw_failures;
181 transfer_list_abort_all(&instance->transfers_interrupt);
182 transfer_list_abort_all(&instance->transfers_control_slow);
183 transfer_list_abort_all(&instance->transfers_control_full);
184 transfer_list_abort_all(&instance->transfers_bulk_full);
185
186 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
187 /* reinitialize hw, this triggers virtual disconnect*/
188 hc_init_hw(instance);
189 } else {
190 usb_log_fatal("Too many UHCI hardware failures!.\n");
191 hc_fini(instance);
192 }
193 }
194}
195
196/** Initialize UHCI hc driver structure
197 *
198 * @param[in] instance Memory place to initialize.
199 * @param[in] regs Range of device's I/O control registers.
200 * @param[in] interrupts True if hw interrupts should be used.
201 * @return Error code.
202 * @note Should be called only once on any structure.
203 *
204 * Initializes memory structures, starts up hw, and launches debugger and
205 * interrupt fibrils.
206 */
207int hc_init(hc_t *instance, addr_range_t *regs, bool interrupts)
208{
209 assert(instance);
210 assert(regs);
211 assert(regs->size >= sizeof(uhci_regs_t));
212
213 instance->hw_interrupts = interrupts;
214 instance->hw_failures = 0;
215
216 /* allow access to hc control registers */
217 uhci_regs_t *io;
218 int ret = pio_enable_range(regs, (void **) &io);
219 if (ret != EOK) {
220 usb_log_error("Failed to gain access to registers at %p: %s.\n",
221 io, str_error(ret));
222 return ret;
223 }
224 instance->registers = io;
225
226 usb_log_debug(
227 "Device registers at %p (%zuB) accessible.\n", io, regs->size);
228
229 ret = hc_init_mem_structures(instance);
230 if (ret != EOK) {
231 usb_log_error("Failed to init UHCI memory structures: %s.\n",
232 str_error(ret));
233 // TODO: we should disable pio here
234 return ret;
235 }
236
237 hc_init_hw(instance);
238 if (!interrupts) {
239 instance->interrupt_emulator =
240 fibril_create(hc_interrupt_emulator, instance);
241 fibril_add_ready(instance->interrupt_emulator);
242 }
243 (void)hc_debug_checker;
244
245 uhci_rh_init(&instance->rh, instance->registers->ports, "uhci");
246
247 return EOK;
248}
249
250/** Initialize UHCI hc hw resources.
251 *
252 * @param[in] instance UHCI structure to use.
253 * For magic values see UHCI Design Guide
254 */
255void hc_init_hw(const hc_t *instance)
256{
257 assert(instance);
258 uhci_regs_t *registers = instance->registers;
259
260 /* Reset everything, who knows what touched it before us */
261 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
262 async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
263 pio_write_16(&registers->usbcmd, 0);
264
265 /* Reset hc, all states and counters. Hope that hw is not broken */
266 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
267 do { async_usleep(10); }
268 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
269
270 /* Set frame to exactly 1ms */
271 pio_write_8(&registers->sofmod, 64);
272
273 /* Set frame list pointer */
274 const uint32_t pa = addr_to_phys(instance->frame_list);
275 pio_write_32(&registers->flbaseadd, pa);
276
277 if (instance->hw_interrupts) {
278 /* Enable all interrupts, but resume interrupt */
279 pio_write_16(&instance->registers->usbintr,
280 UHCI_INTR_ALLOW_INTERRUPTS);
281 }
282
283 const uint16_t cmd = pio_read_16(&registers->usbcmd);
284 if (cmd != 0)
285 usb_log_warning("Previous command value: %x.\n", cmd);
286
287 /* Start the hc with large(64B) packet FSBR */
288 pio_write_16(&registers->usbcmd,
289 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
290}
291
292/** Initialize UHCI hc memory structures.
293 *
294 * @param[in] instance UHCI structure to use.
295 * @return Error code
296 * @note Should be called only once on any structure.
297 *
298 * Structures:
299 * - transfer lists (queue heads need to be accessible by the hw)
300 * - frame list page (needs to be one UHCI hw accessible 4K page)
301 */
302int hc_init_mem_structures(hc_t *instance)
303{
304 assert(instance);
305
306 /* Init USB frame list page */
307 instance->frame_list = get_page();
308 if (!instance->frame_list) {
309 return ENOMEM;
310 }
311 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
312
313 /* Init transfer lists */
314 int ret = hc_init_transfer_lists(instance);
315 if (ret != EOK) {
316 usb_log_error("Failed to initialize transfer lists.\n");
317 return_page(instance->frame_list);
318 return ENOMEM;
319 }
320 usb_log_debug("Initialized transfer lists.\n");
321
322
323 /* Set all frames to point to the first queue head */
324 const uint32_t queue = LINK_POINTER_QH(
325 addr_to_phys(instance->transfers_interrupt.queue_head));
326
327 for (unsigned i = 0; i < UHCI_FRAME_LIST_COUNT; ++i) {
328 instance->frame_list[i] = queue;
329 }
330
331 return EOK;
332}
333
334/** Initialize UHCI hc transfer lists.
335 *
336 * @param[in] instance UHCI structure to use.
337 * @return Error code
338 * @note Should be called only once on any structure.
339 *
340 * Initializes transfer lists and sets them in one chain to support proper
341 * USB scheduling. Sets pointer table for quick access.
342 */
343int hc_init_transfer_lists(hc_t *instance)
344{
345 assert(instance);
346#define SETUP_TRANSFER_LIST(type, name) \
347do { \
348 int ret = transfer_list_init(&instance->transfers_##type, name); \
349 if (ret != EOK) { \
350 usb_log_error("Failed to setup %s transfer list: %s.\n", \
351 name, str_error(ret)); \
352 transfer_list_fini(&instance->transfers_bulk_full); \
353 transfer_list_fini(&instance->transfers_control_full); \
354 transfer_list_fini(&instance->transfers_control_slow); \
355 transfer_list_fini(&instance->transfers_interrupt); \
356 return ret; \
357 } \
358} while (0)
359
360 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
361 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
362 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
363 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
364#undef SETUP_TRANSFER_LIST
365 /* Connect lists into one schedule */
366 transfer_list_set_next(&instance->transfers_control_full,
367 &instance->transfers_bulk_full);
368 transfer_list_set_next(&instance->transfers_control_slow,
369 &instance->transfers_control_full);
370 transfer_list_set_next(&instance->transfers_interrupt,
371 &instance->transfers_control_slow);
372
373 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
374 * buggy on certain hw, enable at your own risk. */
375#ifdef FSBR
376 transfer_list_set_next(&instance->transfers_bulk_full,
377 &instance->transfers_control_full);
378#endif
379
380 /* Assign pointers to be used during scheduling */
381 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
382 &instance->transfers_interrupt;
383 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
384 &instance->transfers_interrupt;
385 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
386 &instance->transfers_control_full;
387 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
388 &instance->transfers_control_slow;
389 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
390 &instance->transfers_bulk_full;
391
392 return EOK;
393}
394
395/** Schedule batch for execution.
396 *
397 * @param[in] instance UHCI structure to use.
398 * @param[in] batch Transfer batch to schedule.
399 * @return Error code
400 *
401 * Checks for bandwidth availability and appends the batch to the proper queue.
402 */
403int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
404{
405 assert(hcd);
406 hc_t *instance = hcd->driver.data;
407 assert(instance);
408 assert(batch);
409
410 if (batch->ep->address == uhci_rh_get_address(&instance->rh))
411 return uhci_rh_schedule(&instance->rh, batch);
412
413 uhci_transfer_batch_t *uhci_batch = uhci_transfer_batch_get(batch);
414 if (!uhci_batch) {
415 usb_log_error("Failed to create UHCI transfer structures.\n");
416 return ENOMEM;
417 }
418
419 transfer_list_t *list =
420 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
421 assert(list);
422 transfer_list_add_batch(list, uhci_batch);
423
424 return EOK;
425}
426
427/** Polling function, emulates interrupts.
428 *
429 * @param[in] arg UHCI hc structure to use.
430 * @return EOK (should never return)
431 */
432int hc_interrupt_emulator(void* arg)
433{
434 usb_log_debug("Started interrupt emulator.\n");
435 hc_t *instance = arg;
436 assert(instance);
437
438 while (1) {
439 /* Read and clear status register */
440 uint16_t status = pio_read_16(&instance->registers->usbsts);
441 pio_write_16(&instance->registers->usbsts, status);
442 if (status != 0)
443 usb_log_debug2("UHCI status: %x.\n", status);
444 hc_interrupt(instance, status);
445 async_usleep(UHCI_INT_EMULATOR_TIMEOUT);
446 }
447 return EOK;
448}
449
450/** Debug function, checks consistency of memory structures.
451 *
452 * @param[in] arg UHCI structure to use.
453 * @return EOK (should never return)
454 */
455int hc_debug_checker(void *arg)
456{
457 hc_t *instance = arg;
458 assert(instance);
459
460#define QH(queue) \
461 instance->transfers_##queue.queue_head
462
463 while (1) {
464 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
465 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
466 const uint16_t intr =
467 pio_read_16(&instance->registers->usbintr);
468
469 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
470 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
471 cmd, sts, intr);
472 }
473
474 const uintptr_t frame_list =
475 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
476 if (frame_list != addr_to_phys(instance->frame_list)) {
477 usb_log_debug("Framelist address: %p vs. %p.\n",
478 (void *) frame_list,
479 (void *) addr_to_phys(instance->frame_list));
480 }
481
482 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
483
484 uintptr_t expected_pa = instance->frame_list[frnum]
485 & LINK_POINTER_ADDRESS_MASK;
486 uintptr_t real_pa = addr_to_phys(QH(interrupt));
487 if (expected_pa != real_pa) {
488 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
489 (void *) expected_pa, frnum, (void *) real_pa);
490 }
491
492 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
493 real_pa = addr_to_phys(QH(control_slow));
494 if (expected_pa != real_pa) {
495 usb_log_debug("Control Slow QH: %p vs. %p.\n",
496 (void *) expected_pa, (void *) real_pa);
497 }
498
499 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
500 real_pa = addr_to_phys(QH(control_full));
501 if (expected_pa != real_pa) {
502 usb_log_debug("Control Full QH: %p vs. %p.\n",
503 (void *) expected_pa, (void *) real_pa);
504 }
505
506 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
507 real_pa = addr_to_phys(QH(bulk_full));
508 if (expected_pa != real_pa ) {
509 usb_log_debug("Bulk QH: %p vs. %p.\n",
510 (void *) expected_pa, (void *) real_pa);
511 }
512 async_usleep(UHCI_DEBUGER_TIMEOUT);
513 }
514 return EOK;
515#undef QH
516}
517/**
518 * @}
519 */
Note: See TracBrowser for help on using the repository browser.