source: mainline/uspace/drv/bus/usb/uhci/hc.c@ 772a172

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 772a172 was 772a172, checked in by Jan Vesely <jano.vesely@…>, 12 years ago

ohci,uhci: Switch to library provided irq setup routine.
  • Property mode set to 100644
File size: 14.8 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41
42#include "hc.h"
43#include "uhci_batch.h"
44
45#define UHCI_INTR_ALLOW_INTERRUPTS \
46 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
47#define UHCI_STATUS_USED_INTERRUPTS \
48 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
49
50static const irq_pio_range_t uhci_irq_pio_ranges[] = {
51 {
52 .base = 0,
53 .size = sizeof(uhci_regs_t)
54 }
55};
56
57static const irq_cmd_t uhci_irq_commands[] = {
58 {
59 .cmd = CMD_PIO_READ_16,
60 .dstarg = 1,
61 .addr = NULL
62 },
63 {
64 .cmd = CMD_AND,
65 .srcarg = 1,
66 .dstarg = 2,
67 .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS
68 },
69 {
70 .cmd = CMD_PREDICATE,
71 .srcarg = 2,
72 .value = 2
73 },
74 {
75 .cmd = CMD_PIO_WRITE_A_16,
76 .srcarg = 1,
77 .addr = NULL
78 },
79 {
80 .cmd = CMD_ACCEPT
81 }
82};
83
84static void hc_init_hw(const hc_t *instance);
85static int hc_init_mem_structures(hc_t *instance);
86static int hc_init_transfer_lists(hc_t *instance);
87
88static int hc_interrupt_emulator(void *arg);
89static int hc_debug_checker(void *arg);
90
91
92/** Generate IRQ code.
93 * @param[out] code IRQ code structure.
94 * @param[in] regs Device's register range.
95 *
96 * @return Error code.
97 */
98int hc_gen_irq_code(irq_code_t *code, addr_range_t *regs)
99{
100 assert(code);
101
102 if (RNGSZ(*regs) < sizeof(uhci_regs_t))
103 return EOVERFLOW;
104
105 code->ranges = malloc(sizeof(uhci_irq_pio_ranges));
106 if (code->ranges == NULL)
107 return ENOMEM;
108
109 code->cmds = malloc(sizeof(uhci_irq_commands));
110 if (code->cmds == NULL) {
111 free(code->ranges);
112 return ENOMEM;
113 }
114
115 code->rangecount = ARRAY_SIZE(uhci_irq_pio_ranges);
116 code->cmdcount = ARRAY_SIZE(uhci_irq_commands);
117
118 memcpy(code->ranges, uhci_irq_pio_ranges, sizeof(uhci_irq_pio_ranges));
119 code->ranges[0].base = RNGABS(*regs);
120
121 memcpy(code->cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
122 uhci_regs_t *registers = (uhci_regs_t *) RNGABSPTR(*regs);
123 code->cmds[0].addr = (void*)&registers->usbsts;
124 code->cmds[3].addr = (void*)&registers->usbsts;
125
126 return EOK;
127}
128
129/** Take action based on the interrupt cause.
130 *
131 * @param[in] instance UHCI structure to use.
132 * @param[in] status Value of the status register at the time of interrupt.
133 *
134 * Interrupt might indicate:
135 * - transaction completed, either by triggering IOC, SPD, or an error
136 * - some kind of device error
137 * - resume from suspend state (not implemented)
138 */
139void hc_interrupt(hc_t *instance, uint16_t status)
140{
141 assert(instance);
142 /* Lower 2 bits are transaction error and transaction complete */
143 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
144 LIST_INITIALIZE(done);
145 transfer_list_remove_finished(
146 &instance->transfers_interrupt, &done);
147 transfer_list_remove_finished(
148 &instance->transfers_control_slow, &done);
149 transfer_list_remove_finished(
150 &instance->transfers_control_full, &done);
151 transfer_list_remove_finished(
152 &instance->transfers_bulk_full, &done);
153
154 while (!list_empty(&done)) {
155 link_t *item = list_first(&done);
156 list_remove(item);
157 uhci_transfer_batch_t *batch =
158 uhci_transfer_batch_from_link(item);
159 uhci_transfer_batch_finish_dispose(batch);
160 }
161 }
162 /* Resume interrupts are not supported */
163 if (status & UHCI_STATUS_RESUME) {
164 usb_log_error("Resume interrupt!\n");
165 }
166
167 /* Bits 4 and 5 indicate hc error */
168 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
169 usb_log_error("UHCI hardware failure!.\n");
170 ++instance->hw_failures;
171 transfer_list_abort_all(&instance->transfers_interrupt);
172 transfer_list_abort_all(&instance->transfers_control_slow);
173 transfer_list_abort_all(&instance->transfers_control_full);
174 transfer_list_abort_all(&instance->transfers_bulk_full);
175
176 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
177 /* reinitialize hw, this triggers virtual disconnect*/
178 hc_init_hw(instance);
179 } else {
180 usb_log_fatal("Too many UHCI hardware failures!.\n");
181 hc_fini(instance);
182 }
183 }
184}
185
186/** Initialize UHCI hc driver structure
187 *
188 * @param[in] instance Memory place to initialize.
189 * @param[in] regs Range of device's I/O control registers.
190 * @param[in] interrupts True if hw interrupts should be used.
191 * @return Error code.
192 * @note Should be called only once on any structure.
193 *
194 * Initializes memory structures, starts up hw, and launches debugger and
195 * interrupt fibrils.
196 */
197int hc_init(hc_t *instance, addr_range_t *regs, bool interrupts)
198{
199 assert(instance);
200 assert(regs);
201 assert(regs->size >= sizeof(uhci_regs_t));
202
203 instance->hw_interrupts = interrupts;
204 instance->hw_failures = 0;
205
206 /* allow access to hc control registers */
207 uhci_regs_t *io;
208 int ret = pio_enable_range(regs, (void **) &io);
209 if (ret != EOK) {
210 usb_log_error("Failed to gain access to registers at %p: %s.\n",
211 io, str_error(ret));
212 return ret;
213 }
214 instance->registers = io;
215
216 usb_log_debug(
217 "Device registers at %p (%zuB) accessible.\n", io, regs->size);
218
219 ret = hc_init_mem_structures(instance);
220 if (ret != EOK) {
221 usb_log_error("Failed to init UHCI memory structures: %s.\n",
222 str_error(ret));
223 // TODO: we should disable pio here
224 return ret;
225 }
226
227 hc_init_hw(instance);
228 if (!interrupts) {
229 instance->interrupt_emulator =
230 fibril_create(hc_interrupt_emulator, instance);
231 fibril_add_ready(instance->interrupt_emulator);
232 }
233 (void)hc_debug_checker;
234
235 uhci_rh_init(&instance->rh, instance->registers->ports, "uhci");
236
237 return EOK;
238}
239
240/** Initialize UHCI hc hw resources.
241 *
242 * @param[in] instance UHCI structure to use.
243 * For magic values see UHCI Design Guide
244 */
245void hc_init_hw(const hc_t *instance)
246{
247 assert(instance);
248 uhci_regs_t *registers = instance->registers;
249
250 /* Reset everything, who knows what touched it before us */
251 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
252 async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
253 pio_write_16(&registers->usbcmd, 0);
254
255 /* Reset hc, all states and counters. Hope that hw is not broken */
256 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
257 do { async_usleep(10); }
258 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
259
260 /* Set frame to exactly 1ms */
261 pio_write_8(&registers->sofmod, 64);
262
263 /* Set frame list pointer */
264 const uint32_t pa = addr_to_phys(instance->frame_list);
265 pio_write_32(&registers->flbaseadd, pa);
266
267 if (instance->hw_interrupts) {
268 /* Enable all interrupts, but resume interrupt */
269 pio_write_16(&instance->registers->usbintr,
270 UHCI_INTR_ALLOW_INTERRUPTS);
271 }
272
273 const uint16_t cmd = pio_read_16(&registers->usbcmd);
274 if (cmd != 0)
275 usb_log_warning("Previous command value: %x.\n", cmd);
276
277 /* Start the hc with large(64B) packet FSBR */
278 pio_write_16(&registers->usbcmd,
279 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
280}
281
282/** Initialize UHCI hc memory structures.
283 *
284 * @param[in] instance UHCI structure to use.
285 * @return Error code
286 * @note Should be called only once on any structure.
287 *
288 * Structures:
289 * - transfer lists (queue heads need to be accessible by the hw)
290 * - frame list page (needs to be one UHCI hw accessible 4K page)
291 */
292int hc_init_mem_structures(hc_t *instance)
293{
294 assert(instance);
295
296 /* Init USB frame list page */
297 instance->frame_list = get_page();
298 if (!instance->frame_list) {
299 return ENOMEM;
300 }
301 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
302
303 /* Init transfer lists */
304 int ret = hc_init_transfer_lists(instance);
305 if (ret != EOK) {
306 usb_log_error("Failed to initialize transfer lists.\n");
307 return_page(instance->frame_list);
308 return ENOMEM;
309 }
310 usb_log_debug("Initialized transfer lists.\n");
311
312
313 /* Set all frames to point to the first queue head */
314 const uint32_t queue = LINK_POINTER_QH(
315 addr_to_phys(instance->transfers_interrupt.queue_head));
316
317 for (unsigned i = 0; i < UHCI_FRAME_LIST_COUNT; ++i) {
318 instance->frame_list[i] = queue;
319 }
320
321 return EOK;
322}
323
324/** Initialize UHCI hc transfer lists.
325 *
326 * @param[in] instance UHCI structure to use.
327 * @return Error code
328 * @note Should be called only once on any structure.
329 *
330 * Initializes transfer lists and sets them in one chain to support proper
331 * USB scheduling. Sets pointer table for quick access.
332 */
333int hc_init_transfer_lists(hc_t *instance)
334{
335 assert(instance);
336#define SETUP_TRANSFER_LIST(type, name) \
337do { \
338 int ret = transfer_list_init(&instance->transfers_##type, name); \
339 if (ret != EOK) { \
340 usb_log_error("Failed to setup %s transfer list: %s.\n", \
341 name, str_error(ret)); \
342 transfer_list_fini(&instance->transfers_bulk_full); \
343 transfer_list_fini(&instance->transfers_control_full); \
344 transfer_list_fini(&instance->transfers_control_slow); \
345 transfer_list_fini(&instance->transfers_interrupt); \
346 return ret; \
347 } \
348} while (0)
349
350 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
351 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
352 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
353 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
354#undef SETUP_TRANSFER_LIST
355 /* Connect lists into one schedule */
356 transfer_list_set_next(&instance->transfers_control_full,
357 &instance->transfers_bulk_full);
358 transfer_list_set_next(&instance->transfers_control_slow,
359 &instance->transfers_control_full);
360 transfer_list_set_next(&instance->transfers_interrupt,
361 &instance->transfers_control_slow);
362
363 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
364 * buggy on certain hw, enable at your own risk. */
365#ifdef FSBR
366 transfer_list_set_next(&instance->transfers_bulk_full,
367 &instance->transfers_control_full);
368#endif
369
370 /* Assign pointers to be used during scheduling */
371 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
372 &instance->transfers_interrupt;
373 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
374 &instance->transfers_interrupt;
375 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
376 &instance->transfers_control_full;
377 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
378 &instance->transfers_control_slow;
379 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
380 &instance->transfers_bulk_full;
381
382 return EOK;
383}
384
385/** Schedule batch for execution.
386 *
387 * @param[in] instance UHCI structure to use.
388 * @param[in] batch Transfer batch to schedule.
389 * @return Error code
390 *
391 * Checks for bandwidth availability and appends the batch to the proper queue.
392 */
393int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
394{
395 assert(hcd);
396 hc_t *instance = hcd->driver.data;
397 assert(instance);
398 assert(batch);
399
400 if (batch->ep->address == uhci_rh_get_address(&instance->rh))
401 return uhci_rh_schedule(&instance->rh, batch);
402
403 uhci_transfer_batch_t *uhci_batch = uhci_transfer_batch_get(batch);
404 if (!uhci_batch) {
405 usb_log_error("Failed to create UHCI transfer structures.\n");
406 return ENOMEM;
407 }
408
409 transfer_list_t *list =
410 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
411 assert(list);
412 transfer_list_add_batch(list, uhci_batch);
413
414 return EOK;
415}
416
417/** Polling function, emulates interrupts.
418 *
419 * @param[in] arg UHCI hc structure to use.
420 * @return EOK (should never return)
421 */
422int hc_interrupt_emulator(void* arg)
423{
424 usb_log_debug("Started interrupt emulator.\n");
425 hc_t *instance = arg;
426 assert(instance);
427
428 while (1) {
429 /* Read and clear status register */
430 uint16_t status = pio_read_16(&instance->registers->usbsts);
431 pio_write_16(&instance->registers->usbsts, status);
432 if (status != 0)
433 usb_log_debug2("UHCI status: %x.\n", status);
434 hc_interrupt(instance, status);
435 async_usleep(UHCI_INT_EMULATOR_TIMEOUT);
436 }
437 return EOK;
438}
439
440/** Debug function, checks consistency of memory structures.
441 *
442 * @param[in] arg UHCI structure to use.
443 * @return EOK (should never return)
444 */
445int hc_debug_checker(void *arg)
446{
447 hc_t *instance = arg;
448 assert(instance);
449
450#define QH(queue) \
451 instance->transfers_##queue.queue_head
452
453 while (1) {
454 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
455 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
456 const uint16_t intr =
457 pio_read_16(&instance->registers->usbintr);
458
459 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
460 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
461 cmd, sts, intr);
462 }
463
464 const uintptr_t frame_list =
465 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
466 if (frame_list != addr_to_phys(instance->frame_list)) {
467 usb_log_debug("Framelist address: %p vs. %p.\n",
468 (void *) frame_list,
469 (void *) addr_to_phys(instance->frame_list));
470 }
471
472 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
473
474 uintptr_t expected_pa = instance->frame_list[frnum]
475 & LINK_POINTER_ADDRESS_MASK;
476 uintptr_t real_pa = addr_to_phys(QH(interrupt));
477 if (expected_pa != real_pa) {
478 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
479 (void *) expected_pa, frnum, (void *) real_pa);
480 }
481
482 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
483 real_pa = addr_to_phys(QH(control_slow));
484 if (expected_pa != real_pa) {
485 usb_log_debug("Control Slow QH: %p vs. %p.\n",
486 (void *) expected_pa, (void *) real_pa);
487 }
488
489 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
490 real_pa = addr_to_phys(QH(control_full));
491 if (expected_pa != real_pa) {
492 usb_log_debug("Control Full QH: %p vs. %p.\n",
493 (void *) expected_pa, (void *) real_pa);
494 }
495
496 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
497 real_pa = addr_to_phys(QH(bulk_full));
498 if (expected_pa != real_pa ) {
499 usb_log_debug("Bulk QH: %p vs. %p.\n",
500 (void *) expected_pa, (void *) real_pa);
501 }
502 async_usleep(UHCI_DEBUGER_TIMEOUT);
503 }
504 return EOK;
505#undef QH
506}
507/**
508 * @}
509 */
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