source: mainline/uspace/drv/bus/usb/uhci/hc.c@ 69a93d02

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 69a93d02 was 929599a8, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago

uhci: implemented transfer abort
  • Property mode set to 100644
File size: 17.0 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbuhcihc
30 * @{
31 */
32/** @file
33 * @brief UHCI Host controller driver routines
34 */
35
36#include <adt/list.h>
37#include <assert.h>
38#include <async.h>
39#include <ddi.h>
40#include <device/hw_res_parsed.h>
41#include <fibril.h>
42#include <errno.h>
43#include <macros.h>
44#include <mem.h>
45#include <stdlib.h>
46#include <stdint.h>
47#include <str_error.h>
48
49#include <usb/debug.h>
50#include <usb/usb.h>
51#include <usb/host/utils/malloc32.h>
52#include <usb/host/bandwidth.h>
53
54#include "uhci_batch.h"
55#include "transfer_list.h"
56#include "hc.h"
57
58#define UHCI_INTR_ALLOW_INTERRUPTS \
59 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
60#define UHCI_STATUS_USED_INTERRUPTS \
61 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
62
63static const irq_pio_range_t uhci_irq_pio_ranges[] = {
64 {
65 .base = 0,
66 .size = sizeof(uhci_regs_t)
67 }
68};
69
70static const irq_cmd_t uhci_irq_commands[] = {
71 {
72 .cmd = CMD_PIO_READ_16,
73 .dstarg = 1,
74 .addr = NULL
75 },
76 {
77 .cmd = CMD_AND,
78 .srcarg = 1,
79 .dstarg = 2,
80 .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS
81 },
82 {
83 .cmd = CMD_PREDICATE,
84 .srcarg = 2,
85 .value = 2
86 },
87 {
88 .cmd = CMD_PIO_WRITE_A_16,
89 .srcarg = 1,
90 .addr = NULL
91 },
92 {
93 .cmd = CMD_ACCEPT
94 }
95};
96
97static void hc_init_hw(const hc_t *instance);
98static int hc_init_mem_structures(hc_t *instance, hc_device_t *);
99static int hc_init_transfer_lists(hc_t *instance);
100
101static int hc_debug_checker(void *arg);
102
103
104/** Generate IRQ code.
105 * @param[out] code IRQ code structure.
106 * @param[in] hw_res Device's resources.
107 *
108 * @return Error code.
109 */
110int hc_gen_irq_code(irq_code_t *code, hc_device_t *hcd, const hw_res_list_parsed_t *hw_res)
111{
112 assert(code);
113 assert(hw_res);
114
115 if (hw_res->irqs.count != 1 || hw_res->io_ranges.count != 1)
116 return EINVAL;
117 const addr_range_t regs = hw_res->io_ranges.ranges[0];
118
119 if (RNGSZ(regs) < sizeof(uhci_regs_t))
120 return EOVERFLOW;
121
122 code->ranges = malloc(sizeof(uhci_irq_pio_ranges));
123 if (code->ranges == NULL)
124 return ENOMEM;
125
126 code->cmds = malloc(sizeof(uhci_irq_commands));
127 if (code->cmds == NULL) {
128 free(code->ranges);
129 return ENOMEM;
130 }
131
132 code->rangecount = ARRAY_SIZE(uhci_irq_pio_ranges);
133 code->cmdcount = ARRAY_SIZE(uhci_irq_commands);
134
135 memcpy(code->ranges, uhci_irq_pio_ranges, sizeof(uhci_irq_pio_ranges));
136 code->ranges[0].base = RNGABS(regs);
137
138 memcpy(code->cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
139 uhci_regs_t *registers = (uhci_regs_t *) RNGABSPTR(regs);
140 code->cmds[0].addr = (void*)&registers->usbsts;
141 code->cmds[3].addr = (void*)&registers->usbsts;
142
143 usb_log_debug("I/O regs at %p (size %zu), IRQ %d.\n",
144 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
145
146 return hw_res->irqs.irqs[0];
147}
148
149/** Take action based on the interrupt cause.
150 *
151 * @param[in] hcd HCD structure to use.
152 * @param[in] status Value of the status register at the time of interrupt.
153 *
154 * Interrupt might indicate:
155 * - transaction completed, either by triggering IOC, SPD, or an error
156 * - some kind of device error
157 * - resume from suspend state (not implemented)
158 */
159static void hc_interrupt(bus_t *bus, uint32_t status)
160{
161 hc_t *instance = bus_to_hc(bus);
162
163 /* Lower 2 bits are transaction error and transaction complete */
164 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
165 LIST_INITIALIZE(done);
166 transfer_list_remove_finished(
167 &instance->transfers_interrupt, &done);
168 transfer_list_remove_finished(
169 &instance->transfers_control_slow, &done);
170 transfer_list_remove_finished(
171 &instance->transfers_control_full, &done);
172 transfer_list_remove_finished(
173 &instance->transfers_bulk_full, &done);
174
175 list_foreach_safe(done, current, next) {
176 list_remove(current);
177 uhci_transfer_batch_t *batch =
178 uhci_transfer_batch_from_link(current);
179 usb_transfer_batch_finish(&batch->base);
180 }
181 }
182 /* Resume interrupts are not supported */
183 if (status & UHCI_STATUS_RESUME) {
184 usb_log_error("Resume interrupt!\n");
185 }
186
187 /* Bits 4 and 5 indicate hc error */
188 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
189 usb_log_error("UHCI hardware failure!.\n");
190 ++instance->hw_failures;
191 transfer_list_abort_all(&instance->transfers_interrupt);
192 transfer_list_abort_all(&instance->transfers_control_slow);
193 transfer_list_abort_all(&instance->transfers_control_full);
194 transfer_list_abort_all(&instance->transfers_bulk_full);
195
196 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
197 /* reinitialize hw, this triggers virtual disconnect*/
198 hc_init_hw(instance);
199 } else {
200 usb_log_fatal("Too many UHCI hardware failures!.\n");
201 hc_gone(&instance->base);
202 }
203 }
204}
205
206/** Initialize UHCI hc driver structure
207 *
208 * @param[in] instance Memory place to initialize.
209 * @param[in] regs Range of device's I/O control registers.
210 * @param[in] interrupts True if hw interrupts should be used.
211 * @return Error code.
212 * @note Should be called only once on any structure.
213 *
214 * Initializes memory structures, starts up hw, and launches debugger and
215 * interrupt fibrils.
216 */
217int hc_add(hc_device_t *hcd, const hw_res_list_parsed_t *hw_res)
218{
219 hc_t *instance = hcd_to_hc(hcd);
220 assert(hw_res);
221 if (hw_res->io_ranges.count != 1 ||
222 hw_res->io_ranges.ranges[0].size < sizeof(uhci_regs_t))
223 return EINVAL;
224
225 instance->hw_failures = 0;
226
227 /* allow access to hc control registers */
228 int ret = pio_enable_range(&hw_res->io_ranges.ranges[0],
229 (void **) &instance->registers);
230 if (ret != EOK) {
231 usb_log_error("Failed to gain access to registers: %s.\n",
232 str_error(ret));
233 return ret;
234 }
235
236 usb_log_debug("Device registers at %" PRIx64 " (%zuB) accessible.\n",
237 hw_res->io_ranges.ranges[0].address.absolute,
238 hw_res->io_ranges.ranges[0].size);
239
240 ret = hc_init_mem_structures(instance, hcd);
241 if (ret != EOK) {
242 usb_log_error("Failed to init UHCI memory structures: %s.\n",
243 str_error(ret));
244 // TODO: we should disable pio here
245 return ret;
246 }
247
248 return EOK;
249}
250
251int hc_start(hc_device_t *hcd)
252{
253 hc_t *instance = hcd_to_hc(hcd);
254 hc_init_hw(instance);
255 (void)hc_debug_checker;
256
257 return uhci_rh_init(&instance->rh, instance->registers->ports, "uhci");
258}
259
260/** Safely dispose host controller internal structures
261 *
262 * @param[in] instance Host controller structure to use.
263 */
264int hc_gone(hc_device_t *instance)
265{
266 assert(instance);
267 //TODO Implement
268 return ENOTSUP;
269}
270
271/** Initialize UHCI hc hw resources.
272 *
273 * @param[in] instance UHCI structure to use.
274 * For magic values see UHCI Design Guide
275 */
276void hc_init_hw(const hc_t *instance)
277{
278 assert(instance);
279 uhci_regs_t *registers = instance->registers;
280
281 /* Reset everything, who knows what touched it before us */
282 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
283 async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
284 pio_write_16(&registers->usbcmd, 0);
285
286 /* Reset hc, all states and counters. Hope that hw is not broken */
287 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
288 do { async_usleep(10); }
289 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
290
291 /* Set frame to exactly 1ms */
292 pio_write_8(&registers->sofmod, 64);
293
294 /* Set frame list pointer */
295 const uint32_t pa = addr_to_phys(instance->frame_list);
296 pio_write_32(&registers->flbaseadd, pa);
297
298 if (instance->base.irq_cap >= 0) {
299 /* Enable all interrupts, but resume interrupt */
300 pio_write_16(&instance->registers->usbintr,
301 UHCI_INTR_ALLOW_INTERRUPTS);
302 }
303
304 const uint16_t cmd = pio_read_16(&registers->usbcmd);
305 if (cmd != 0)
306 usb_log_warning("Previous command value: %x.\n", cmd);
307
308 /* Start the hc with large(64B) packet FSBR */
309 pio_write_16(&registers->usbcmd,
310 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
311}
312
313static usb_transfer_batch_t *create_transfer_batch(endpoint_t *ep)
314{
315 uhci_transfer_batch_t *batch = uhci_transfer_batch_create(ep);
316 return &batch->base;
317}
318
319static void destroy_transfer_batch(usb_transfer_batch_t *batch)
320{
321 uhci_transfer_batch_destroy(uhci_transfer_batch_get(batch));
322}
323
324static void endpoint_unregister(endpoint_t *ep)
325{
326 hc_t * const hc = bus_to_hc(endpoint_get_bus(ep));
327 usb2_bus_ops.endpoint_unregister(ep);
328
329 uhci_transfer_batch_t *batch = NULL;
330
331 fibril_mutex_lock(&ep->guard);
332 if (ep->active_batch) {
333 batch = uhci_transfer_batch_get(ep->active_batch);
334
335 transfer_list_t *list = hc->transfers[ep->device->speed][ep->transfer_type];
336 assert(list);
337
338 fibril_mutex_lock(&list->guard);
339 transfer_list_remove_batch(list, batch);
340 fibril_mutex_unlock(&list->guard);
341
342 endpoint_wait_timeout_locked(ep, 2000);
343
344 batch = uhci_transfer_batch_get(ep->active_batch);
345 if (ep->active_batch) {
346 endpoint_deactivate_locked(ep);
347 }
348 }
349 fibril_mutex_unlock(&ep->guard);
350
351 if (batch) {
352 batch->base.error = EINTR;
353 batch->base.transfered_size = 0;
354 usb_transfer_batch_finish(&batch->base);
355 }
356}
357
358static int hc_status(bus_t *, uint32_t *);
359static int hc_schedule(usb_transfer_batch_t *);
360
361static const bus_ops_t uhci_bus_ops = {
362 .parent = &usb2_bus_ops,
363
364 .interrupt = hc_interrupt,
365 .status = hc_status,
366
367 .endpoint_unregister = endpoint_unregister,
368 .endpoint_count_bw = bandwidth_count_usb11,
369
370 .batch_create = create_transfer_batch,
371 .batch_schedule = hc_schedule,
372 .batch_destroy = destroy_transfer_batch,
373};
374
375/** Initialize UHCI hc memory structures.
376 *
377 * @param[in] instance UHCI structure to use.
378 * @return Error code
379 * @note Should be called only once on any structure.
380 *
381 * Structures:
382 * - transfer lists (queue heads need to be accessible by the hw)
383 * - frame list page (needs to be one UHCI hw accessible 4K page)
384 */
385int hc_init_mem_structures(hc_t *instance, hc_device_t *hcd)
386{
387 assert(instance);
388
389 usb2_bus_init(&instance->bus, BANDWIDTH_AVAILABLE_USB11);
390
391 bus_t *bus = (bus_t *) &instance->bus;
392 bus->ops = &uhci_bus_ops;
393
394 hc_device_setup(&instance->base, bus);
395
396 /* Init USB frame list page */
397 instance->frame_list = get_page();
398 if (!instance->frame_list) {
399 return ENOMEM;
400 }
401 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
402
403 /* Init transfer lists */
404 int ret = hc_init_transfer_lists(instance);
405 if (ret != EOK) {
406 usb_log_error("Failed to initialize transfer lists.\n");
407 return_page(instance->frame_list);
408 return ENOMEM;
409 }
410 usb_log_debug("Initialized transfer lists.\n");
411
412
413 /* Set all frames to point to the first queue head */
414 const uint32_t queue = LINK_POINTER_QH(
415 addr_to_phys(instance->transfers_interrupt.queue_head));
416
417 for (unsigned i = 0; i < UHCI_FRAME_LIST_COUNT; ++i) {
418 instance->frame_list[i] = queue;
419 }
420
421 return EOK;
422}
423
424/** Initialize UHCI hc transfer lists.
425 *
426 * @param[in] instance UHCI structure to use.
427 * @return Error code
428 * @note Should be called only once on any structure.
429 *
430 * Initializes transfer lists and sets them in one chain to support proper
431 * USB scheduling. Sets pointer table for quick access.
432 */
433int hc_init_transfer_lists(hc_t *instance)
434{
435 assert(instance);
436#define SETUP_TRANSFER_LIST(type, name) \
437do { \
438 int ret = transfer_list_init(&instance->transfers_##type, name); \
439 if (ret != EOK) { \
440 usb_log_error("Failed to setup %s transfer list: %s.\n", \
441 name, str_error(ret)); \
442 transfer_list_fini(&instance->transfers_bulk_full); \
443 transfer_list_fini(&instance->transfers_control_full); \
444 transfer_list_fini(&instance->transfers_control_slow); \
445 transfer_list_fini(&instance->transfers_interrupt); \
446 return ret; \
447 } \
448} while (0)
449
450 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
451 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
452 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
453 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
454#undef SETUP_TRANSFER_LIST
455 /* Connect lists into one schedule */
456 transfer_list_set_next(&instance->transfers_control_full,
457 &instance->transfers_bulk_full);
458 transfer_list_set_next(&instance->transfers_control_slow,
459 &instance->transfers_control_full);
460 transfer_list_set_next(&instance->transfers_interrupt,
461 &instance->transfers_control_slow);
462
463 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
464 * buggy on certain hw, enable at your own risk. */
465#ifdef FSBR
466 transfer_list_set_next(&instance->transfers_bulk_full,
467 &instance->transfers_control_full);
468#endif
469
470 /* Assign pointers to be used during scheduling */
471 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
472 &instance->transfers_interrupt;
473 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
474 &instance->transfers_interrupt;
475 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
476 &instance->transfers_control_full;
477 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
478 &instance->transfers_control_slow;
479 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
480 &instance->transfers_bulk_full;
481
482 return EOK;
483}
484
485static int hc_status(bus_t *bus, uint32_t *status)
486{
487 hc_t *instance = bus_to_hc(bus);
488 assert(status);
489
490 *status = 0;
491 if (instance->registers) {
492 uint16_t s = pio_read_16(&instance->registers->usbsts);
493 pio_write_16(&instance->registers->usbsts, s);
494 *status = s;
495 }
496 return EOK;
497}
498
499/** Schedule batch for execution.
500 *
501 * @param[in] instance UHCI structure to use.
502 * @param[in] batch Transfer batch to schedule.
503 * @return Error code
504 *
505 * Checks for bandwidth availability and appends the batch to the proper queue.
506 */
507static int hc_schedule(usb_transfer_batch_t *batch)
508{
509 uhci_transfer_batch_t *uhci_batch = uhci_transfer_batch_get(batch);
510 endpoint_t *ep = batch->ep;
511 hc_t *hc = bus_to_hc(endpoint_get_bus(ep));
512
513 if (batch->target.address == uhci_rh_get_address(&hc->rh))
514 return uhci_rh_schedule(&hc->rh, batch);
515
516
517 const int err = uhci_transfer_batch_prepare(uhci_batch);
518 if (err)
519 return err;
520
521 transfer_list_t *list = hc->transfers[ep->device->speed][ep->transfer_type];
522 assert(list);
523 transfer_list_add_batch(list, uhci_batch);
524
525 return EOK;
526}
527
528int hc_unschedule_batch(usb_transfer_batch_t *batch)
529{
530
531 return EOK;
532}
533
534/** Debug function, checks consistency of memory structures.
535 *
536 * @param[in] arg UHCI structure to use.
537 * @return EOK (should never return)
538 */
539int hc_debug_checker(void *arg)
540{
541 hc_t *instance = arg;
542 assert(instance);
543
544#define QH(queue) \
545 instance->transfers_##queue.queue_head
546
547 while (1) {
548 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
549 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
550 const uint16_t intr =
551 pio_read_16(&instance->registers->usbintr);
552
553 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
554 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
555 cmd, sts, intr);
556 }
557
558 const uintptr_t frame_list =
559 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
560 if (frame_list != addr_to_phys(instance->frame_list)) {
561 usb_log_debug("Framelist address: %p vs. %p.\n",
562 (void *) frame_list,
563 (void *) addr_to_phys(instance->frame_list));
564 }
565
566 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
567
568 uintptr_t expected_pa = instance->frame_list[frnum]
569 & LINK_POINTER_ADDRESS_MASK;
570 uintptr_t real_pa = addr_to_phys(QH(interrupt));
571 if (expected_pa != real_pa) {
572 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
573 (void *) expected_pa, frnum, (void *) real_pa);
574 }
575
576 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
577 real_pa = addr_to_phys(QH(control_slow));
578 if (expected_pa != real_pa) {
579 usb_log_debug("Control Slow QH: %p vs. %p.\n",
580 (void *) expected_pa, (void *) real_pa);
581 }
582
583 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
584 real_pa = addr_to_phys(QH(control_full));
585 if (expected_pa != real_pa) {
586 usb_log_debug("Control Full QH: %p vs. %p.\n",
587 (void *) expected_pa, (void *) real_pa);
588 }
589
590 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
591 real_pa = addr_to_phys(QH(bulk_full));
592 if (expected_pa != real_pa ) {
593 usb_log_debug("Bulk QH: %p vs. %p.\n",
594 (void *) expected_pa, (void *) real_pa);
595 }
596 async_usleep(UHCI_DEBUGER_TIMEOUT);
597 }
598 return EOK;
599#undef QH
600}
601/**
602 * @}
603 */
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