source: mainline/uspace/drv/bus/usb/uhci/hc.c@ 5fe0a697

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 5fe0a697 was 5fe0a697, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

UHCI: Use new usb hc driver architecture.
  • Property mode set to 100644
File size: 16.3 KB
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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41
42#include "hc.h"
43#include "batch.h"
44
45#define UHCI_INTR_ALLOW_INTERRUPTS \
46 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
47#define UHCI_STATUS_USED_INTERRUPTS \
48 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
49
50static int schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
51{
52 assert(hcd);
53 return hc_schedule(hcd->private_data, batch);
54}
55
56static const irq_cmd_t uhci_irq_commands[] =
57{
58 { .cmd = CMD_PIO_READ_16, .dstarg = 1, .addr = NULL/*filled later*/},
59 { .cmd = CMD_BTEST, .srcarg = 1, .dstarg = 2,
60 .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS },
61 { .cmd = CMD_PREDICATE, .srcarg = 2, .value = 2 },
62 { .cmd = CMD_PIO_WRITE_A_16, .srcarg = 1, .addr = NULL/*filled later*/},
63 { .cmd = CMD_ACCEPT },
64};
65
66static int hc_init_transfer_lists(hc_t *instance);
67static int hc_init_mem_structures(hc_t *instance);
68static void hc_init_hw(hc_t *instance);
69
70static int hc_interrupt_emulator(void *arg);
71static int hc_debug_checker(void *arg);
72
73/*----------------------------------------------------------------------------*/
74/** Get number of commands used in IRQ code.
75 * @return Number of commands.
76 */
77size_t hc_irq_cmd_count(void)
78{
79 return sizeof(uhci_irq_commands) / sizeof(irq_cmd_t);
80}
81/*----------------------------------------------------------------------------*/
82/** Generate IRQ code commands.
83 * @param[out] cmds Place to store the commands.
84 * @param[in] cmd_size Size of the place (bytes).
85 * @param[in] regs Physical address of device's registers.
86 * @param[in] reg_size Size of the register area (bytes).
87 *
88 * @return Error code.
89 */
90int hc_get_irq_commands(
91 irq_cmd_t cmds[], size_t cmd_size, uintptr_t regs, size_t reg_size)
92{
93 if (cmd_size < sizeof(uhci_irq_commands)
94 || reg_size < sizeof(uhci_regs_t))
95 return EOVERFLOW;
96
97 uhci_regs_t *registers = (uhci_regs_t*)regs;
98
99 memcpy(cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
100
101 cmds[0].addr = (void*)&registers->usbsts;
102 cmds[3].addr = (void*)&registers->usbsts;
103 return EOK;
104}
105/*----------------------------------------------------------------------------*/
106/** Initialize UHCI hc driver structure
107 *
108 * @param[in] instance Memory place to initialize.
109 * @param[in] regs Address of I/O control registers.
110 * @param[in] reg_size Size of I/O control registers.
111 * @param[in] interrupts True if hw interrupts should be used.
112 * @return Error code.
113 * @note Should be called only once on any structure.
114 *
115 * Initializes memory structures, starts up hw, and launches debugger and
116 * interrupt fibrils.
117 */
118int hc_init(hc_t *instance, void *regs, size_t reg_size, bool interrupts)
119{
120 assert(reg_size >= sizeof(uhci_regs_t));
121 int ret;
122
123#define CHECK_RET_RETURN(ret, message...) \
124 if (ret != EOK) { \
125 usb_log_error(message); \
126 return ret; \
127 } else (void) 0
128
129 instance->hw_interrupts = interrupts;
130 instance->hw_failures = 0;
131
132 /* allow access to hc control registers */
133 uhci_regs_t *io;
134 ret = pio_enable(regs, reg_size, (void **)&io);
135 CHECK_RET_RETURN(ret, "Failed to gain access to registers at %p: %s.\n",
136 io, str_error(ret));
137 instance->registers = io;
138 usb_log_debug(
139 "Device registers at %p (%zuB) accessible.\n", io, reg_size);
140 hcd_init(&instance->generic, BANDWIDTH_AVAILABLE_USB11);
141 instance->generic.private_data = instance;
142 instance->generic.schedule = schedule;
143 instance->generic.batch_private_ctor = uhci_transfer_batch_create;
144 instance->generic.batch_private_dtor = uhci_transfer_batch_dispose;
145
146 ret = hc_init_mem_structures(instance);
147 CHECK_RET_RETURN(ret,
148 "Failed to initialize UHCI memory structures: %s.\n",
149 str_error(ret));
150
151 hc_init_hw(instance);
152 if (!interrupts) {
153 instance->interrupt_emulator =
154 fibril_create(hc_interrupt_emulator, instance);
155 fibril_add_ready(instance->interrupt_emulator);
156 }
157 (void)hc_debug_checker;
158
159 return EOK;
160#undef CHECK_RET_DEST_FUN_RETURN
161}
162/*----------------------------------------------------------------------------*/
163/** Initialize UHCI hc hw resources.
164 *
165 * @param[in] instance UHCI structure to use.
166 * For magic values see UHCI Design Guide
167 */
168void hc_init_hw(hc_t *instance)
169{
170 assert(instance);
171 uhci_regs_t *registers = instance->registers;
172
173 /* Reset everything, who knows what touched it before us */
174 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
175 async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
176 pio_write_16(&registers->usbcmd, 0);
177
178 /* Reset hc, all states and counters. Hope that hw is not broken */
179 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
180 do { async_usleep(10); }
181 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
182
183 /* Set frame to exactly 1ms */
184 pio_write_8(&registers->sofmod, 64);
185
186 /* Set frame list pointer */
187 const uint32_t pa = addr_to_phys(instance->frame_list);
188 pio_write_32(&registers->flbaseadd, pa);
189
190 if (instance->hw_interrupts) {
191 /* Enable all interrupts, but resume interrupt */
192 pio_write_16(&instance->registers->usbintr,
193 UHCI_INTR_ALLOW_INTERRUPTS);
194 }
195
196 const uint16_t cmd = pio_read_16(&registers->usbcmd);
197 if (cmd != 0)
198 usb_log_warning("Previous command value: %x.\n", cmd);
199
200 /* Start the hc with large(64B) packet FSBR */
201 pio_write_16(&registers->usbcmd,
202 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
203}
204/*----------------------------------------------------------------------------*/
205/** Initialize UHCI hc memory structures.
206 *
207 * @param[in] instance UHCI structure to use.
208 * @return Error code
209 * @note Should be called only once on any structure.
210 *
211 * Structures:
212 * - interrupt code (I/O addressses are customized per instance)
213 * - transfer lists (queue heads need to be accessible by the hw)
214 * - frame list page (needs to be one UHCI hw accessible 4K page)
215 */
216int hc_init_mem_structures(hc_t *instance)
217{
218 assert(instance);
219#define CHECK_RET_RETURN(ret, message...) \
220 if (ret != EOK) { \
221 usb_log_error(message); \
222 return ret; \
223 } else (void) 0
224
225 /* Init transfer lists */
226 int ret = hc_init_transfer_lists(instance);
227 CHECK_RET_RETURN(ret, "Failed to initialize transfer lists.\n");
228 usb_log_debug("Initialized transfer lists.\n");
229
230 /* Init device keeper */
231 usb_device_keeper_init(&instance->manager);
232 usb_log_debug("Initialized device keeper.\n");
233
234 ret = usb_endpoint_manager_init(&instance->ep_manager,
235 BANDWIDTH_AVAILABLE_USB11);
236 CHECK_RET_RETURN(ret, "Failed to initialize endpoint manager: %s.\n",
237 str_error(ret));
238
239 /* Init USB frame list page*/
240 instance->frame_list = get_page();
241 if (!instance->frame_list) {
242 usb_log_error("Failed to get frame list page.\n");
243 usb_endpoint_manager_destroy(&instance->ep_manager);
244 return ENOMEM;
245 }
246 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
247
248 /* Set all frames to point to the first queue head */
249 const uint32_t queue = LINK_POINTER_QH(
250 addr_to_phys(instance->transfers_interrupt.queue_head));
251 unsigned i = 0;
252 for(; i < UHCI_FRAME_LIST_COUNT; ++i) {
253 instance->frame_list[i] = queue;
254 }
255
256 return EOK;
257#undef CHECK_RET_RETURN
258}
259/*----------------------------------------------------------------------------*/
260/** Initialize UHCI hc transfer lists.
261 *
262 * @param[in] instance UHCI structure to use.
263 * @return Error code
264 * @note Should be called only once on any structure.
265 *
266 * Initializes transfer lists and sets them in one chain to support proper
267 * USB scheduling. Sets pointer table for quick access.
268 */
269int hc_init_transfer_lists(hc_t *instance)
270{
271 assert(instance);
272#define SETUP_TRANSFER_LIST(type, name) \
273do { \
274 int ret = transfer_list_init(&instance->transfers_##type, name); \
275 if (ret != EOK) { \
276 usb_log_error("Failed to setup %s transfer list: %s.\n", \
277 name, str_error(ret)); \
278 transfer_list_fini(&instance->transfers_bulk_full); \
279 transfer_list_fini(&instance->transfers_control_full); \
280 transfer_list_fini(&instance->transfers_control_slow); \
281 transfer_list_fini(&instance->transfers_interrupt); \
282 return ret; \
283 } \
284} while (0)
285
286 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
287 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
288 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
289 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
290#undef SETUP_TRANSFER_LIST
291 /* Connect lists into one schedule */
292 transfer_list_set_next(&instance->transfers_control_full,
293 &instance->transfers_bulk_full);
294 transfer_list_set_next(&instance->transfers_control_slow,
295 &instance->transfers_control_full);
296 transfer_list_set_next(&instance->transfers_interrupt,
297 &instance->transfers_control_slow);
298
299 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
300 * buggy on certain hw, enable at your own risk. */
301#ifdef FSBR
302 transfer_list_set_next(&instance->transfers_bulk_full,
303 &instance->transfers_control_full);
304#endif
305
306 /* Assign pointers to be used during scheduling */
307 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
308 &instance->transfers_interrupt;
309 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
310 &instance->transfers_interrupt;
311 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
312 &instance->transfers_control_full;
313 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
314 &instance->transfers_control_slow;
315 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
316 &instance->transfers_bulk_full;
317
318 return EOK;
319#undef CHECK_RET_CLEAR_RETURN
320}
321/*----------------------------------------------------------------------------*/
322/** Schedule batch for execution.
323 *
324 * @param[in] instance UHCI structure to use.
325 * @param[in] batch Transfer batch to schedule.
326 * @return Error code
327 *
328 * Checks for bandwidth availability and appends the batch to the proper queue.
329 */
330int hc_schedule(hc_t *instance, usb_transfer_batch_t *batch)
331{
332 assert(instance);
333 assert(batch);
334
335 transfer_list_t *list =
336 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
337 assert(list);
338 transfer_list_add_batch(list, batch);
339
340 return EOK;
341}
342/*----------------------------------------------------------------------------*/
343/** Take action based on the interrupt cause.
344 *
345 * @param[in] instance UHCI structure to use.
346 * @param[in] status Value of the status register at the time of interrupt.
347 *
348 * Interrupt might indicate:
349 * - transaction completed, either by triggering IOC, SPD, or an error
350 * - some kind of device error
351 * - resume from suspend state (not implemented)
352 */
353void hc_interrupt(hc_t *instance, uint16_t status)
354{
355 assert(instance);
356 /* Lower 2 bits are transaction error and transaction complete */
357 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
358 LIST_INITIALIZE(done);
359 transfer_list_remove_finished(
360 &instance->transfers_interrupt, &done);
361 transfer_list_remove_finished(
362 &instance->transfers_control_slow, &done);
363 transfer_list_remove_finished(
364 &instance->transfers_control_full, &done);
365 transfer_list_remove_finished(
366 &instance->transfers_bulk_full, &done);
367
368 while (!list_empty(&done)) {
369 link_t *item = list_first(&done);
370 list_remove(item);
371 usb_transfer_batch_t *batch =
372 list_get_instance(item, usb_transfer_batch_t, link);
373 usb_transfer_batch_finish(batch);
374 }
375 }
376 /* Resume interrupts are not supported */
377 if (status & UHCI_STATUS_RESUME) {
378 usb_log_error("Resume interrupt!\n");
379 }
380
381 /* Bits 4 and 5 indicate hc error */
382 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
383 usb_log_error("UHCI hardware failure!.\n");
384 ++instance->hw_failures;
385 transfer_list_abort_all(&instance->transfers_interrupt);
386 transfer_list_abort_all(&instance->transfers_control_slow);
387 transfer_list_abort_all(&instance->transfers_control_full);
388 transfer_list_abort_all(&instance->transfers_bulk_full);
389
390 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
391 /* reinitialize hw, this triggers virtual disconnect*/
392 hc_init_hw(instance);
393 } else {
394 usb_log_fatal("Too many UHCI hardware failures!.\n");
395 hc_fini(instance);
396 }
397 }
398}
399/*----------------------------------------------------------------------------*/
400/** Polling function, emulates interrupts.
401 *
402 * @param[in] arg UHCI hc structure to use.
403 * @return EOK (should never return)
404 */
405int hc_interrupt_emulator(void* arg)
406{
407 usb_log_debug("Started interrupt emulator.\n");
408 hc_t *instance = arg;
409 assert(instance);
410
411 while (1) {
412 /* Read and clear status register */
413 uint16_t status = pio_read_16(&instance->registers->usbsts);
414 pio_write_16(&instance->registers->usbsts, status);
415 if (status != 0)
416 usb_log_debug2("UHCI status: %x.\n", status);
417// Qemu fails to report stalled communication
418// see https://bugs.launchpad.net/qemu/+bug/757654
419// This is a simple workaround to force queue processing every time
420 // status |= 1;
421 hc_interrupt(instance, status);
422 async_usleep(UHCI_INT_EMULATOR_TIMEOUT);
423 }
424 return EOK;
425}
426/*---------------------------------------------------------------------------*/
427/** Debug function, checks consistency of memory structures.
428 *
429 * @param[in] arg UHCI structure to use.
430 * @return EOK (should never return)
431 */
432int hc_debug_checker(void *arg)
433{
434 hc_t *instance = arg;
435 assert(instance);
436
437#define QH(queue) \
438 instance->transfers_##queue.queue_head
439
440 while (1) {
441 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
442 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
443 const uint16_t intr =
444 pio_read_16(&instance->registers->usbintr);
445
446 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
447 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
448 cmd, sts, intr);
449 }
450
451 const uintptr_t frame_list =
452 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
453 if (frame_list != addr_to_phys(instance->frame_list)) {
454 usb_log_debug("Framelist address: %p vs. %p.\n",
455 (void *) frame_list,
456 (void *) addr_to_phys(instance->frame_list));
457 }
458
459 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
460
461 uintptr_t expected_pa = instance->frame_list[frnum]
462 & LINK_POINTER_ADDRESS_MASK;
463 uintptr_t real_pa = addr_to_phys(QH(interrupt));
464 if (expected_pa != real_pa) {
465 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
466 (void *) expected_pa, frnum, (void *) real_pa);
467 }
468
469 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
470 real_pa = addr_to_phys(QH(control_slow));
471 if (expected_pa != real_pa) {
472 usb_log_debug("Control Slow QH: %p vs. %p.\n",
473 (void *) expected_pa, (void *) real_pa);
474 }
475
476 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
477 real_pa = addr_to_phys(QH(control_full));
478 if (expected_pa != real_pa) {
479 usb_log_debug("Control Full QH: %p vs. %p.\n",
480 (void *) expected_pa, (void *) real_pa);
481 }
482
483 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
484 real_pa = addr_to_phys(QH(bulk_full));
485 if (expected_pa != real_pa ) {
486 usb_log_debug("Bulk QH: %p vs. %p.\n",
487 (void *) expected_pa, (void *) real_pa);
488 }
489 async_usleep(UHCI_DEBUGER_TIMEOUT);
490 }
491 return EOK;
492#undef QH
493}
494/**
495 * @}
496 */
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