source: mainline/uspace/drv/bus/usb/uhci/hc.c@ 47a9633

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 47a9633 was 32fb6bce, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago

usbhost: refactoring

This commit moves interrupt, status and schedule to bus
operations. Then the purpose of hcd_t is better defined, and split into
hc_driver_t and hc_device_t. hc_driver_t is used to wrap driver
implementation by the library (similar to how usb_driver_t is used to
wrap usb device drivers). hc_device_t is used as a parent for hc_t
inside drivers, and is allocated inside the DDF device node.

To support these changes, some local identifiers were renamed, some
functions were moved and/or renamed and their arguments changed. The
most notable one being hcd_send_batch → bus_device_send_batch.
  • Property mode set to 100644
File size: 16.2 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbuhcihc
30 * @{
31 */
32/** @file
33 * @brief UHCI Host controller driver routines
34 */
35
36#include <adt/list.h>
37#include <assert.h>
38#include <async.h>
39#include <ddi.h>
40#include <device/hw_res_parsed.h>
41#include <fibril.h>
42#include <errno.h>
43#include <macros.h>
44#include <mem.h>
45#include <stdlib.h>
46#include <stdint.h>
47#include <str_error.h>
48
49#include <usb/debug.h>
50#include <usb/usb.h>
51#include <usb/host/utils/malloc32.h>
52#include <usb/host/bandwidth.h>
53
54#include "uhci_batch.h"
55#include "hc.h"
56
57#define UHCI_INTR_ALLOW_INTERRUPTS \
58 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
59#define UHCI_STATUS_USED_INTERRUPTS \
60 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
61
62static const irq_pio_range_t uhci_irq_pio_ranges[] = {
63 {
64 .base = 0,
65 .size = sizeof(uhci_regs_t)
66 }
67};
68
69static const irq_cmd_t uhci_irq_commands[] = {
70 {
71 .cmd = CMD_PIO_READ_16,
72 .dstarg = 1,
73 .addr = NULL
74 },
75 {
76 .cmd = CMD_AND,
77 .srcarg = 1,
78 .dstarg = 2,
79 .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS
80 },
81 {
82 .cmd = CMD_PREDICATE,
83 .srcarg = 2,
84 .value = 2
85 },
86 {
87 .cmd = CMD_PIO_WRITE_A_16,
88 .srcarg = 1,
89 .addr = NULL
90 },
91 {
92 .cmd = CMD_ACCEPT
93 }
94};
95
96static void hc_init_hw(const hc_t *instance);
97static int hc_init_mem_structures(hc_t *instance, hc_device_t *);
98static int hc_init_transfer_lists(hc_t *instance);
99
100static int hc_debug_checker(void *arg);
101
102
103/** Generate IRQ code.
104 * @param[out] code IRQ code structure.
105 * @param[in] hw_res Device's resources.
106 *
107 * @return Error code.
108 */
109int hc_gen_irq_code(irq_code_t *code, hc_device_t *hcd, const hw_res_list_parsed_t *hw_res)
110{
111 assert(code);
112 assert(hw_res);
113
114 if (hw_res->irqs.count != 1 || hw_res->io_ranges.count != 1)
115 return EINVAL;
116 const addr_range_t regs = hw_res->io_ranges.ranges[0];
117
118 if (RNGSZ(regs) < sizeof(uhci_regs_t))
119 return EOVERFLOW;
120
121 code->ranges = malloc(sizeof(uhci_irq_pio_ranges));
122 if (code->ranges == NULL)
123 return ENOMEM;
124
125 code->cmds = malloc(sizeof(uhci_irq_commands));
126 if (code->cmds == NULL) {
127 free(code->ranges);
128 return ENOMEM;
129 }
130
131 code->rangecount = ARRAY_SIZE(uhci_irq_pio_ranges);
132 code->cmdcount = ARRAY_SIZE(uhci_irq_commands);
133
134 memcpy(code->ranges, uhci_irq_pio_ranges, sizeof(uhci_irq_pio_ranges));
135 code->ranges[0].base = RNGABS(regs);
136
137 memcpy(code->cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
138 uhci_regs_t *registers = (uhci_regs_t *) RNGABSPTR(regs);
139 code->cmds[0].addr = (void*)&registers->usbsts;
140 code->cmds[3].addr = (void*)&registers->usbsts;
141
142 usb_log_debug("I/O regs at %p (size %zu), IRQ %d.\n",
143 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
144
145 return hw_res->irqs.irqs[0];
146}
147
148/** Take action based on the interrupt cause.
149 *
150 * @param[in] hcd HCD structure to use.
151 * @param[in] status Value of the status register at the time of interrupt.
152 *
153 * Interrupt might indicate:
154 * - transaction completed, either by triggering IOC, SPD, or an error
155 * - some kind of device error
156 * - resume from suspend state (not implemented)
157 */
158static void hc_interrupt(bus_t *bus, uint32_t status)
159{
160 hc_t *instance = bus_to_hc(bus);
161
162 /* Lower 2 bits are transaction error and transaction complete */
163 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
164 LIST_INITIALIZE(done);
165 transfer_list_remove_finished(
166 &instance->transfers_interrupt, &done);
167 transfer_list_remove_finished(
168 &instance->transfers_control_slow, &done);
169 transfer_list_remove_finished(
170 &instance->transfers_control_full, &done);
171 transfer_list_remove_finished(
172 &instance->transfers_bulk_full, &done);
173
174 list_foreach_safe(done, current, next) {
175 list_remove(current);
176 uhci_transfer_batch_t *batch =
177 uhci_transfer_batch_from_link(current);
178 usb_transfer_batch_finish(&batch->base);
179 }
180 }
181 /* Resume interrupts are not supported */
182 if (status & UHCI_STATUS_RESUME) {
183 usb_log_error("Resume interrupt!\n");
184 }
185
186 /* Bits 4 and 5 indicate hc error */
187 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
188 usb_log_error("UHCI hardware failure!.\n");
189 ++instance->hw_failures;
190 transfer_list_abort_all(&instance->transfers_interrupt);
191 transfer_list_abort_all(&instance->transfers_control_slow);
192 transfer_list_abort_all(&instance->transfers_control_full);
193 transfer_list_abort_all(&instance->transfers_bulk_full);
194
195 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
196 /* reinitialize hw, this triggers virtual disconnect*/
197 hc_init_hw(instance);
198 } else {
199 usb_log_fatal("Too many UHCI hardware failures!.\n");
200 hc_gone(&instance->base);
201 }
202 }
203}
204
205/** Initialize UHCI hc driver structure
206 *
207 * @param[in] instance Memory place to initialize.
208 * @param[in] regs Range of device's I/O control registers.
209 * @param[in] interrupts True if hw interrupts should be used.
210 * @return Error code.
211 * @note Should be called only once on any structure.
212 *
213 * Initializes memory structures, starts up hw, and launches debugger and
214 * interrupt fibrils.
215 */
216int hc_add(hc_device_t *hcd, const hw_res_list_parsed_t *hw_res)
217{
218 hc_t *instance = hcd_to_hc(hcd);
219 assert(hw_res);
220 if (hw_res->io_ranges.count != 1 ||
221 hw_res->io_ranges.ranges[0].size < sizeof(uhci_regs_t))
222 return EINVAL;
223
224 instance->hw_failures = 0;
225
226 /* allow access to hc control registers */
227 int ret = pio_enable_range(&hw_res->io_ranges.ranges[0],
228 (void **) &instance->registers);
229 if (ret != EOK) {
230 usb_log_error("Failed to gain access to registers: %s.\n",
231 str_error(ret));
232 return ret;
233 }
234
235 usb_log_debug("Device registers at %" PRIx64 " (%zuB) accessible.\n",
236 hw_res->io_ranges.ranges[0].address.absolute,
237 hw_res->io_ranges.ranges[0].size);
238
239 ret = hc_init_mem_structures(instance, hcd);
240 if (ret != EOK) {
241 usb_log_error("Failed to init UHCI memory structures: %s.\n",
242 str_error(ret));
243 // TODO: we should disable pio here
244 return ret;
245 }
246
247 return EOK;
248}
249
250int hc_start(hc_device_t *hcd)
251{
252 hc_t *instance = hcd_to_hc(hcd);
253 hc_init_hw(instance);
254 (void)hc_debug_checker;
255
256 return uhci_rh_init(&instance->rh, instance->registers->ports, "uhci");
257}
258
259/** Safely dispose host controller internal structures
260 *
261 * @param[in] instance Host controller structure to use.
262 */
263int hc_gone(hc_device_t *instance)
264{
265 assert(instance);
266 //TODO Implement
267 return ENOTSUP;
268}
269
270/** Initialize UHCI hc hw resources.
271 *
272 * @param[in] instance UHCI structure to use.
273 * For magic values see UHCI Design Guide
274 */
275void hc_init_hw(const hc_t *instance)
276{
277 assert(instance);
278 uhci_regs_t *registers = instance->registers;
279
280 /* Reset everything, who knows what touched it before us */
281 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
282 async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
283 pio_write_16(&registers->usbcmd, 0);
284
285 /* Reset hc, all states and counters. Hope that hw is not broken */
286 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
287 do { async_usleep(10); }
288 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
289
290 /* Set frame to exactly 1ms */
291 pio_write_8(&registers->sofmod, 64);
292
293 /* Set frame list pointer */
294 const uint32_t pa = addr_to_phys(instance->frame_list);
295 pio_write_32(&registers->flbaseadd, pa);
296
297 if (instance->base.irq_cap >= 0) {
298 /* Enable all interrupts, but resume interrupt */
299 pio_write_16(&instance->registers->usbintr,
300 UHCI_INTR_ALLOW_INTERRUPTS);
301 }
302
303 const uint16_t cmd = pio_read_16(&registers->usbcmd);
304 if (cmd != 0)
305 usb_log_warning("Previous command value: %x.\n", cmd);
306
307 /* Start the hc with large(64B) packet FSBR */
308 pio_write_16(&registers->usbcmd,
309 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
310}
311
312static usb_transfer_batch_t *create_transfer_batch(endpoint_t *ep)
313{
314 uhci_transfer_batch_t *batch = uhci_transfer_batch_create(ep);
315 return &batch->base;
316}
317
318static void destroy_transfer_batch(usb_transfer_batch_t *batch)
319{
320 uhci_transfer_batch_destroy(uhci_transfer_batch_get(batch));
321}
322
323static int hc_status(bus_t *, uint32_t *);
324static int hc_schedule(usb_transfer_batch_t *);
325
326static const bus_ops_t uhci_bus_ops = {
327 .parent = &usb2_bus_ops,
328
329 .interrupt = hc_interrupt,
330 .status = hc_status,
331
332 .endpoint_count_bw = bandwidth_count_usb11,
333 .batch_create = create_transfer_batch,
334 .batch_schedule = hc_schedule,
335 .batch_destroy = destroy_transfer_batch,
336};
337
338/** Initialize UHCI hc memory structures.
339 *
340 * @param[in] instance UHCI structure to use.
341 * @return Error code
342 * @note Should be called only once on any structure.
343 *
344 * Structures:
345 * - transfer lists (queue heads need to be accessible by the hw)
346 * - frame list page (needs to be one UHCI hw accessible 4K page)
347 */
348int hc_init_mem_structures(hc_t *instance, hc_device_t *hcd)
349{
350 int err;
351 assert(instance);
352
353 if ((err = usb2_bus_init(&instance->bus, BANDWIDTH_AVAILABLE_USB11)))
354 return err;
355
356 bus_t *bus = (bus_t *) &instance->bus;
357 bus->ops = &uhci_bus_ops;
358
359 hc_device_setup(&instance->base, bus);
360
361 /* Init USB frame list page */
362 instance->frame_list = get_page();
363 if (!instance->frame_list) {
364 return ENOMEM;
365 }
366 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
367
368 /* Init transfer lists */
369 int ret = hc_init_transfer_lists(instance);
370 if (ret != EOK) {
371 usb_log_error("Failed to initialize transfer lists.\n");
372 return_page(instance->frame_list);
373 return ENOMEM;
374 }
375 usb_log_debug("Initialized transfer lists.\n");
376
377
378 /* Set all frames to point to the first queue head */
379 const uint32_t queue = LINK_POINTER_QH(
380 addr_to_phys(instance->transfers_interrupt.queue_head));
381
382 for (unsigned i = 0; i < UHCI_FRAME_LIST_COUNT; ++i) {
383 instance->frame_list[i] = queue;
384 }
385
386 return EOK;
387}
388
389/** Initialize UHCI hc transfer lists.
390 *
391 * @param[in] instance UHCI structure to use.
392 * @return Error code
393 * @note Should be called only once on any structure.
394 *
395 * Initializes transfer lists and sets them in one chain to support proper
396 * USB scheduling. Sets pointer table for quick access.
397 */
398int hc_init_transfer_lists(hc_t *instance)
399{
400 assert(instance);
401#define SETUP_TRANSFER_LIST(type, name) \
402do { \
403 int ret = transfer_list_init(&instance->transfers_##type, name); \
404 if (ret != EOK) { \
405 usb_log_error("Failed to setup %s transfer list: %s.\n", \
406 name, str_error(ret)); \
407 transfer_list_fini(&instance->transfers_bulk_full); \
408 transfer_list_fini(&instance->transfers_control_full); \
409 transfer_list_fini(&instance->transfers_control_slow); \
410 transfer_list_fini(&instance->transfers_interrupt); \
411 return ret; \
412 } \
413} while (0)
414
415 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
416 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
417 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
418 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
419#undef SETUP_TRANSFER_LIST
420 /* Connect lists into one schedule */
421 transfer_list_set_next(&instance->transfers_control_full,
422 &instance->transfers_bulk_full);
423 transfer_list_set_next(&instance->transfers_control_slow,
424 &instance->transfers_control_full);
425 transfer_list_set_next(&instance->transfers_interrupt,
426 &instance->transfers_control_slow);
427
428 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
429 * buggy on certain hw, enable at your own risk. */
430#ifdef FSBR
431 transfer_list_set_next(&instance->transfers_bulk_full,
432 &instance->transfers_control_full);
433#endif
434
435 /* Assign pointers to be used during scheduling */
436 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
437 &instance->transfers_interrupt;
438 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
439 &instance->transfers_interrupt;
440 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
441 &instance->transfers_control_full;
442 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
443 &instance->transfers_control_slow;
444 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
445 &instance->transfers_bulk_full;
446
447 return EOK;
448}
449
450static int hc_status(bus_t *bus, uint32_t *status)
451{
452 hc_t *instance = bus_to_hc(bus);
453 assert(status);
454
455 *status = 0;
456 if (instance->registers) {
457 uint16_t s = pio_read_16(&instance->registers->usbsts);
458 pio_write_16(&instance->registers->usbsts, s);
459 *status = s;
460 }
461 return EOK;
462}
463
464/** Schedule batch for execution.
465 *
466 * @param[in] instance UHCI structure to use.
467 * @param[in] batch Transfer batch to schedule.
468 * @return Error code
469 *
470 * Checks for bandwidth availability and appends the batch to the proper queue.
471 */
472static int hc_schedule(usb_transfer_batch_t *batch)
473{
474 hc_t *instance = bus_to_hc(endpoint_get_bus(batch->ep));
475 assert(batch);
476
477 if (batch->target.address == uhci_rh_get_address(&instance->rh))
478 return uhci_rh_schedule(&instance->rh, batch);
479
480 uhci_transfer_batch_t *uhci_batch = (uhci_transfer_batch_t *) batch;
481 if (!uhci_batch) {
482 usb_log_error("Failed to create UHCI transfer structures.\n");
483 return ENOMEM;
484 }
485
486 const int err = uhci_transfer_batch_prepare(uhci_batch);
487 if (err)
488 return err;
489
490 transfer_list_t *list =
491 instance->transfers[batch->ep->device->speed][batch->ep->transfer_type];
492 assert(list);
493 transfer_list_add_batch(list, uhci_batch);
494
495 return EOK;
496}
497
498/** Debug function, checks consistency of memory structures.
499 *
500 * @param[in] arg UHCI structure to use.
501 * @return EOK (should never return)
502 */
503int hc_debug_checker(void *arg)
504{
505 hc_t *instance = arg;
506 assert(instance);
507
508#define QH(queue) \
509 instance->transfers_##queue.queue_head
510
511 while (1) {
512 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
513 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
514 const uint16_t intr =
515 pio_read_16(&instance->registers->usbintr);
516
517 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
518 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
519 cmd, sts, intr);
520 }
521
522 const uintptr_t frame_list =
523 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
524 if (frame_list != addr_to_phys(instance->frame_list)) {
525 usb_log_debug("Framelist address: %p vs. %p.\n",
526 (void *) frame_list,
527 (void *) addr_to_phys(instance->frame_list));
528 }
529
530 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
531
532 uintptr_t expected_pa = instance->frame_list[frnum]
533 & LINK_POINTER_ADDRESS_MASK;
534 uintptr_t real_pa = addr_to_phys(QH(interrupt));
535 if (expected_pa != real_pa) {
536 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
537 (void *) expected_pa, frnum, (void *) real_pa);
538 }
539
540 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
541 real_pa = addr_to_phys(QH(control_slow));
542 if (expected_pa != real_pa) {
543 usb_log_debug("Control Slow QH: %p vs. %p.\n",
544 (void *) expected_pa, (void *) real_pa);
545 }
546
547 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
548 real_pa = addr_to_phys(QH(control_full));
549 if (expected_pa != real_pa) {
550 usb_log_debug("Control Full QH: %p vs. %p.\n",
551 (void *) expected_pa, (void *) real_pa);
552 }
553
554 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
555 real_pa = addr_to_phys(QH(bulk_full));
556 if (expected_pa != real_pa ) {
557 usb_log_debug("Bulk QH: %p vs. %p.\n",
558 (void *) expected_pa, (void *) real_pa);
559 }
560 async_usleep(UHCI_DEBUGER_TIMEOUT);
561 }
562 return EOK;
563#undef QH
564}
565/**
566 * @}
567 */
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