source: mainline/uspace/drv/bus/usb/uhci/hc.c@ 3e200736

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 3e200736 was 3e200736, checked in by Jan Vesely <jano.vesely@…>, 12 years ago

uhci,ohci, ehci: Move interrupt replacement fibril to libusbhost
  • Property mode set to 100644
File size: 15.2 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34
35#include <adt/list.h>
36#include <assert.h>
37#include <async.h>
38#include <ddi.h>
39#include <device/hw_res_parsed.h>
40#include <fibril.h>
41#include <errno.h>
42#include <macros.h>
43#include <mem.h>
44#include <stdlib.h>
45#include <str_error.h>
46#include <sys/types.h>
47
48#include <usb/debug.h>
49#include <usb/usb.h>
50
51#include "uhci_batch.h"
52#include "utils/malloc32.h"
53#include "hc.h"
54
55#define UHCI_INTR_ALLOW_INTERRUPTS \
56 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
57#define UHCI_STATUS_USED_INTERRUPTS \
58 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
59
60static const irq_pio_range_t uhci_irq_pio_ranges[] = {
61 {
62 .base = 0,
63 .size = sizeof(uhci_regs_t)
64 }
65};
66
67static const irq_cmd_t uhci_irq_commands[] = {
68 {
69 .cmd = CMD_PIO_READ_16,
70 .dstarg = 1,
71 .addr = NULL
72 },
73 {
74 .cmd = CMD_AND,
75 .srcarg = 1,
76 .dstarg = 2,
77 .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS
78 },
79 {
80 .cmd = CMD_PREDICATE,
81 .srcarg = 2,
82 .value = 2
83 },
84 {
85 .cmd = CMD_PIO_WRITE_A_16,
86 .srcarg = 1,
87 .addr = NULL
88 },
89 {
90 .cmd = CMD_ACCEPT
91 }
92};
93
94static void hc_init_hw(const hc_t *instance);
95static int hc_init_mem_structures(hc_t *instance);
96static int hc_init_transfer_lists(hc_t *instance);
97
98static int hc_debug_checker(void *arg);
99
100
101/** Generate IRQ code.
102 * @param[out] code IRQ code structure.
103 * @param[in] hw_res Device's resources.
104 *
105 * @return Error code.
106 */
107int hc_gen_irq_code(irq_code_t *code, const hw_res_list_parsed_t *hw_res)
108{
109 assert(code);
110 assert(hw_res);
111
112 if (hw_res->irqs.count != 1 || hw_res->io_ranges.count != 1)
113 return EINVAL;
114 const addr_range_t regs = hw_res->io_ranges.ranges[0];
115
116 if (RNGSZ(regs) < sizeof(uhci_regs_t))
117 return EOVERFLOW;
118
119 code->ranges = malloc(sizeof(uhci_irq_pio_ranges));
120 if (code->ranges == NULL)
121 return ENOMEM;
122
123 code->cmds = malloc(sizeof(uhci_irq_commands));
124 if (code->cmds == NULL) {
125 free(code->ranges);
126 return ENOMEM;
127 }
128
129 code->rangecount = ARRAY_SIZE(uhci_irq_pio_ranges);
130 code->cmdcount = ARRAY_SIZE(uhci_irq_commands);
131
132 memcpy(code->ranges, uhci_irq_pio_ranges, sizeof(uhci_irq_pio_ranges));
133 code->ranges[0].base = RNGABS(regs);
134
135 memcpy(code->cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
136 uhci_regs_t *registers = (uhci_regs_t *) RNGABSPTR(regs);
137 code->cmds[0].addr = (void*)&registers->usbsts;
138 code->cmds[3].addr = (void*)&registers->usbsts;
139
140 usb_log_debug("I/O regs at %p (size %zu), IRQ %d.\n",
141 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
142
143 return hw_res->irqs.irqs[0];
144}
145
146/** Take action based on the interrupt cause.
147 *
148 * @param[in] instance UHCI structure to use.
149 * @param[in] status Value of the status register at the time of interrupt.
150 *
151 * Interrupt might indicate:
152 * - transaction completed, either by triggering IOC, SPD, or an error
153 * - some kind of device error
154 * - resume from suspend state (not implemented)
155 */
156void hc_interrupt(hc_t *instance, uint16_t status)
157{
158 assert(instance);
159 /* Lower 2 bits are transaction error and transaction complete */
160 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
161 LIST_INITIALIZE(done);
162 transfer_list_remove_finished(
163 &instance->transfers_interrupt, &done);
164 transfer_list_remove_finished(
165 &instance->transfers_control_slow, &done);
166 transfer_list_remove_finished(
167 &instance->transfers_control_full, &done);
168 transfer_list_remove_finished(
169 &instance->transfers_bulk_full, &done);
170
171 list_foreach_safe(done, current, next) {
172 list_remove(current);
173 uhci_transfer_batch_t *batch =
174 uhci_transfer_batch_from_link(current);
175 uhci_transfer_batch_finish_dispose(batch);
176 }
177 }
178 /* Resume interrupts are not supported */
179 if (status & UHCI_STATUS_RESUME) {
180 usb_log_error("Resume interrupt!\n");
181 }
182
183 /* Bits 4 and 5 indicate hc error */
184 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
185 usb_log_error("UHCI hardware failure!.\n");
186 ++instance->hw_failures;
187 transfer_list_abort_all(&instance->transfers_interrupt);
188 transfer_list_abort_all(&instance->transfers_control_slow);
189 transfer_list_abort_all(&instance->transfers_control_full);
190 transfer_list_abort_all(&instance->transfers_bulk_full);
191
192 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
193 /* reinitialize hw, this triggers virtual disconnect*/
194 hc_init_hw(instance);
195 } else {
196 usb_log_fatal("Too many UHCI hardware failures!.\n");
197 hc_fini(instance);
198 }
199 }
200}
201
202/** Initialize UHCI hc driver structure
203 *
204 * @param[in] instance Memory place to initialize.
205 * @param[in] regs Range of device's I/O control registers.
206 * @param[in] interrupts True if hw interrupts should be used.
207 * @return Error code.
208 * @note Should be called only once on any structure.
209 *
210 * Initializes memory structures, starts up hw, and launches debugger and
211 * interrupt fibrils.
212 */
213int hc_init(hc_t *instance, const hw_res_list_parsed_t *hw_res, bool interrupts)
214{
215 assert(instance);
216 assert(hw_res);
217 if (hw_res->io_ranges.count != 1 ||
218 hw_res->io_ranges.ranges[0].size < sizeof(uhci_regs_t))
219 return EINVAL;
220
221 instance->hw_interrupts = interrupts;
222 instance->hw_failures = 0;
223
224 /* allow access to hc control registers */
225 int ret = pio_enable_range(&hw_res->io_ranges.ranges[0],
226 (void **) &instance->registers);
227 if (ret != EOK) {
228 usb_log_error("Failed to gain access to registers: %s.\n",
229 str_error(ret));
230 return ret;
231 }
232
233 usb_log_debug("Device registers at %" PRIx64 " (%zuB) accessible.\n",
234 hw_res->io_ranges.ranges[0].address.absolute,
235 hw_res->io_ranges.ranges[0].size);
236
237 ret = hc_init_mem_structures(instance);
238 if (ret != EOK) {
239 usb_log_error("Failed to init UHCI memory structures: %s.\n",
240 str_error(ret));
241 // TODO: we should disable pio here
242 return ret;
243 }
244
245 hc_init_hw(instance);
246 (void)hc_debug_checker;
247
248 uhci_rh_init(&instance->rh, instance->registers->ports, "uhci");
249
250 return EOK;
251}
252
253/** Safely dispose host controller internal structures
254 *
255 * @param[in] instance Host controller structure to use.
256 */
257void hc_fini(hc_t *instance)
258{
259 assert(instance);
260 //TODO Implement
261}
262
263/** Initialize UHCI hc hw resources.
264 *
265 * @param[in] instance UHCI structure to use.
266 * For magic values see UHCI Design Guide
267 */
268void hc_init_hw(const hc_t *instance)
269{
270 assert(instance);
271 uhci_regs_t *registers = instance->registers;
272
273 /* Reset everything, who knows what touched it before us */
274 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
275 async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
276 pio_write_16(&registers->usbcmd, 0);
277
278 /* Reset hc, all states and counters. Hope that hw is not broken */
279 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
280 do { async_usleep(10); }
281 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
282
283 /* Set frame to exactly 1ms */
284 pio_write_8(&registers->sofmod, 64);
285
286 /* Set frame list pointer */
287 const uint32_t pa = addr_to_phys(instance->frame_list);
288 pio_write_32(&registers->flbaseadd, pa);
289
290 if (instance->hw_interrupts) {
291 /* Enable all interrupts, but resume interrupt */
292 pio_write_16(&instance->registers->usbintr,
293 UHCI_INTR_ALLOW_INTERRUPTS);
294 }
295
296 const uint16_t cmd = pio_read_16(&registers->usbcmd);
297 if (cmd != 0)
298 usb_log_warning("Previous command value: %x.\n", cmd);
299
300 /* Start the hc with large(64B) packet FSBR */
301 pio_write_16(&registers->usbcmd,
302 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
303}
304
305/** Initialize UHCI hc memory structures.
306 *
307 * @param[in] instance UHCI structure to use.
308 * @return Error code
309 * @note Should be called only once on any structure.
310 *
311 * Structures:
312 * - transfer lists (queue heads need to be accessible by the hw)
313 * - frame list page (needs to be one UHCI hw accessible 4K page)
314 */
315int hc_init_mem_structures(hc_t *instance)
316{
317 assert(instance);
318
319 /* Init USB frame list page */
320 instance->frame_list = get_page();
321 if (!instance->frame_list) {
322 return ENOMEM;
323 }
324 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
325
326 /* Init transfer lists */
327 int ret = hc_init_transfer_lists(instance);
328 if (ret != EOK) {
329 usb_log_error("Failed to initialize transfer lists.\n");
330 return_page(instance->frame_list);
331 return ENOMEM;
332 }
333 usb_log_debug("Initialized transfer lists.\n");
334
335
336 /* Set all frames to point to the first queue head */
337 const uint32_t queue = LINK_POINTER_QH(
338 addr_to_phys(instance->transfers_interrupt.queue_head));
339
340 for (unsigned i = 0; i < UHCI_FRAME_LIST_COUNT; ++i) {
341 instance->frame_list[i] = queue;
342 }
343
344 return EOK;
345}
346
347/** Initialize UHCI hc transfer lists.
348 *
349 * @param[in] instance UHCI structure to use.
350 * @return Error code
351 * @note Should be called only once on any structure.
352 *
353 * Initializes transfer lists and sets them in one chain to support proper
354 * USB scheduling. Sets pointer table for quick access.
355 */
356int hc_init_transfer_lists(hc_t *instance)
357{
358 assert(instance);
359#define SETUP_TRANSFER_LIST(type, name) \
360do { \
361 int ret = transfer_list_init(&instance->transfers_##type, name); \
362 if (ret != EOK) { \
363 usb_log_error("Failed to setup %s transfer list: %s.\n", \
364 name, str_error(ret)); \
365 transfer_list_fini(&instance->transfers_bulk_full); \
366 transfer_list_fini(&instance->transfers_control_full); \
367 transfer_list_fini(&instance->transfers_control_slow); \
368 transfer_list_fini(&instance->transfers_interrupt); \
369 return ret; \
370 } \
371} while (0)
372
373 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
374 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
375 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
376 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
377#undef SETUP_TRANSFER_LIST
378 /* Connect lists into one schedule */
379 transfer_list_set_next(&instance->transfers_control_full,
380 &instance->transfers_bulk_full);
381 transfer_list_set_next(&instance->transfers_control_slow,
382 &instance->transfers_control_full);
383 transfer_list_set_next(&instance->transfers_interrupt,
384 &instance->transfers_control_slow);
385
386 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
387 * buggy on certain hw, enable at your own risk. */
388#ifdef FSBR
389 transfer_list_set_next(&instance->transfers_bulk_full,
390 &instance->transfers_control_full);
391#endif
392
393 /* Assign pointers to be used during scheduling */
394 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
395 &instance->transfers_interrupt;
396 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
397 &instance->transfers_interrupt;
398 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
399 &instance->transfers_control_full;
400 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
401 &instance->transfers_control_slow;
402 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
403 &instance->transfers_bulk_full;
404
405 return EOK;
406}
407
408int hc_status(hcd_t *hcd, uint32_t *status)
409{
410 assert(hcd);
411 assert(status);
412 hc_t *instance = hcd->driver.data;
413 assert(instance);
414
415 *status = 0;
416 if (instance->registers) {
417 uint16_t s = pio_read_16(&instance->registers->usbsts);
418 pio_write_16(&instance->registers->usbsts, s);
419 *status = s;
420 }
421 return EOK;
422}
423
424/** Schedule batch for execution.
425 *
426 * @param[in] instance UHCI structure to use.
427 * @param[in] batch Transfer batch to schedule.
428 * @return Error code
429 *
430 * Checks for bandwidth availability and appends the batch to the proper queue.
431 */
432int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
433{
434 assert(hcd);
435 hc_t *instance = hcd->driver.data;
436 assert(instance);
437 assert(batch);
438
439 if (batch->ep->address == uhci_rh_get_address(&instance->rh))
440 return uhci_rh_schedule(&instance->rh, batch);
441
442 uhci_transfer_batch_t *uhci_batch = uhci_transfer_batch_get(batch);
443 if (!uhci_batch) {
444 usb_log_error("Failed to create UHCI transfer structures.\n");
445 return ENOMEM;
446 }
447
448 transfer_list_t *list =
449 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
450 assert(list);
451 transfer_list_add_batch(list, uhci_batch);
452
453 return EOK;
454}
455
456/** Debug function, checks consistency of memory structures.
457 *
458 * @param[in] arg UHCI structure to use.
459 * @return EOK (should never return)
460 */
461int hc_debug_checker(void *arg)
462{
463 hc_t *instance = arg;
464 assert(instance);
465
466#define QH(queue) \
467 instance->transfers_##queue.queue_head
468
469 while (1) {
470 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
471 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
472 const uint16_t intr =
473 pio_read_16(&instance->registers->usbintr);
474
475 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
476 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
477 cmd, sts, intr);
478 }
479
480 const uintptr_t frame_list =
481 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
482 if (frame_list != addr_to_phys(instance->frame_list)) {
483 usb_log_debug("Framelist address: %p vs. %p.\n",
484 (void *) frame_list,
485 (void *) addr_to_phys(instance->frame_list));
486 }
487
488 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
489
490 uintptr_t expected_pa = instance->frame_list[frnum]
491 & LINK_POINTER_ADDRESS_MASK;
492 uintptr_t real_pa = addr_to_phys(QH(interrupt));
493 if (expected_pa != real_pa) {
494 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
495 (void *) expected_pa, frnum, (void *) real_pa);
496 }
497
498 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
499 real_pa = addr_to_phys(QH(control_slow));
500 if (expected_pa != real_pa) {
501 usb_log_debug("Control Slow QH: %p vs. %p.\n",
502 (void *) expected_pa, (void *) real_pa);
503 }
504
505 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
506 real_pa = addr_to_phys(QH(control_full));
507 if (expected_pa != real_pa) {
508 usb_log_debug("Control Full QH: %p vs. %p.\n",
509 (void *) expected_pa, (void *) real_pa);
510 }
511
512 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
513 real_pa = addr_to_phys(QH(bulk_full));
514 if (expected_pa != real_pa ) {
515 usb_log_debug("Bulk QH: %p vs. %p.\n",
516 (void *) expected_pa, (void *) real_pa);
517 }
518 async_usleep(UHCI_DEBUGER_TIMEOUT);
519 }
520 return EOK;
521#undef QH
522}
523/**
524 * @}
525 */
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