source: mainline/uspace/drv/bus/usb/uhci/hc.c@ 10cd715

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 10cd715 was 888238e9, checked in by Aearsis <Hlavaty.Ondrej@…>, 8 years ago

usbhost: endpoints do not have speed on their own

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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbuhcihc
30 * @{
31 */
32/** @file
33 * @brief UHCI Host controller driver routines
34 */
35
36#include <adt/list.h>
37#include <assert.h>
38#include <async.h>
39#include <ddi.h>
40#include <device/hw_res_parsed.h>
41#include <fibril.h>
42#include <errno.h>
43#include <macros.h>
44#include <mem.h>
45#include <stdlib.h>
46#include <stdint.h>
47#include <str_error.h>
48
49#include <usb/debug.h>
50#include <usb/usb.h>
51#include <usb/host/utils/malloc32.h>
52#include <usb/host/bandwidth.h>
53
54#include "uhci_batch.h"
55#include "hc.h"
56
57#define UHCI_INTR_ALLOW_INTERRUPTS \
58 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
59#define UHCI_STATUS_USED_INTERRUPTS \
60 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
61
62static const irq_pio_range_t uhci_irq_pio_ranges[] = {
63 {
64 .base = 0,
65 .size = sizeof(uhci_regs_t)
66 }
67};
68
69static const irq_cmd_t uhci_irq_commands[] = {
70 {
71 .cmd = CMD_PIO_READ_16,
72 .dstarg = 1,
73 .addr = NULL
74 },
75 {
76 .cmd = CMD_AND,
77 .srcarg = 1,
78 .dstarg = 2,
79 .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS
80 },
81 {
82 .cmd = CMD_PREDICATE,
83 .srcarg = 2,
84 .value = 2
85 },
86 {
87 .cmd = CMD_PIO_WRITE_A_16,
88 .srcarg = 1,
89 .addr = NULL
90 },
91 {
92 .cmd = CMD_ACCEPT
93 }
94};
95
96static void hc_init_hw(const hc_t *instance);
97static int hc_init_mem_structures(hc_t *instance);
98static int hc_init_transfer_lists(hc_t *instance);
99
100static int hc_debug_checker(void *arg);
101
102
103/** Generate IRQ code.
104 * @param[out] code IRQ code structure.
105 * @param[in] hw_res Device's resources.
106 *
107 * @return Error code.
108 */
109int uhci_hc_gen_irq_code(irq_code_t *code, hcd_t *hcd, const hw_res_list_parsed_t *hw_res)
110{
111 assert(code);
112 assert(hw_res);
113
114 if (hw_res->irqs.count != 1 || hw_res->io_ranges.count != 1)
115 return EINVAL;
116 const addr_range_t regs = hw_res->io_ranges.ranges[0];
117
118 if (RNGSZ(regs) < sizeof(uhci_regs_t))
119 return EOVERFLOW;
120
121 code->ranges = malloc(sizeof(uhci_irq_pio_ranges));
122 if (code->ranges == NULL)
123 return ENOMEM;
124
125 code->cmds = malloc(sizeof(uhci_irq_commands));
126 if (code->cmds == NULL) {
127 free(code->ranges);
128 return ENOMEM;
129 }
130
131 code->rangecount = ARRAY_SIZE(uhci_irq_pio_ranges);
132 code->cmdcount = ARRAY_SIZE(uhci_irq_commands);
133
134 memcpy(code->ranges, uhci_irq_pio_ranges, sizeof(uhci_irq_pio_ranges));
135 code->ranges[0].base = RNGABS(regs);
136
137 memcpy(code->cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
138 uhci_regs_t *registers = (uhci_regs_t *) RNGABSPTR(regs);
139 code->cmds[0].addr = (void*)&registers->usbsts;
140 code->cmds[3].addr = (void*)&registers->usbsts;
141
142 usb_log_debug("I/O regs at %p (size %zu), IRQ %d.\n",
143 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
144
145 return hw_res->irqs.irqs[0];
146}
147
148/** Take action based on the interrupt cause.
149 *
150 * @param[in] hcd HCD structure to use.
151 * @param[in] status Value of the status register at the time of interrupt.
152 *
153 * Interrupt might indicate:
154 * - transaction completed, either by triggering IOC, SPD, or an error
155 * - some kind of device error
156 * - resume from suspend state (not implemented)
157 */
158void uhci_hc_interrupt(hcd_t *hcd, uint32_t status)
159{
160 assert(hcd);
161 hc_t *instance = hcd_get_driver_data(hcd);
162 assert(instance);
163 /* Lower 2 bits are transaction error and transaction complete */
164 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
165 LIST_INITIALIZE(done);
166 transfer_list_remove_finished(
167 &instance->transfers_interrupt, &done);
168 transfer_list_remove_finished(
169 &instance->transfers_control_slow, &done);
170 transfer_list_remove_finished(
171 &instance->transfers_control_full, &done);
172 transfer_list_remove_finished(
173 &instance->transfers_bulk_full, &done);
174
175 list_foreach_safe(done, current, next) {
176 list_remove(current);
177 uhci_transfer_batch_t *batch =
178 uhci_transfer_batch_from_link(current);
179 usb_transfer_batch_finish(&batch->base);
180 }
181 }
182 /* Resume interrupts are not supported */
183 if (status & UHCI_STATUS_RESUME) {
184 usb_log_error("Resume interrupt!\n");
185 }
186
187 /* Bits 4 and 5 indicate hc error */
188 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
189 usb_log_error("UHCI hardware failure!.\n");
190 ++instance->hw_failures;
191 transfer_list_abort_all(&instance->transfers_interrupt);
192 transfer_list_abort_all(&instance->transfers_control_slow);
193 transfer_list_abort_all(&instance->transfers_control_full);
194 transfer_list_abort_all(&instance->transfers_bulk_full);
195
196 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
197 /* reinitialize hw, this triggers virtual disconnect*/
198 hc_init_hw(instance);
199 } else {
200 usb_log_fatal("Too many UHCI hardware failures!.\n");
201 hc_fini(instance);
202 }
203 }
204}
205
206/** Initialize UHCI hc driver structure
207 *
208 * @param[in] instance Memory place to initialize.
209 * @param[in] regs Range of device's I/O control registers.
210 * @param[in] interrupts True if hw interrupts should be used.
211 * @return Error code.
212 * @note Should be called only once on any structure.
213 *
214 * Initializes memory structures, starts up hw, and launches debugger and
215 * interrupt fibrils.
216 */
217int hc_init(hc_t *instance, const hw_res_list_parsed_t *hw_res)
218{
219 assert(instance);
220 assert(hw_res);
221 if (hw_res->io_ranges.count != 1 ||
222 hw_res->io_ranges.ranges[0].size < sizeof(uhci_regs_t))
223 return EINVAL;
224
225 instance->hw_failures = 0;
226
227 /* allow access to hc control registers */
228 int ret = pio_enable_range(&hw_res->io_ranges.ranges[0],
229 (void **) &instance->registers);
230 if (ret != EOK) {
231 usb_log_error("Failed to gain access to registers: %s.\n",
232 str_error(ret));
233 return ret;
234 }
235
236 usb_log_debug("Device registers at %" PRIx64 " (%zuB) accessible.\n",
237 hw_res->io_ranges.ranges[0].address.absolute,
238 hw_res->io_ranges.ranges[0].size);
239
240 ret = hc_init_mem_structures(instance);
241 if (ret != EOK) {
242 usb_log_error("Failed to init UHCI memory structures: %s.\n",
243 str_error(ret));
244 // TODO: we should disable pio here
245 return ret;
246 }
247
248 return EOK;
249}
250
251void hc_start(hc_t *instance)
252{
253 hc_init_hw(instance);
254 (void)hc_debug_checker;
255
256 uhci_rh_init(&instance->rh, instance->registers->ports, "uhci");
257}
258
259/** Safely dispose host controller internal structures
260 *
261 * @param[in] instance Host controller structure to use.
262 */
263void hc_fini(hc_t *instance)
264{
265 assert(instance);
266 //TODO Implement
267}
268
269/** Initialize UHCI hc hw resources.
270 *
271 * @param[in] instance UHCI structure to use.
272 * For magic values see UHCI Design Guide
273 */
274void hc_init_hw(const hc_t *instance)
275{
276 assert(instance);
277 uhci_regs_t *registers = instance->registers;
278
279 /* Reset everything, who knows what touched it before us */
280 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
281 async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
282 pio_write_16(&registers->usbcmd, 0);
283
284 /* Reset hc, all states and counters. Hope that hw is not broken */
285 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
286 do { async_usleep(10); }
287 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
288
289 /* Set frame to exactly 1ms */
290 pio_write_8(&registers->sofmod, 64);
291
292 /* Set frame list pointer */
293 const uint32_t pa = addr_to_phys(instance->frame_list);
294 pio_write_32(&registers->flbaseadd, pa);
295
296 if (instance->hw_interrupts) {
297 /* Enable all interrupts, but resume interrupt */
298 pio_write_16(&instance->registers->usbintr,
299 UHCI_INTR_ALLOW_INTERRUPTS);
300 }
301
302 const uint16_t cmd = pio_read_16(&registers->usbcmd);
303 if (cmd != 0)
304 usb_log_warning("Previous command value: %x.\n", cmd);
305
306 /* Start the hc with large(64B) packet FSBR */
307 pio_write_16(&registers->usbcmd,
308 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
309}
310
311static usb_transfer_batch_t *create_transfer_batch(bus_t *bus, endpoint_t *ep)
312{
313 uhci_transfer_batch_t *batch = uhci_transfer_batch_create(ep);
314 return &batch->base;
315}
316
317static void destroy_transfer_batch(usb_transfer_batch_t *batch)
318{
319 uhci_transfer_batch_destroy(uhci_transfer_batch_get(batch));
320}
321
322/** Initialize UHCI hc memory structures.
323 *
324 * @param[in] instance UHCI structure to use.
325 * @return Error code
326 * @note Should be called only once on any structure.
327 *
328 * Structures:
329 * - transfer lists (queue heads need to be accessible by the hw)
330 * - frame list page (needs to be one UHCI hw accessible 4K page)
331 */
332int hc_init_mem_structures(hc_t *instance)
333{
334 int err;
335 assert(instance);
336
337 if ((err = usb2_bus_init(&instance->bus, BANDWIDTH_AVAILABLE_USB11, bandwidth_count_usb11)))
338 return err;
339
340 instance->bus.base.ops.create_batch = create_transfer_batch;
341 instance->bus.base.ops.destroy_batch = destroy_transfer_batch;
342
343 /* Init USB frame list page */
344 instance->frame_list = get_page();
345 if (!instance->frame_list) {
346 return ENOMEM;
347 }
348 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
349
350 /* Init transfer lists */
351 int ret = hc_init_transfer_lists(instance);
352 if (ret != EOK) {
353 usb_log_error("Failed to initialize transfer lists.\n");
354 return_page(instance->frame_list);
355 return ENOMEM;
356 }
357 usb_log_debug("Initialized transfer lists.\n");
358
359
360 /* Set all frames to point to the first queue head */
361 const uint32_t queue = LINK_POINTER_QH(
362 addr_to_phys(instance->transfers_interrupt.queue_head));
363
364 for (unsigned i = 0; i < UHCI_FRAME_LIST_COUNT; ++i) {
365 instance->frame_list[i] = queue;
366 }
367
368 return EOK;
369}
370
371/** Initialize UHCI hc transfer lists.
372 *
373 * @param[in] instance UHCI structure to use.
374 * @return Error code
375 * @note Should be called only once on any structure.
376 *
377 * Initializes transfer lists and sets them in one chain to support proper
378 * USB scheduling. Sets pointer table for quick access.
379 */
380int hc_init_transfer_lists(hc_t *instance)
381{
382 assert(instance);
383#define SETUP_TRANSFER_LIST(type, name) \
384do { \
385 int ret = transfer_list_init(&instance->transfers_##type, name); \
386 if (ret != EOK) { \
387 usb_log_error("Failed to setup %s transfer list: %s.\n", \
388 name, str_error(ret)); \
389 transfer_list_fini(&instance->transfers_bulk_full); \
390 transfer_list_fini(&instance->transfers_control_full); \
391 transfer_list_fini(&instance->transfers_control_slow); \
392 transfer_list_fini(&instance->transfers_interrupt); \
393 return ret; \
394 } \
395} while (0)
396
397 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
398 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
399 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
400 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
401#undef SETUP_TRANSFER_LIST
402 /* Connect lists into one schedule */
403 transfer_list_set_next(&instance->transfers_control_full,
404 &instance->transfers_bulk_full);
405 transfer_list_set_next(&instance->transfers_control_slow,
406 &instance->transfers_control_full);
407 transfer_list_set_next(&instance->transfers_interrupt,
408 &instance->transfers_control_slow);
409
410 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
411 * buggy on certain hw, enable at your own risk. */
412#ifdef FSBR
413 transfer_list_set_next(&instance->transfers_bulk_full,
414 &instance->transfers_control_full);
415#endif
416
417 /* Assign pointers to be used during scheduling */
418 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
419 &instance->transfers_interrupt;
420 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
421 &instance->transfers_interrupt;
422 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
423 &instance->transfers_control_full;
424 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
425 &instance->transfers_control_slow;
426 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
427 &instance->transfers_bulk_full;
428
429 return EOK;
430}
431
432int uhci_hc_status(hcd_t *hcd, uint32_t *status)
433{
434 assert(hcd);
435 assert(status);
436 hc_t *instance = hcd_get_driver_data(hcd);
437 assert(instance);
438
439 *status = 0;
440 if (instance->registers) {
441 uint16_t s = pio_read_16(&instance->registers->usbsts);
442 pio_write_16(&instance->registers->usbsts, s);
443 *status = s;
444 }
445 return EOK;
446}
447
448/** Schedule batch for execution.
449 *
450 * @param[in] instance UHCI structure to use.
451 * @param[in] batch Transfer batch to schedule.
452 * @return Error code
453 *
454 * Checks for bandwidth availability and appends the batch to the proper queue.
455 */
456int uhci_hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
457{
458 assert(hcd);
459 hc_t *instance = hcd_get_driver_data(hcd);
460 assert(instance);
461 assert(batch);
462
463 if (batch->target.address == uhci_rh_get_address(&instance->rh))
464 return uhci_rh_schedule(&instance->rh, batch);
465
466 uhci_transfer_batch_t *uhci_batch = (uhci_transfer_batch_t *) batch;
467 if (!uhci_batch) {
468 usb_log_error("Failed to create UHCI transfer structures.\n");
469 return ENOMEM;
470 }
471
472 const int err = uhci_transfer_batch_prepare(uhci_batch);
473 if (err)
474 return err;
475
476 transfer_list_t *list =
477 instance->transfers[batch->ep->device->speed][batch->ep->transfer_type];
478 assert(list);
479 transfer_list_add_batch(list, uhci_batch);
480
481 return EOK;
482}
483
484/** Debug function, checks consistency of memory structures.
485 *
486 * @param[in] arg UHCI structure to use.
487 * @return EOK (should never return)
488 */
489int hc_debug_checker(void *arg)
490{
491 hc_t *instance = arg;
492 assert(instance);
493
494#define QH(queue) \
495 instance->transfers_##queue.queue_head
496
497 while (1) {
498 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
499 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
500 const uint16_t intr =
501 pio_read_16(&instance->registers->usbintr);
502
503 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
504 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
505 cmd, sts, intr);
506 }
507
508 const uintptr_t frame_list =
509 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
510 if (frame_list != addr_to_phys(instance->frame_list)) {
511 usb_log_debug("Framelist address: %p vs. %p.\n",
512 (void *) frame_list,
513 (void *) addr_to_phys(instance->frame_list));
514 }
515
516 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
517
518 uintptr_t expected_pa = instance->frame_list[frnum]
519 & LINK_POINTER_ADDRESS_MASK;
520 uintptr_t real_pa = addr_to_phys(QH(interrupt));
521 if (expected_pa != real_pa) {
522 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
523 (void *) expected_pa, frnum, (void *) real_pa);
524 }
525
526 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
527 real_pa = addr_to_phys(QH(control_slow));
528 if (expected_pa != real_pa) {
529 usb_log_debug("Control Slow QH: %p vs. %p.\n",
530 (void *) expected_pa, (void *) real_pa);
531 }
532
533 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
534 real_pa = addr_to_phys(QH(control_full));
535 if (expected_pa != real_pa) {
536 usb_log_debug("Control Full QH: %p vs. %p.\n",
537 (void *) expected_pa, (void *) real_pa);
538 }
539
540 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
541 real_pa = addr_to_phys(QH(bulk_full));
542 if (expected_pa != real_pa ) {
543 usb_log_debug("Bulk QH: %p vs. %p.\n",
544 (void *) expected_pa, (void *) real_pa);
545 }
546 async_usleep(UHCI_DEBUGER_TIMEOUT);
547 }
548 return EOK;
549#undef QH
550}
551/**
552 * @}
553 */
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