source: mainline/uspace/drv/bus/usb/uhci/hc.c@ 0ef03d7

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 0ef03d7 was a720ff6, checked in by Jan Vesely <jano.vesely@…>, 13 years ago

uhci: Use helper routines provided by libusbhost
  • Property mode set to 100644
File size: 15.1 KB
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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41
42#include "hc.h"
43#include "uhci_batch.h"
44
45#define UHCI_INTR_ALLOW_INTERRUPTS \
46 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
47#define UHCI_STATUS_USED_INTERRUPTS \
48 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
49
50static const irq_pio_range_t uhci_irq_pio_ranges[] = {
51 {
52 .base = 0,
53 .size = sizeof(uhci_regs_t)
54 }
55};
56
57static const irq_cmd_t uhci_irq_commands[] = {
58 {
59 .cmd = CMD_PIO_READ_16,
60 .dstarg = 1,
61 .addr = NULL
62 },
63 {
64 .cmd = CMD_AND,
65 .srcarg = 1,
66 .dstarg = 2,
67 .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS
68 },
69 {
70 .cmd = CMD_PREDICATE,
71 .srcarg = 2,
72 .value = 2
73 },
74 {
75 .cmd = CMD_PIO_WRITE_A_16,
76 .srcarg = 1,
77 .addr = NULL
78 },
79 {
80 .cmd = CMD_ACCEPT
81 }
82};
83
84static void hc_init_hw(const hc_t *instance);
85static int hc_init_mem_structures(hc_t *instance);
86static int hc_init_transfer_lists(hc_t *instance);
87
88static int hc_interrupt_emulator(void *arg);
89static int hc_debug_checker(void *arg);
90
91
92/** Get number of PIO ranges used in IRQ code.
93 * @return Number of ranges.
94 */
95size_t hc_irq_pio_range_count(void)
96{
97 return sizeof(uhci_irq_pio_ranges) / sizeof(irq_pio_range_t);
98}
99
100/** Get number of commands used in IRQ code.
101 * @return Number of commands.
102 */
103size_t hc_irq_cmd_count(void)
104{
105 return sizeof(uhci_irq_commands) / sizeof(irq_cmd_t);
106}
107
108/** Generate IRQ code.
109 * @param[out] ranges PIO ranges buffer.
110 * @param[in] ranges_size Size of the ranges buffer (bytes).
111 * @param[out] cmds Commands buffer.
112 * @param[in] cmds_size Size of the commands buffer (bytes).
113 * @param[in] regs Physical address of device's registers.
114 * @param[in] reg_size Size of the register area (bytes).
115 *
116 * @return Error code.
117 */
118int
119hc_get_irq_code(irq_pio_range_t ranges[], size_t ranges_size, irq_cmd_t cmds[],
120 size_t cmds_size, uintptr_t regs, size_t reg_size)
121{
122 if ((ranges_size < sizeof(uhci_irq_pio_ranges)) ||
123 (cmds_size < sizeof(uhci_irq_commands)) ||
124 (reg_size < sizeof(uhci_regs_t)))
125 return EOVERFLOW;
126
127 memcpy(ranges, uhci_irq_pio_ranges, sizeof(uhci_irq_pio_ranges));
128 ranges[0].base = regs;
129
130 memcpy(cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
131 uhci_regs_t *registers = (uhci_regs_t *) regs;
132 cmds[0].addr = &registers->usbsts;
133 cmds[3].addr = &registers->usbsts;
134
135 return EOK;
136}
137
138/** Take action based on the interrupt cause.
139 *
140 * @param[in] instance UHCI structure to use.
141 * @param[in] status Value of the status register at the time of interrupt.
142 *
143 * Interrupt might indicate:
144 * - transaction completed, either by triggering IOC, SPD, or an error
145 * - some kind of device error
146 * - resume from suspend state (not implemented)
147 */
148void hc_interrupt(hc_t *instance, uint16_t status)
149{
150 assert(instance);
151 /* Lower 2 bits are transaction error and transaction complete */
152 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
153 LIST_INITIALIZE(done);
154 transfer_list_remove_finished(
155 &instance->transfers_interrupt, &done);
156 transfer_list_remove_finished(
157 &instance->transfers_control_slow, &done);
158 transfer_list_remove_finished(
159 &instance->transfers_control_full, &done);
160 transfer_list_remove_finished(
161 &instance->transfers_bulk_full, &done);
162
163 while (!list_empty(&done)) {
164 link_t *item = list_first(&done);
165 list_remove(item);
166 uhci_transfer_batch_t *batch =
167 uhci_transfer_batch_from_link(item);
168 uhci_transfer_batch_finish_dispose(batch);
169 }
170 }
171 /* Resume interrupts are not supported */
172 if (status & UHCI_STATUS_RESUME) {
173 usb_log_error("Resume interrupt!\n");
174 }
175
176 /* Bits 4 and 5 indicate hc error */
177 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
178 usb_log_error("UHCI hardware failure!.\n");
179 ++instance->hw_failures;
180 transfer_list_abort_all(&instance->transfers_interrupt);
181 transfer_list_abort_all(&instance->transfers_control_slow);
182 transfer_list_abort_all(&instance->transfers_control_full);
183 transfer_list_abort_all(&instance->transfers_bulk_full);
184
185 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
186 /* reinitialize hw, this triggers virtual disconnect*/
187 hc_init_hw(instance);
188 } else {
189 usb_log_fatal("Too many UHCI hardware failures!.\n");
190 hc_fini(instance);
191 }
192 }
193}
194
195/** Initialize UHCI hc driver structure
196 *
197 * @param[in] instance Memory place to initialize.
198 * @param[in] regs Address of I/O control registers.
199 * @param[in] reg_size Size of I/O control registers.
200 * @param[in] interrupts True if hw interrupts should be used.
201 * @return Error code.
202 * @note Should be called only once on any structure.
203 *
204 * Initializes memory structures, starts up hw, and launches debugger and
205 * interrupt fibrils.
206 */
207int hc_init(hc_t *instance, void *regs, size_t reg_size, bool interrupts)
208{
209 assert(reg_size >= sizeof(uhci_regs_t));
210 int ret;
211
212#define CHECK_RET_RETURN(ret, message...) \
213 if (ret != EOK) { \
214 usb_log_error(message); \
215 return ret; \
216 } else (void) 0
217
218 instance->hw_interrupts = interrupts;
219 instance->hw_failures = 0;
220
221 /* allow access to hc control registers */
222 uhci_regs_t *io;
223 ret = pio_enable(regs, reg_size, (void **)&io);
224 CHECK_RET_RETURN(ret, "Failed to gain access to registers at %p: %s.\n",
225 io, str_error(ret));
226 instance->registers = io;
227 usb_log_debug(
228 "Device registers at %p (%zuB) accessible.\n", io, reg_size);
229
230 ret = hc_init_mem_structures(instance);
231 CHECK_RET_RETURN(ret,
232 "Failed to initialize UHCI memory structures: %s.\n",
233 str_error(ret));
234
235#undef CHECK_RET_RETURN
236
237 hc_init_hw(instance);
238 if (!interrupts) {
239 instance->interrupt_emulator =
240 fibril_create(hc_interrupt_emulator, instance);
241 fibril_add_ready(instance->interrupt_emulator);
242 }
243 (void)hc_debug_checker;
244
245 return EOK;
246}
247
248/** Initialize UHCI hc hw resources.
249 *
250 * @param[in] instance UHCI structure to use.
251 * For magic values see UHCI Design Guide
252 */
253void hc_init_hw(const hc_t *instance)
254{
255 assert(instance);
256 uhci_regs_t *registers = instance->registers;
257
258 /* Reset everything, who knows what touched it before us */
259 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
260 async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
261 pio_write_16(&registers->usbcmd, 0);
262
263 /* Reset hc, all states and counters. Hope that hw is not broken */
264 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
265 do { async_usleep(10); }
266 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
267
268 /* Set frame to exactly 1ms */
269 pio_write_8(&registers->sofmod, 64);
270
271 /* Set frame list pointer */
272 const uint32_t pa = addr_to_phys(instance->frame_list);
273 pio_write_32(&registers->flbaseadd, pa);
274
275 if (instance->hw_interrupts) {
276 /* Enable all interrupts, but resume interrupt */
277 pio_write_16(&instance->registers->usbintr,
278 UHCI_INTR_ALLOW_INTERRUPTS);
279 }
280
281 const uint16_t cmd = pio_read_16(&registers->usbcmd);
282 if (cmd != 0)
283 usb_log_warning("Previous command value: %x.\n", cmd);
284
285 /* Start the hc with large(64B) packet FSBR */
286 pio_write_16(&registers->usbcmd,
287 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
288}
289
290/** Initialize UHCI hc memory structures.
291 *
292 * @param[in] instance UHCI structure to use.
293 * @return Error code
294 * @note Should be called only once on any structure.
295 *
296 * Structures:
297 * - transfer lists (queue heads need to be accessible by the hw)
298 * - frame list page (needs to be one UHCI hw accessible 4K page)
299 */
300int hc_init_mem_structures(hc_t *instance)
301{
302 assert(instance);
303
304 /* Init USB frame list page */
305 instance->frame_list = get_page();
306 if (!instance->frame_list) {
307 return ENOMEM;
308 }
309 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
310
311 /* Init transfer lists */
312 int ret = hc_init_transfer_lists(instance);
313 if (ret != EOK) {
314 usb_log_error("Failed to initialize transfer lists.\n");
315 return_page(instance->frame_list);
316 return ENOMEM;
317 }
318 usb_log_debug("Initialized transfer lists.\n");
319
320
321 /* Set all frames to point to the first queue head */
322 const uint32_t queue = LINK_POINTER_QH(
323 addr_to_phys(instance->transfers_interrupt.queue_head));
324
325 for (unsigned i = 0; i < UHCI_FRAME_LIST_COUNT; ++i) {
326 instance->frame_list[i] = queue;
327 }
328
329 return EOK;
330}
331
332/** Initialize UHCI hc transfer lists.
333 *
334 * @param[in] instance UHCI structure to use.
335 * @return Error code
336 * @note Should be called only once on any structure.
337 *
338 * Initializes transfer lists and sets them in one chain to support proper
339 * USB scheduling. Sets pointer table for quick access.
340 */
341int hc_init_transfer_lists(hc_t *instance)
342{
343 assert(instance);
344#define SETUP_TRANSFER_LIST(type, name) \
345do { \
346 int ret = transfer_list_init(&instance->transfers_##type, name); \
347 if (ret != EOK) { \
348 usb_log_error("Failed to setup %s transfer list: %s.\n", \
349 name, str_error(ret)); \
350 transfer_list_fini(&instance->transfers_bulk_full); \
351 transfer_list_fini(&instance->transfers_control_full); \
352 transfer_list_fini(&instance->transfers_control_slow); \
353 transfer_list_fini(&instance->transfers_interrupt); \
354 return ret; \
355 } \
356} while (0)
357
358 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
359 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
360 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
361 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
362#undef SETUP_TRANSFER_LIST
363 /* Connect lists into one schedule */
364 transfer_list_set_next(&instance->transfers_control_full,
365 &instance->transfers_bulk_full);
366 transfer_list_set_next(&instance->transfers_control_slow,
367 &instance->transfers_control_full);
368 transfer_list_set_next(&instance->transfers_interrupt,
369 &instance->transfers_control_slow);
370
371 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
372 * buggy on certain hw, enable at your own risk. */
373#ifdef FSBR
374 transfer_list_set_next(&instance->transfers_bulk_full,
375 &instance->transfers_control_full);
376#endif
377
378 /* Assign pointers to be used during scheduling */
379 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
380 &instance->transfers_interrupt;
381 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
382 &instance->transfers_interrupt;
383 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
384 &instance->transfers_control_full;
385 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
386 &instance->transfers_control_slow;
387 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
388 &instance->transfers_bulk_full;
389
390 return EOK;
391#undef CHECK_RET_CLEAR_RETURN
392}
393
394/** Schedule batch for execution.
395 *
396 * @param[in] instance UHCI structure to use.
397 * @param[in] batch Transfer batch to schedule.
398 * @return Error code
399 *
400 * Checks for bandwidth availability and appends the batch to the proper queue.
401 */
402int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
403{
404 assert(hcd);
405 hc_t *instance = hcd->private_data;
406 assert(instance);
407 assert(batch);
408 uhci_transfer_batch_t *uhci_batch = uhci_transfer_batch_get(batch);
409 if (!uhci_batch) {
410 usb_log_error("Failed to create UHCI transfer structures.\n");
411 return ENOMEM;
412 }
413
414 transfer_list_t *list =
415 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
416 assert(list);
417 transfer_list_add_batch(list, uhci_batch);
418
419 return EOK;
420}
421
422/** Polling function, emulates interrupts.
423 *
424 * @param[in] arg UHCI hc structure to use.
425 * @return EOK (should never return)
426 */
427int hc_interrupt_emulator(void* arg)
428{
429 usb_log_debug("Started interrupt emulator.\n");
430 hc_t *instance = arg;
431 assert(instance);
432
433 while (1) {
434 /* Read and clear status register */
435 uint16_t status = pio_read_16(&instance->registers->usbsts);
436 pio_write_16(&instance->registers->usbsts, status);
437 if (status != 0)
438 usb_log_debug2("UHCI status: %x.\n", status);
439 hc_interrupt(instance, status);
440 async_usleep(UHCI_INT_EMULATOR_TIMEOUT);
441 }
442 return EOK;
443}
444
445/** Debug function, checks consistency of memory structures.
446 *
447 * @param[in] arg UHCI structure to use.
448 * @return EOK (should never return)
449 */
450int hc_debug_checker(void *arg)
451{
452 hc_t *instance = arg;
453 assert(instance);
454
455#define QH(queue) \
456 instance->transfers_##queue.queue_head
457
458 while (1) {
459 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
460 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
461 const uint16_t intr =
462 pio_read_16(&instance->registers->usbintr);
463
464 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
465 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
466 cmd, sts, intr);
467 }
468
469 const uintptr_t frame_list =
470 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
471 if (frame_list != addr_to_phys(instance->frame_list)) {
472 usb_log_debug("Framelist address: %p vs. %p.\n",
473 (void *) frame_list,
474 (void *) addr_to_phys(instance->frame_list));
475 }
476
477 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
478
479 uintptr_t expected_pa = instance->frame_list[frnum]
480 & LINK_POINTER_ADDRESS_MASK;
481 uintptr_t real_pa = addr_to_phys(QH(interrupt));
482 if (expected_pa != real_pa) {
483 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
484 (void *) expected_pa, frnum, (void *) real_pa);
485 }
486
487 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
488 real_pa = addr_to_phys(QH(control_slow));
489 if (expected_pa != real_pa) {
490 usb_log_debug("Control Slow QH: %p vs. %p.\n",
491 (void *) expected_pa, (void *) real_pa);
492 }
493
494 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
495 real_pa = addr_to_phys(QH(control_full));
496 if (expected_pa != real_pa) {
497 usb_log_debug("Control Full QH: %p vs. %p.\n",
498 (void *) expected_pa, (void *) real_pa);
499 }
500
501 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
502 real_pa = addr_to_phys(QH(bulk_full));
503 if (expected_pa != real_pa ) {
504 usb_log_debug("Bulk QH: %p vs. %p.\n",
505 (void *) expected_pa, (void *) real_pa);
506 }
507 async_usleep(UHCI_DEBUGER_TIMEOUT);
508 }
509 return EOK;
510#undef QH
511}
512/**
513 * @}
514 */
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