source: mainline/uspace/drv/bus/usb/uhci/hc.c@ 6210a333

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 6210a333 was 6210a333, checked in by Jan Vesely <jano.vesely@…>, 12 years ago

uhci, ohci: Cleanup irq code generation.
  • Property mode set to 100644
File size: 15.7 KB
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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41
42#include "hc.h"
43#include "uhci_batch.h"
44
45#define UHCI_INTR_ALLOW_INTERRUPTS \
46 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
47#define UHCI_STATUS_USED_INTERRUPTS \
48 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
49
50static const irq_pio_range_t uhci_irq_pio_ranges[] = {
51 {
52 .base = 0,
53 .size = sizeof(uhci_regs_t)
54 }
55};
56
57static const irq_cmd_t uhci_irq_commands[] = {
58 {
59 .cmd = CMD_PIO_READ_16,
60 .dstarg = 1,
61 .addr = NULL
62 },
63 {
64 .cmd = CMD_AND,
65 .srcarg = 1,
66 .dstarg = 2,
67 .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS
68 },
69 {
70 .cmd = CMD_PREDICATE,
71 .srcarg = 2,
72 .value = 2
73 },
74 {
75 .cmd = CMD_PIO_WRITE_A_16,
76 .srcarg = 1,
77 .addr = NULL
78 },
79 {
80 .cmd = CMD_ACCEPT
81 }
82};
83
84static void hc_init_hw(const hc_t *instance);
85static int hc_init_mem_structures(hc_t *instance);
86static int hc_init_transfer_lists(hc_t *instance);
87
88static int hc_interrupt_emulator(void *arg);
89static int hc_debug_checker(void *arg);
90
91
92/** Generate IRQ code.
93 * @param[out] code IRQ code structure.
94 * @param[in] regs Device's register range.
95 *
96 * @return Error code.
97 */
98int hc_gen_irq_code(irq_code_t *code, addr_range_t *regs)
99{
100 assert(code);
101
102 if (RNGSZ(*regs) < sizeof(uhci_regs_t))
103 return EOVERFLOW;
104
105 code->ranges = malloc(sizeof(uhci_irq_pio_ranges));
106 if (code->ranges == NULL)
107 return ENOMEM;
108
109 code->cmds = malloc(sizeof(uhci_irq_commands));
110 if (code->cmds == NULL) {
111 free(code->ranges);
112 return ENOMEM;
113 }
114
115 code->rangecount = ARRAY_SIZE(uhci_irq_pio_ranges);
116 code->cmdcount = ARRAY_SIZE(uhci_irq_commands);
117
118 memcpy(code->ranges, uhci_irq_pio_ranges, sizeof(uhci_irq_pio_ranges));
119 code->ranges[0].base = RNGABS(*regs);
120
121 memcpy(code->cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
122 uhci_regs_t *registers = (uhci_regs_t *) RNGABSPTR(*regs);
123 code->cmds[0].addr = (void*)&registers->usbsts;
124 code->cmds[3].addr = (void*)&registers->usbsts;
125
126 return EOK;
127}
128
129/** Register interrupt handler.
130 *
131 * @param[in] device Host controller DDF device
132 * @param[in] regs Register range
133 * @param[in] irq Interrupt number
134 * @paran[in] handler Interrupt handler
135 *
136 * @return EOK on success or negative error code
137 */
138int hc_register_irq_handler(ddf_dev_t *device, addr_range_t *regs, int irq,
139 interrupt_handler_t handler)
140{
141 assert(device);
142
143 irq_code_t irq_code = { 0 };
144
145 int ret = hc_gen_irq_code(&irq_code, regs);
146 if (ret != EOK) {
147 usb_log_error("Failed to generate IRQ commands: %s.\n",
148 str_error(ret));
149 return ret;
150 }
151 //TODO we leak memory here
152
153 /* Register handler to avoid interrupt lockup */
154 ret = register_interrupt_handler(device, irq, handler, &irq_code);
155 if (ret != EOK) {
156 usb_log_error("Failed to register interrupt handler: %s.\n",
157 str_error(ret));
158 return ret;
159 }
160
161 return EOK;
162}
163
164/** Take action based on the interrupt cause.
165 *
166 * @param[in] instance UHCI structure to use.
167 * @param[in] status Value of the status register at the time of interrupt.
168 *
169 * Interrupt might indicate:
170 * - transaction completed, either by triggering IOC, SPD, or an error
171 * - some kind of device error
172 * - resume from suspend state (not implemented)
173 */
174void hc_interrupt(hc_t *instance, uint16_t status)
175{
176 assert(instance);
177 /* Lower 2 bits are transaction error and transaction complete */
178 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
179 LIST_INITIALIZE(done);
180 transfer_list_remove_finished(
181 &instance->transfers_interrupt, &done);
182 transfer_list_remove_finished(
183 &instance->transfers_control_slow, &done);
184 transfer_list_remove_finished(
185 &instance->transfers_control_full, &done);
186 transfer_list_remove_finished(
187 &instance->transfers_bulk_full, &done);
188
189 while (!list_empty(&done)) {
190 link_t *item = list_first(&done);
191 list_remove(item);
192 uhci_transfer_batch_t *batch =
193 uhci_transfer_batch_from_link(item);
194 uhci_transfer_batch_finish_dispose(batch);
195 }
196 }
197 /* Resume interrupts are not supported */
198 if (status & UHCI_STATUS_RESUME) {
199 usb_log_error("Resume interrupt!\n");
200 }
201
202 /* Bits 4 and 5 indicate hc error */
203 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
204 usb_log_error("UHCI hardware failure!.\n");
205 ++instance->hw_failures;
206 transfer_list_abort_all(&instance->transfers_interrupt);
207 transfer_list_abort_all(&instance->transfers_control_slow);
208 transfer_list_abort_all(&instance->transfers_control_full);
209 transfer_list_abort_all(&instance->transfers_bulk_full);
210
211 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
212 /* reinitialize hw, this triggers virtual disconnect*/
213 hc_init_hw(instance);
214 } else {
215 usb_log_fatal("Too many UHCI hardware failures!.\n");
216 hc_fini(instance);
217 }
218 }
219}
220
221/** Initialize UHCI hc driver structure
222 *
223 * @param[in] instance Memory place to initialize.
224 * @param[in] regs Range of device's I/O control registers.
225 * @param[in] interrupts True if hw interrupts should be used.
226 * @return Error code.
227 * @note Should be called only once on any structure.
228 *
229 * Initializes memory structures, starts up hw, and launches debugger and
230 * interrupt fibrils.
231 */
232int hc_init(hc_t *instance, addr_range_t *regs, bool interrupts)
233{
234 assert(instance);
235 assert(regs);
236 assert(regs->size >= sizeof(uhci_regs_t));
237
238 instance->hw_interrupts = interrupts;
239 instance->hw_failures = 0;
240
241 /* allow access to hc control registers */
242 uhci_regs_t *io;
243 int ret = pio_enable_range(regs, (void **) &io);
244 if (ret != EOK) {
245 usb_log_error("Failed to gain access to registers at %p: %s.\n",
246 io, str_error(ret));
247 return ret;
248 }
249 instance->registers = io;
250
251 usb_log_debug(
252 "Device registers at %p (%zuB) accessible.\n", io, regs->size);
253
254 ret = hc_init_mem_structures(instance);
255 if (ret != EOK) {
256 usb_log_error("Failed to init UHCI memory structures: %s.\n",
257 str_error(ret));
258 // TODO: we should disable pio here
259 return ret;
260 }
261
262 hc_init_hw(instance);
263 if (!interrupts) {
264 instance->interrupt_emulator =
265 fibril_create(hc_interrupt_emulator, instance);
266 fibril_add_ready(instance->interrupt_emulator);
267 }
268 (void)hc_debug_checker;
269
270 uhci_rh_init(&instance->rh, instance->registers->ports, "uhci");
271
272 return EOK;
273}
274
275/** Initialize UHCI hc hw resources.
276 *
277 * @param[in] instance UHCI structure to use.
278 * For magic values see UHCI Design Guide
279 */
280void hc_init_hw(const hc_t *instance)
281{
282 assert(instance);
283 uhci_regs_t *registers = instance->registers;
284
285 /* Reset everything, who knows what touched it before us */
286 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
287 async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
288 pio_write_16(&registers->usbcmd, 0);
289
290 /* Reset hc, all states and counters. Hope that hw is not broken */
291 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
292 do { async_usleep(10); }
293 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
294
295 /* Set frame to exactly 1ms */
296 pio_write_8(&registers->sofmod, 64);
297
298 /* Set frame list pointer */
299 const uint32_t pa = addr_to_phys(instance->frame_list);
300 pio_write_32(&registers->flbaseadd, pa);
301
302 if (instance->hw_interrupts) {
303 /* Enable all interrupts, but resume interrupt */
304 pio_write_16(&instance->registers->usbintr,
305 UHCI_INTR_ALLOW_INTERRUPTS);
306 }
307
308 const uint16_t cmd = pio_read_16(&registers->usbcmd);
309 if (cmd != 0)
310 usb_log_warning("Previous command value: %x.\n", cmd);
311
312 /* Start the hc with large(64B) packet FSBR */
313 pio_write_16(&registers->usbcmd,
314 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
315}
316
317/** Initialize UHCI hc memory structures.
318 *
319 * @param[in] instance UHCI structure to use.
320 * @return Error code
321 * @note Should be called only once on any structure.
322 *
323 * Structures:
324 * - transfer lists (queue heads need to be accessible by the hw)
325 * - frame list page (needs to be one UHCI hw accessible 4K page)
326 */
327int hc_init_mem_structures(hc_t *instance)
328{
329 assert(instance);
330
331 /* Init USB frame list page */
332 instance->frame_list = get_page();
333 if (!instance->frame_list) {
334 return ENOMEM;
335 }
336 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
337
338 /* Init transfer lists */
339 int ret = hc_init_transfer_lists(instance);
340 if (ret != EOK) {
341 usb_log_error("Failed to initialize transfer lists.\n");
342 return_page(instance->frame_list);
343 return ENOMEM;
344 }
345 usb_log_debug("Initialized transfer lists.\n");
346
347
348 /* Set all frames to point to the first queue head */
349 const uint32_t queue = LINK_POINTER_QH(
350 addr_to_phys(instance->transfers_interrupt.queue_head));
351
352 for (unsigned i = 0; i < UHCI_FRAME_LIST_COUNT; ++i) {
353 instance->frame_list[i] = queue;
354 }
355
356 return EOK;
357}
358
359/** Initialize UHCI hc transfer lists.
360 *
361 * @param[in] instance UHCI structure to use.
362 * @return Error code
363 * @note Should be called only once on any structure.
364 *
365 * Initializes transfer lists and sets them in one chain to support proper
366 * USB scheduling. Sets pointer table for quick access.
367 */
368int hc_init_transfer_lists(hc_t *instance)
369{
370 assert(instance);
371#define SETUP_TRANSFER_LIST(type, name) \
372do { \
373 int ret = transfer_list_init(&instance->transfers_##type, name); \
374 if (ret != EOK) { \
375 usb_log_error("Failed to setup %s transfer list: %s.\n", \
376 name, str_error(ret)); \
377 transfer_list_fini(&instance->transfers_bulk_full); \
378 transfer_list_fini(&instance->transfers_control_full); \
379 transfer_list_fini(&instance->transfers_control_slow); \
380 transfer_list_fini(&instance->transfers_interrupt); \
381 return ret; \
382 } \
383} while (0)
384
385 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
386 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
387 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
388 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
389#undef SETUP_TRANSFER_LIST
390 /* Connect lists into one schedule */
391 transfer_list_set_next(&instance->transfers_control_full,
392 &instance->transfers_bulk_full);
393 transfer_list_set_next(&instance->transfers_control_slow,
394 &instance->transfers_control_full);
395 transfer_list_set_next(&instance->transfers_interrupt,
396 &instance->transfers_control_slow);
397
398 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
399 * buggy on certain hw, enable at your own risk. */
400#ifdef FSBR
401 transfer_list_set_next(&instance->transfers_bulk_full,
402 &instance->transfers_control_full);
403#endif
404
405 /* Assign pointers to be used during scheduling */
406 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
407 &instance->transfers_interrupt;
408 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
409 &instance->transfers_interrupt;
410 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
411 &instance->transfers_control_full;
412 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
413 &instance->transfers_control_slow;
414 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
415 &instance->transfers_bulk_full;
416
417 return EOK;
418}
419
420/** Schedule batch for execution.
421 *
422 * @param[in] instance UHCI structure to use.
423 * @param[in] batch Transfer batch to schedule.
424 * @return Error code
425 *
426 * Checks for bandwidth availability and appends the batch to the proper queue.
427 */
428int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
429{
430 assert(hcd);
431 hc_t *instance = hcd->driver.data;
432 assert(instance);
433 assert(batch);
434
435 if (batch->ep->address == uhci_rh_get_address(&instance->rh))
436 return uhci_rh_schedule(&instance->rh, batch);
437
438 uhci_transfer_batch_t *uhci_batch = uhci_transfer_batch_get(batch);
439 if (!uhci_batch) {
440 usb_log_error("Failed to create UHCI transfer structures.\n");
441 return ENOMEM;
442 }
443
444 transfer_list_t *list =
445 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
446 assert(list);
447 transfer_list_add_batch(list, uhci_batch);
448
449 return EOK;
450}
451
452/** Polling function, emulates interrupts.
453 *
454 * @param[in] arg UHCI hc structure to use.
455 * @return EOK (should never return)
456 */
457int hc_interrupt_emulator(void* arg)
458{
459 usb_log_debug("Started interrupt emulator.\n");
460 hc_t *instance = arg;
461 assert(instance);
462
463 while (1) {
464 /* Read and clear status register */
465 uint16_t status = pio_read_16(&instance->registers->usbsts);
466 pio_write_16(&instance->registers->usbsts, status);
467 if (status != 0)
468 usb_log_debug2("UHCI status: %x.\n", status);
469 hc_interrupt(instance, status);
470 async_usleep(UHCI_INT_EMULATOR_TIMEOUT);
471 }
472 return EOK;
473}
474
475/** Debug function, checks consistency of memory structures.
476 *
477 * @param[in] arg UHCI structure to use.
478 * @return EOK (should never return)
479 */
480int hc_debug_checker(void *arg)
481{
482 hc_t *instance = arg;
483 assert(instance);
484
485#define QH(queue) \
486 instance->transfers_##queue.queue_head
487
488 while (1) {
489 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
490 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
491 const uint16_t intr =
492 pio_read_16(&instance->registers->usbintr);
493
494 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
495 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
496 cmd, sts, intr);
497 }
498
499 const uintptr_t frame_list =
500 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
501 if (frame_list != addr_to_phys(instance->frame_list)) {
502 usb_log_debug("Framelist address: %p vs. %p.\n",
503 (void *) frame_list,
504 (void *) addr_to_phys(instance->frame_list));
505 }
506
507 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
508
509 uintptr_t expected_pa = instance->frame_list[frnum]
510 & LINK_POINTER_ADDRESS_MASK;
511 uintptr_t real_pa = addr_to_phys(QH(interrupt));
512 if (expected_pa != real_pa) {
513 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
514 (void *) expected_pa, frnum, (void *) real_pa);
515 }
516
517 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
518 real_pa = addr_to_phys(QH(control_slow));
519 if (expected_pa != real_pa) {
520 usb_log_debug("Control Slow QH: %p vs. %p.\n",
521 (void *) expected_pa, (void *) real_pa);
522 }
523
524 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
525 real_pa = addr_to_phys(QH(control_full));
526 if (expected_pa != real_pa) {
527 usb_log_debug("Control Full QH: %p vs. %p.\n",
528 (void *) expected_pa, (void *) real_pa);
529 }
530
531 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
532 real_pa = addr_to_phys(QH(bulk_full));
533 if (expected_pa != real_pa ) {
534 usb_log_debug("Bulk QH: %p vs. %p.\n",
535 (void *) expected_pa, (void *) real_pa);
536 }
537 async_usleep(UHCI_DEBUGER_TIMEOUT);
538 }
539 return EOK;
540#undef QH
541}
542/**
543 * @}
544 */
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