[9351353] | 1 | /*
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| 2 | * Copyright (c) 2011 Jan Vesely
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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[17ceb72] | 28 | /** @addtogroup drvusbuhcihc
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[9351353] | 29 | * @{
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| 30 | */
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| 31 | /** @file
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[17ceb72] | 32 | * @brief UHCI Host controller driver routines
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[9351353] | 33 | */
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| 34 | #include <errno.h>
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| 35 | #include <str_error.h>
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| 36 | #include <adt/list.h>
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| 37 | #include <libarch/ddi.h>
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| 38 |
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| 39 | #include <usb/debug.h>
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| 40 | #include <usb/usb.h>
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| 41 |
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[c01cd32] | 42 | #include "hc.h"
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[07f49ae] | 43 | #include "uhci_batch.h"
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[9351353] | 44 |
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[8986412] | 45 | #define UHCI_INTR_ALLOW_INTERRUPTS \
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[af81980] | 46 | (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
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[8986412] | 47 | #define UHCI_STATUS_USED_INTERRUPTS \
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| 48 | (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
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[af81980] | 49 |
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[5fe0a697] | 50 |
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[dfe4955] | 51 | static const irq_cmd_t uhci_irq_commands[] =
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| 52 | {
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| 53 | { .cmd = CMD_PIO_READ_16, .dstarg = 1, .addr = NULL/*filled later*/},
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| 54 | { .cmd = CMD_BTEST, .srcarg = 1, .dstarg = 2,
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| 55 | .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS },
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| 56 | { .cmd = CMD_PREDICATE, .srcarg = 2, .value = 2 },
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| 57 | { .cmd = CMD_PIO_WRITE_A_16, .srcarg = 1, .addr = NULL/*filled later*/},
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| 58 | { .cmd = CMD_ACCEPT },
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| 59 | };
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[302a4b6] | 60 |
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[3afb758] | 61 | static void hc_init_hw(const hc_t *instance);
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[c01cd32] | 62 | static int hc_init_mem_structures(hc_t *instance);
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[3afb758] | 63 | static int hc_init_transfer_lists(hc_t *instance);
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| 64 | static int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch);
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[9351353] | 65 |
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[c01cd32] | 66 | static int hc_interrupt_emulator(void *arg);
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| 67 | static int hc_debug_checker(void *arg);
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[dfe4955] | 68 |
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| 69 | /*----------------------------------------------------------------------------*/
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| 70 | /** Get number of commands used in IRQ code.
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| 71 | * @return Number of commands.
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| 72 | */
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| 73 | size_t hc_irq_cmd_count(void)
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| 74 | {
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| 75 | return sizeof(uhci_irq_commands) / sizeof(irq_cmd_t);
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| 76 | }
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| 77 | /*----------------------------------------------------------------------------*/
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| 78 | /** Generate IRQ code commands.
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| 79 | * @param[out] cmds Place to store the commands.
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| 80 | * @param[in] cmd_size Size of the place (bytes).
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| 81 | * @param[in] regs Physical address of device's registers.
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| 82 | * @param[in] reg_size Size of the register area (bytes).
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| 83 | *
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| 84 | * @return Error code.
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| 85 | */
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| 86 | int hc_get_irq_commands(
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| 87 | irq_cmd_t cmds[], size_t cmd_size, uintptr_t regs, size_t reg_size)
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| 88 | {
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| 89 | if (cmd_size < sizeof(uhci_irq_commands)
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| 90 | || reg_size < sizeof(uhci_regs_t))
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| 91 | return EOVERFLOW;
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| 92 |
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| 93 | uhci_regs_t *registers = (uhci_regs_t*)regs;
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| 94 |
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| 95 | memcpy(cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
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| 96 |
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| 97 | cmds[0].addr = (void*)®isters->usbsts;
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| 98 | cmds[3].addr = (void*)®isters->usbsts;
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| 99 | return EOK;
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| 100 | }
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[9351353] | 101 | /*----------------------------------------------------------------------------*/
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[3afb758] | 102 | /** Take action based on the interrupt cause.
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| 103 | *
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| 104 | * @param[in] instance UHCI structure to use.
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| 105 | * @param[in] status Value of the status register at the time of interrupt.
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| 106 | *
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| 107 | * Interrupt might indicate:
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| 108 | * - transaction completed, either by triggering IOC, SPD, or an error
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| 109 | * - some kind of device error
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| 110 | * - resume from suspend state (not implemented)
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| 111 | */
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| 112 | void hc_interrupt(hc_t *instance, uint16_t status)
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| 113 | {
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| 114 | assert(instance);
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| 115 | /* Lower 2 bits are transaction error and transaction complete */
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| 116 | if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
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| 117 | LIST_INITIALIZE(done);
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| 118 | transfer_list_remove_finished(
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| 119 | &instance->transfers_interrupt, &done);
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| 120 | transfer_list_remove_finished(
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| 121 | &instance->transfers_control_slow, &done);
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| 122 | transfer_list_remove_finished(
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| 123 | &instance->transfers_control_full, &done);
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| 124 | transfer_list_remove_finished(
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| 125 | &instance->transfers_bulk_full, &done);
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| 126 |
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| 127 | while (!list_empty(&done)) {
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| 128 | link_t *item = list_first(&done);
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| 129 | list_remove(item);
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[b991d37] | 130 | uhci_transfer_batch_t *batch =
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| 131 | uhci_transfer_batch_from_link(item);
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[6bba41d] | 132 | uhci_transfer_batch_finish_dispose(batch);
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[3afb758] | 133 | }
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| 134 | }
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| 135 | /* Resume interrupts are not supported */
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| 136 | if (status & UHCI_STATUS_RESUME) {
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| 137 | usb_log_error("Resume interrupt!\n");
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| 138 | }
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| 139 |
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| 140 | /* Bits 4 and 5 indicate hc error */
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| 141 | if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
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| 142 | usb_log_error("UHCI hardware failure!.\n");
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| 143 | ++instance->hw_failures;
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| 144 | transfer_list_abort_all(&instance->transfers_interrupt);
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| 145 | transfer_list_abort_all(&instance->transfers_control_slow);
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| 146 | transfer_list_abort_all(&instance->transfers_control_full);
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| 147 | transfer_list_abort_all(&instance->transfers_bulk_full);
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| 148 |
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| 149 | if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
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| 150 | /* reinitialize hw, this triggers virtual disconnect*/
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| 151 | hc_init_hw(instance);
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| 152 | } else {
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| 153 | usb_log_fatal("Too many UHCI hardware failures!.\n");
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| 154 | hc_fini(instance);
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| 155 | }
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| 156 | }
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| 157 | }
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| 158 | /*----------------------------------------------------------------------------*/
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[02cacce] | 159 | /** Initialize UHCI hc driver structure
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[9351353] | 160 | *
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| 161 | * @param[in] instance Memory place to initialize.
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| 162 | * @param[in] regs Address of I/O control registers.
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[23f40280] | 163 | * @param[in] reg_size Size of I/O control registers.
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| 164 | * @param[in] interrupts True if hw interrupts should be used.
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[9351353] | 165 | * @return Error code.
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| 166 | * @note Should be called only once on any structure.
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[17ceb72] | 167 | *
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| 168 | * Initializes memory structures, starts up hw, and launches debugger and
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| 169 | * interrupt fibrils.
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[9351353] | 170 | */
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[d2bff2f] | 171 | int hc_init(hc_t *instance, void *regs, size_t reg_size, bool interrupts)
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[9351353] | 172 | {
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[dfe4955] | 173 | assert(reg_size >= sizeof(uhci_regs_t));
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[9351353] | 174 | int ret;
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| 175 |
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[ea993d18] | 176 | #define CHECK_RET_RETURN(ret, message...) \
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[9351353] | 177 | if (ret != EOK) { \
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| 178 | usb_log_error(message); \
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| 179 | return ret; \
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| 180 | } else (void) 0
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| 181 |
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[ff34e5a] | 182 | instance->hw_interrupts = interrupts;
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[fcc525d] | 183 | instance->hw_failures = 0;
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| 184 |
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[9351353] | 185 | /* allow access to hc control registers */
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[dfe4955] | 186 | uhci_regs_t *io;
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[e247d83] | 187 | ret = pio_enable(regs, reg_size, (void **)&io);
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[26858040] | 188 | CHECK_RET_RETURN(ret, "Failed to gain access to registers at %p: %s.\n",
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| 189 | io, str_error(ret));
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[9351353] | 190 | instance->registers = io;
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[26858040] | 191 | usb_log_debug(
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| 192 | "Device registers at %p (%zuB) accessible.\n", io, reg_size);
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[3afb758] | 193 |
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[7265558] | 194 | ret = hc_init_mem_structures(instance);
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| 195 | CHECK_RET_RETURN(ret,
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| 196 | "Failed to initialize UHCI memory structures: %s.\n",
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[3afb758] | 197 | str_error(ret));
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| 198 |
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[7265558] | 199 | #undef CHECK_RET_RETURN
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| 200 |
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[5e07cbc0] | 201 | hcd_init(&instance->generic, USB_SPEED_FULL,
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| 202 | BANDWIDTH_AVAILABLE_USB11, bandwidth_count_usb11);
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[7265558] | 203 |
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[5fe0a697] | 204 | instance->generic.private_data = instance;
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[3afb758] | 205 | instance->generic.schedule = hc_schedule;
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[1a02517] | 206 | instance->generic.ep_add_hook = NULL;
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[23b0fe8] | 207 |
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[c01cd32] | 208 | hc_init_hw(instance);
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[ff34e5a] | 209 | if (!interrupts) {
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[ea993d18] | 210 | instance->interrupt_emulator =
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[c01cd32] | 211 | fibril_create(hc_interrupt_emulator, instance);
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[ea993d18] | 212 | fibril_add_ready(instance->interrupt_emulator);
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[ff34e5a] | 213 | }
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[ea993d18] | 214 | (void)hc_debug_checker;
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[9351353] | 215 |
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| 216 | return EOK;
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| 217 | }
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| 218 | /*----------------------------------------------------------------------------*/
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[17ceb72] | 219 | /** Initialize UHCI hc hw resources.
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[9351353] | 220 | *
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| 221 | * @param[in] instance UHCI structure to use.
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[17ceb72] | 222 | * For magic values see UHCI Design Guide
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[9351353] | 223 | */
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[3afb758] | 224 | void hc_init_hw(const hc_t *instance)
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[9351353] | 225 | {
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| 226 | assert(instance);
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[dfe4955] | 227 | uhci_regs_t *registers = instance->registers;
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[9351353] | 228 |
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| 229 | /* Reset everything, who knows what touched it before us */
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| 230 | pio_write_16(®isters->usbcmd, UHCI_CMD_GLOBAL_RESET);
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[26858040] | 231 | async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
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[9351353] | 232 | pio_write_16(®isters->usbcmd, 0);
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| 233 |
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[26858040] | 234 | /* Reset hc, all states and counters. Hope that hw is not broken */
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[9351353] | 235 | pio_write_16(®isters->usbcmd, UHCI_CMD_HCRESET);
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| 236 | do { async_usleep(10); }
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| 237 | while ((pio_read_16(®isters->usbcmd) & UHCI_CMD_HCRESET) != 0);
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| 238 |
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[eb2a48a] | 239 | /* Set frame to exactly 1ms */
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| 240 | pio_write_8(®isters->sofmod, 64);
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| 241 |
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| 242 | /* Set frame list pointer */
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[9351353] | 243 | const uint32_t pa = addr_to_phys(instance->frame_list);
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| 244 | pio_write_32(®isters->flbaseadd, pa);
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| 245 |
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[ff34e5a] | 246 | if (instance->hw_interrupts) {
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| 247 | /* Enable all interrupts, but resume interrupt */
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| 248 | pio_write_16(&instance->registers->usbintr,
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[8986412] | 249 | UHCI_INTR_ALLOW_INTERRUPTS);
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[ff34e5a] | 250 | }
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[9351353] | 251 |
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[26858040] | 252 | const uint16_t cmd = pio_read_16(®isters->usbcmd);
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| 253 | if (cmd != 0)
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| 254 | usb_log_warning("Previous command value: %x.\n", cmd);
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[9351353] | 255 |
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| 256 | /* Start the hc with large(64B) packet FSBR */
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| 257 | pio_write_16(®isters->usbcmd,
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| 258 | UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
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| 259 | }
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| 260 | /*----------------------------------------------------------------------------*/
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[17ceb72] | 261 | /** Initialize UHCI hc memory structures.
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[9351353] | 262 | *
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| 263 | * @param[in] instance UHCI structure to use.
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| 264 | * @return Error code
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| 265 | * @note Should be called only once on any structure.
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[17ceb72] | 266 | *
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| 267 | * Structures:
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| 268 | * - transfer lists (queue heads need to be accessible by the hw)
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| 269 | * - frame list page (needs to be one UHCI hw accessible 4K page)
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[9351353] | 270 | */
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[c01cd32] | 271 | int hc_init_mem_structures(hc_t *instance)
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[9351353] | 272 | {
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| 273 | assert(instance);
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| 274 |
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[3afb758] | 275 | /* Init USB frame list page */
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[9351353] | 276 | instance->frame_list = get_page();
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[26858040] | 277 | if (!instance->frame_list) {
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| 278 | return ENOMEM;
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| 279 | }
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[001b152] | 280 | usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
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[9351353] | 281 |
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[3afb758] | 282 | /* Init transfer lists */
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| 283 | int ret = hc_init_transfer_lists(instance);
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| 284 | if (ret != EOK) {
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| 285 | usb_log_error("Failed to initialize transfer lists.\n");
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| 286 | return_page(instance->frame_list);
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| 287 | return ENOMEM;
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| 288 | }
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| 289 | usb_log_debug("Initialized transfer lists.\n");
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| 290 |
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| 291 |
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[9351353] | 292 | /* Set all frames to point to the first queue head */
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[302a4b6] | 293 | const uint32_t queue = LINK_POINTER_QH(
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| 294 | addr_to_phys(instance->transfers_interrupt.queue_head));
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[75f9dcd] | 295 |
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| 296 | for (unsigned i = 0; i < UHCI_FRAME_LIST_COUNT; ++i) {
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[9351353] | 297 | instance->frame_list[i] = queue;
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| 298 | }
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| 299 |
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| 300 | return EOK;
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| 301 | }
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| 302 | /*----------------------------------------------------------------------------*/
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[17ceb72] | 303 | /** Initialize UHCI hc transfer lists.
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[9351353] | 304 | *
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| 305 | * @param[in] instance UHCI structure to use.
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| 306 | * @return Error code
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| 307 | * @note Should be called only once on any structure.
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[17ceb72] | 308 | *
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| 309 | * Initializes transfer lists and sets them in one chain to support proper
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| 310 | * USB scheduling. Sets pointer table for quick access.
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[9351353] | 311 | */
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[c01cd32] | 312 | int hc_init_transfer_lists(hc_t *instance)
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[9351353] | 313 | {
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| 314 | assert(instance);
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[27205841] | 315 | #define SETUP_TRANSFER_LIST(type, name) \
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| 316 | do { \
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| 317 | int ret = transfer_list_init(&instance->transfers_##type, name); \
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[9351353] | 318 | if (ret != EOK) { \
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[26858040] | 319 | usb_log_error("Failed to setup %s transfer list: %s.\n", \
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| 320 | name, str_error(ret)); \
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[9351353] | 321 | transfer_list_fini(&instance->transfers_bulk_full); \
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| 322 | transfer_list_fini(&instance->transfers_control_full); \
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| 323 | transfer_list_fini(&instance->transfers_control_slow); \
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| 324 | transfer_list_fini(&instance->transfers_interrupt); \
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| 325 | return ret; \
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[27205841] | 326 | } \
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| 327 | } while (0)
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| 328 |
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| 329 | SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
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| 330 | SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
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| 331 | SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
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| 332 | SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
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| 333 | #undef SETUP_TRANSFER_LIST
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| 334 | /* Connect lists into one schedule */
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[9351353] | 335 | transfer_list_set_next(&instance->transfers_control_full,
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| 336 | &instance->transfers_bulk_full);
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| 337 | transfer_list_set_next(&instance->transfers_control_slow,
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| 338 | &instance->transfers_control_full);
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| 339 | transfer_list_set_next(&instance->transfers_interrupt,
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| 340 | &instance->transfers_control_slow);
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| 341 |
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[e247d83] | 342 | /*FSBR, This feature is not needed (adds no benefit) and is supposedly
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| 343 | * buggy on certain hw, enable at your own risk. */
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[9351353] | 344 | #ifdef FSBR
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| 345 | transfer_list_set_next(&instance->transfers_bulk_full,
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[302a4b6] | 346 | &instance->transfers_control_full);
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[9351353] | 347 | #endif
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| 348 |
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| 349 | /* Assign pointers to be used during scheduling */
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| 350 | instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
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| 351 | &instance->transfers_interrupt;
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| 352 | instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
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| 353 | &instance->transfers_interrupt;
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| 354 | instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
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| 355 | &instance->transfers_control_full;
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| 356 | instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
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| 357 | &instance->transfers_control_slow;
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| 358 | instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
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| 359 | &instance->transfers_bulk_full;
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| 360 |
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| 361 | return EOK;
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| 362 | #undef CHECK_RET_CLEAR_RETURN
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| 363 | }
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| 364 | /*----------------------------------------------------------------------------*/
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[17ceb72] | 365 | /** Schedule batch for execution.
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[9351353] | 366 | *
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| 367 | * @param[in] instance UHCI structure to use.
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| 368 | * @param[in] batch Transfer batch to schedule.
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| 369 | * @return Error code
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[17ceb72] | 370 | *
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| 371 | * Checks for bandwidth availability and appends the batch to the proper queue.
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[9351353] | 372 | */
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[3afb758] | 373 | int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
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[9351353] | 374 | {
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[3afb758] | 375 | assert(hcd);
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| 376 | hc_t *instance = hcd->private_data;
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[9351353] | 377 | assert(instance);
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| 378 | assert(batch);
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[b991d37] | 379 | uhci_transfer_batch_t *uhci_batch = uhci_transfer_batch_get(batch);
|
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| 380 | if (!uhci_batch) {
|
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| 381 | usb_log_error("Failed to create UHCI transfer structures.\n");
|
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| 382 | return ENOMEM;
|
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[23b0fe8] | 383 | }
|
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[9351353] | 384 |
|
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| 385 | transfer_list_t *list =
|
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[d017cea] | 386 | instance->transfers[batch->ep->speed][batch->ep->transfer_type];
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[9351353] | 387 | assert(list);
|
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[b991d37] | 388 | transfer_list_add_batch(list, uhci_batch);
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[9351353] | 389 |
|
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| 390 | return EOK;
|
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| 391 | }
|
---|
| 392 | /*----------------------------------------------------------------------------*/
|
---|
| 393 | /** Polling function, emulates interrupts.
|
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| 394 | *
|
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[17ceb72] | 395 | * @param[in] arg UHCI hc structure to use.
|
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| 396 | * @return EOK (should never return)
|
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[9351353] | 397 | */
|
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[c01cd32] | 398 | int hc_interrupt_emulator(void* arg)
|
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[9351353] | 399 | {
|
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| 400 | usb_log_debug("Started interrupt emulator.\n");
|
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[6f122df] | 401 | hc_t *instance = arg;
|
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[9351353] | 402 | assert(instance);
|
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| 403 |
|
---|
| 404 | while (1) {
|
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[6f122df] | 405 | /* Read and clear status register */
|
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[9351353] | 406 | uint16_t status = pio_read_16(&instance->registers->usbsts);
|
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[27205841] | 407 | pio_write_16(&instance->registers->usbsts, status);
|
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[9351353] | 408 | if (status != 0)
|
---|
| 409 | usb_log_debug2("UHCI status: %x.\n", status);
|
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[c01cd32] | 410 | hc_interrupt(instance, status);
|
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[27205841] | 411 | async_usleep(UHCI_INT_EMULATOR_TIMEOUT);
|
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[9351353] | 412 | }
|
---|
| 413 | return EOK;
|
---|
| 414 | }
|
---|
[3afb758] | 415 | /*----------------------------------------------------------------------------*/
|
---|
[9351353] | 416 | /** Debug function, checks consistency of memory structures.
|
---|
| 417 | *
|
---|
| 418 | * @param[in] arg UHCI structure to use.
|
---|
[17ceb72] | 419 | * @return EOK (should never return)
|
---|
[9351353] | 420 | */
|
---|
[c01cd32] | 421 | int hc_debug_checker(void *arg)
|
---|
[9351353] | 422 | {
|
---|
[6f122df] | 423 | hc_t *instance = arg;
|
---|
[9351353] | 424 | assert(instance);
|
---|
| 425 |
|
---|
| 426 | #define QH(queue) \
|
---|
| 427 | instance->transfers_##queue.queue_head
|
---|
| 428 |
|
---|
| 429 | while (1) {
|
---|
| 430 | const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
|
---|
| 431 | const uint16_t sts = pio_read_16(&instance->registers->usbsts);
|
---|
| 432 | const uint16_t intr =
|
---|
| 433 | pio_read_16(&instance->registers->usbintr);
|
---|
| 434 |
|
---|
| 435 | if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
|
---|
| 436 | usb_log_debug2("Command: %X Status: %X Intr: %x\n",
|
---|
| 437 | cmd, sts, intr);
|
---|
| 438 | }
|
---|
| 439 |
|
---|
[e247d83] | 440 | const uintptr_t frame_list =
|
---|
[9351353] | 441 | pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
|
---|
| 442 | if (frame_list != addr_to_phys(instance->frame_list)) {
|
---|
| 443 | usb_log_debug("Framelist address: %p vs. %p.\n",
|
---|
[4125b7d] | 444 | (void *) frame_list,
|
---|
| 445 | (void *) addr_to_phys(instance->frame_list));
|
---|
[9351353] | 446 | }
|
---|
| 447 |
|
---|
| 448 | int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
|
---|
| 449 |
|
---|
| 450 | uintptr_t expected_pa = instance->frame_list[frnum]
|
---|
| 451 | & LINK_POINTER_ADDRESS_MASK;
|
---|
| 452 | uintptr_t real_pa = addr_to_phys(QH(interrupt));
|
---|
| 453 | if (expected_pa != real_pa) {
|
---|
[4125b7d] | 454 | usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
|
---|
| 455 | (void *) expected_pa, frnum, (void *) real_pa);
|
---|
[9351353] | 456 | }
|
---|
| 457 |
|
---|
| 458 | expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
|
---|
| 459 | real_pa = addr_to_phys(QH(control_slow));
|
---|
| 460 | if (expected_pa != real_pa) {
|
---|
| 461 | usb_log_debug("Control Slow QH: %p vs. %p.\n",
|
---|
[4125b7d] | 462 | (void *) expected_pa, (void *) real_pa);
|
---|
[9351353] | 463 | }
|
---|
| 464 |
|
---|
| 465 | expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
|
---|
| 466 | real_pa = addr_to_phys(QH(control_full));
|
---|
| 467 | if (expected_pa != real_pa) {
|
---|
| 468 | usb_log_debug("Control Full QH: %p vs. %p.\n",
|
---|
[4125b7d] | 469 | (void *) expected_pa, (void *) real_pa);
|
---|
[9351353] | 470 | }
|
---|
| 471 |
|
---|
| 472 | expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
|
---|
| 473 | real_pa = addr_to_phys(QH(bulk_full));
|
---|
| 474 | if (expected_pa != real_pa ) {
|
---|
| 475 | usb_log_debug("Bulk QH: %p vs. %p.\n",
|
---|
[4125b7d] | 476 | (void *) expected_pa, (void *) real_pa);
|
---|
[9351353] | 477 | }
|
---|
| 478 | async_usleep(UHCI_DEBUGER_TIMEOUT);
|
---|
| 479 | }
|
---|
| 480 | return EOK;
|
---|
| 481 | #undef QH
|
---|
| 482 | }
|
---|
| 483 | /**
|
---|
| 484 | * @}
|
---|
| 485 | */
|
---|