source: mainline/uspace/drv/bus/usb/uhci/hc.c@ ad91b806

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ad91b806 was 6bba41d, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

uhci: Add and use uhci_batch_abort. Rename uhci_batch_call_dispose ⇒ uhci_batch finish_dispose

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[9351353]1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
[17ceb72]28/** @addtogroup drvusbuhcihc
[9351353]29 * @{
30 */
31/** @file
[17ceb72]32 * @brief UHCI Host controller driver routines
[9351353]33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41
[c01cd32]42#include "hc.h"
[07f49ae]43#include "uhci_batch.h"
[9351353]44
[8986412]45#define UHCI_INTR_ALLOW_INTERRUPTS \
[af81980]46 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
[8986412]47#define UHCI_STATUS_USED_INTERRUPTS \
48 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
[af81980]49
[5fe0a697]50
[dfe4955]51static const irq_cmd_t uhci_irq_commands[] =
52{
53 { .cmd = CMD_PIO_READ_16, .dstarg = 1, .addr = NULL/*filled later*/},
54 { .cmd = CMD_BTEST, .srcarg = 1, .dstarg = 2,
55 .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS },
56 { .cmd = CMD_PREDICATE, .srcarg = 2, .value = 2 },
57 { .cmd = CMD_PIO_WRITE_A_16, .srcarg = 1, .addr = NULL/*filled later*/},
58 { .cmd = CMD_ACCEPT },
59};
[302a4b6]60
[3afb758]61static void hc_init_hw(const hc_t *instance);
[c01cd32]62static int hc_init_mem_structures(hc_t *instance);
[3afb758]63static int hc_init_transfer_lists(hc_t *instance);
64static int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch);
[9351353]65
[c01cd32]66static int hc_interrupt_emulator(void *arg);
67static int hc_debug_checker(void *arg);
[dfe4955]68
69/*----------------------------------------------------------------------------*/
70/** Get number of commands used in IRQ code.
71 * @return Number of commands.
72 */
73size_t hc_irq_cmd_count(void)
74{
75 return sizeof(uhci_irq_commands) / sizeof(irq_cmd_t);
76}
77/*----------------------------------------------------------------------------*/
78/** Generate IRQ code commands.
79 * @param[out] cmds Place to store the commands.
80 * @param[in] cmd_size Size of the place (bytes).
81 * @param[in] regs Physical address of device's registers.
82 * @param[in] reg_size Size of the register area (bytes).
83 *
84 * @return Error code.
85 */
86int hc_get_irq_commands(
87 irq_cmd_t cmds[], size_t cmd_size, uintptr_t regs, size_t reg_size)
88{
89 if (cmd_size < sizeof(uhci_irq_commands)
90 || reg_size < sizeof(uhci_regs_t))
91 return EOVERFLOW;
92
93 uhci_regs_t *registers = (uhci_regs_t*)regs;
94
95 memcpy(cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
96
97 cmds[0].addr = (void*)&registers->usbsts;
98 cmds[3].addr = (void*)&registers->usbsts;
99 return EOK;
100}
[9351353]101/*----------------------------------------------------------------------------*/
[3afb758]102/** Take action based on the interrupt cause.
103 *
104 * @param[in] instance UHCI structure to use.
105 * @param[in] status Value of the status register at the time of interrupt.
106 *
107 * Interrupt might indicate:
108 * - transaction completed, either by triggering IOC, SPD, or an error
109 * - some kind of device error
110 * - resume from suspend state (not implemented)
111 */
112void hc_interrupt(hc_t *instance, uint16_t status)
113{
114 assert(instance);
115 /* Lower 2 bits are transaction error and transaction complete */
116 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
117 LIST_INITIALIZE(done);
118 transfer_list_remove_finished(
119 &instance->transfers_interrupt, &done);
120 transfer_list_remove_finished(
121 &instance->transfers_control_slow, &done);
122 transfer_list_remove_finished(
123 &instance->transfers_control_full, &done);
124 transfer_list_remove_finished(
125 &instance->transfers_bulk_full, &done);
126
127 while (!list_empty(&done)) {
128 link_t *item = list_first(&done);
129 list_remove(item);
[b991d37]130 uhci_transfer_batch_t *batch =
131 uhci_transfer_batch_from_link(item);
[6bba41d]132 uhci_transfer_batch_finish_dispose(batch);
[3afb758]133 }
134 }
135 /* Resume interrupts are not supported */
136 if (status & UHCI_STATUS_RESUME) {
137 usb_log_error("Resume interrupt!\n");
138 }
139
140 /* Bits 4 and 5 indicate hc error */
141 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
142 usb_log_error("UHCI hardware failure!.\n");
143 ++instance->hw_failures;
144 transfer_list_abort_all(&instance->transfers_interrupt);
145 transfer_list_abort_all(&instance->transfers_control_slow);
146 transfer_list_abort_all(&instance->transfers_control_full);
147 transfer_list_abort_all(&instance->transfers_bulk_full);
148
149 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
150 /* reinitialize hw, this triggers virtual disconnect*/
151 hc_init_hw(instance);
152 } else {
153 usb_log_fatal("Too many UHCI hardware failures!.\n");
154 hc_fini(instance);
155 }
156 }
157}
158/*----------------------------------------------------------------------------*/
[02cacce]159/** Initialize UHCI hc driver structure
[9351353]160 *
161 * @param[in] instance Memory place to initialize.
162 * @param[in] regs Address of I/O control registers.
[23f40280]163 * @param[in] reg_size Size of I/O control registers.
164 * @param[in] interrupts True if hw interrupts should be used.
[9351353]165 * @return Error code.
166 * @note Should be called only once on any structure.
[17ceb72]167 *
168 * Initializes memory structures, starts up hw, and launches debugger and
169 * interrupt fibrils.
[9351353]170 */
[d2bff2f]171int hc_init(hc_t *instance, void *regs, size_t reg_size, bool interrupts)
[9351353]172{
[dfe4955]173 assert(reg_size >= sizeof(uhci_regs_t));
[9351353]174 int ret;
175
[ea993d18]176#define CHECK_RET_RETURN(ret, message...) \
[9351353]177 if (ret != EOK) { \
178 usb_log_error(message); \
179 return ret; \
180 } else (void) 0
181
[ff34e5a]182 instance->hw_interrupts = interrupts;
[fcc525d]183 instance->hw_failures = 0;
184
[9351353]185 /* allow access to hc control registers */
[dfe4955]186 uhci_regs_t *io;
[e247d83]187 ret = pio_enable(regs, reg_size, (void **)&io);
[26858040]188 CHECK_RET_RETURN(ret, "Failed to gain access to registers at %p: %s.\n",
189 io, str_error(ret));
[9351353]190 instance->registers = io;
[26858040]191 usb_log_debug(
192 "Device registers at %p (%zuB) accessible.\n", io, reg_size);
[3afb758]193
[7265558]194 ret = hc_init_mem_structures(instance);
195 CHECK_RET_RETURN(ret,
196 "Failed to initialize UHCI memory structures: %s.\n",
[3afb758]197 str_error(ret));
198
[7265558]199#undef CHECK_RET_RETURN
200
[5e07cbc0]201 hcd_init(&instance->generic, USB_SPEED_FULL,
202 BANDWIDTH_AVAILABLE_USB11, bandwidth_count_usb11);
[7265558]203
[5fe0a697]204 instance->generic.private_data = instance;
[3afb758]205 instance->generic.schedule = hc_schedule;
[1a02517]206 instance->generic.ep_add_hook = NULL;
[23b0fe8]207
[c01cd32]208 hc_init_hw(instance);
[ff34e5a]209 if (!interrupts) {
[ea993d18]210 instance->interrupt_emulator =
[c01cd32]211 fibril_create(hc_interrupt_emulator, instance);
[ea993d18]212 fibril_add_ready(instance->interrupt_emulator);
[ff34e5a]213 }
[ea993d18]214 (void)hc_debug_checker;
[9351353]215
216 return EOK;
217}
218/*----------------------------------------------------------------------------*/
[17ceb72]219/** Initialize UHCI hc hw resources.
[9351353]220 *
221 * @param[in] instance UHCI structure to use.
[17ceb72]222 * For magic values see UHCI Design Guide
[9351353]223 */
[3afb758]224void hc_init_hw(const hc_t *instance)
[9351353]225{
226 assert(instance);
[dfe4955]227 uhci_regs_t *registers = instance->registers;
[9351353]228
229 /* Reset everything, who knows what touched it before us */
230 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
[26858040]231 async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
[9351353]232 pio_write_16(&registers->usbcmd, 0);
233
[26858040]234 /* Reset hc, all states and counters. Hope that hw is not broken */
[9351353]235 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
236 do { async_usleep(10); }
237 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
238
[eb2a48a]239 /* Set frame to exactly 1ms */
240 pio_write_8(&registers->sofmod, 64);
241
242 /* Set frame list pointer */
[9351353]243 const uint32_t pa = addr_to_phys(instance->frame_list);
244 pio_write_32(&registers->flbaseadd, pa);
245
[ff34e5a]246 if (instance->hw_interrupts) {
247 /* Enable all interrupts, but resume interrupt */
248 pio_write_16(&instance->registers->usbintr,
[8986412]249 UHCI_INTR_ALLOW_INTERRUPTS);
[ff34e5a]250 }
[9351353]251
[26858040]252 const uint16_t cmd = pio_read_16(&registers->usbcmd);
253 if (cmd != 0)
254 usb_log_warning("Previous command value: %x.\n", cmd);
[9351353]255
256 /* Start the hc with large(64B) packet FSBR */
257 pio_write_16(&registers->usbcmd,
258 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
259}
260/*----------------------------------------------------------------------------*/
[17ceb72]261/** Initialize UHCI hc memory structures.
[9351353]262 *
263 * @param[in] instance UHCI structure to use.
264 * @return Error code
265 * @note Should be called only once on any structure.
[17ceb72]266 *
267 * Structures:
268 * - transfer lists (queue heads need to be accessible by the hw)
269 * - frame list page (needs to be one UHCI hw accessible 4K page)
[9351353]270 */
[c01cd32]271int hc_init_mem_structures(hc_t *instance)
[9351353]272{
273 assert(instance);
274
[3afb758]275 /* Init USB frame list page */
[9351353]276 instance->frame_list = get_page();
[26858040]277 if (!instance->frame_list) {
278 return ENOMEM;
279 }
[001b152]280 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
[9351353]281
[3afb758]282 /* Init transfer lists */
283 int ret = hc_init_transfer_lists(instance);
284 if (ret != EOK) {
285 usb_log_error("Failed to initialize transfer lists.\n");
286 return_page(instance->frame_list);
287 return ENOMEM;
288 }
289 usb_log_debug("Initialized transfer lists.\n");
290
291
[9351353]292 /* Set all frames to point to the first queue head */
[302a4b6]293 const uint32_t queue = LINK_POINTER_QH(
294 addr_to_phys(instance->transfers_interrupt.queue_head));
[75f9dcd]295
296 for (unsigned i = 0; i < UHCI_FRAME_LIST_COUNT; ++i) {
[9351353]297 instance->frame_list[i] = queue;
298 }
299
300 return EOK;
301}
302/*----------------------------------------------------------------------------*/
[17ceb72]303/** Initialize UHCI hc transfer lists.
[9351353]304 *
305 * @param[in] instance UHCI structure to use.
306 * @return Error code
307 * @note Should be called only once on any structure.
[17ceb72]308 *
309 * Initializes transfer lists and sets them in one chain to support proper
310 * USB scheduling. Sets pointer table for quick access.
[9351353]311 */
[c01cd32]312int hc_init_transfer_lists(hc_t *instance)
[9351353]313{
314 assert(instance);
[27205841]315#define SETUP_TRANSFER_LIST(type, name) \
316do { \
317 int ret = transfer_list_init(&instance->transfers_##type, name); \
[9351353]318 if (ret != EOK) { \
[26858040]319 usb_log_error("Failed to setup %s transfer list: %s.\n", \
320 name, str_error(ret)); \
[9351353]321 transfer_list_fini(&instance->transfers_bulk_full); \
322 transfer_list_fini(&instance->transfers_control_full); \
323 transfer_list_fini(&instance->transfers_control_slow); \
324 transfer_list_fini(&instance->transfers_interrupt); \
325 return ret; \
[27205841]326 } \
327} while (0)
328
329 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
330 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
331 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
332 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
333#undef SETUP_TRANSFER_LIST
334 /* Connect lists into one schedule */
[9351353]335 transfer_list_set_next(&instance->transfers_control_full,
336 &instance->transfers_bulk_full);
337 transfer_list_set_next(&instance->transfers_control_slow,
338 &instance->transfers_control_full);
339 transfer_list_set_next(&instance->transfers_interrupt,
340 &instance->transfers_control_slow);
341
[e247d83]342 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
343 * buggy on certain hw, enable at your own risk. */
[9351353]344#ifdef FSBR
345 transfer_list_set_next(&instance->transfers_bulk_full,
[302a4b6]346 &instance->transfers_control_full);
[9351353]347#endif
348
349 /* Assign pointers to be used during scheduling */
350 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
351 &instance->transfers_interrupt;
352 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
353 &instance->transfers_interrupt;
354 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
355 &instance->transfers_control_full;
356 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
357 &instance->transfers_control_slow;
358 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
359 &instance->transfers_bulk_full;
360
361 return EOK;
362#undef CHECK_RET_CLEAR_RETURN
363}
364/*----------------------------------------------------------------------------*/
[17ceb72]365/** Schedule batch for execution.
[9351353]366 *
367 * @param[in] instance UHCI structure to use.
368 * @param[in] batch Transfer batch to schedule.
369 * @return Error code
[17ceb72]370 *
371 * Checks for bandwidth availability and appends the batch to the proper queue.
[9351353]372 */
[3afb758]373int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
[9351353]374{
[3afb758]375 assert(hcd);
376 hc_t *instance = hcd->private_data;
[9351353]377 assert(instance);
378 assert(batch);
[b991d37]379 uhci_transfer_batch_t *uhci_batch = uhci_transfer_batch_get(batch);
380 if (!uhci_batch) {
381 usb_log_error("Failed to create UHCI transfer structures.\n");
382 return ENOMEM;
[23b0fe8]383 }
[9351353]384
385 transfer_list_t *list =
[d017cea]386 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
[9351353]387 assert(list);
[b991d37]388 transfer_list_add_batch(list, uhci_batch);
[9351353]389
390 return EOK;
391}
392/*----------------------------------------------------------------------------*/
393/** Polling function, emulates interrupts.
394 *
[17ceb72]395 * @param[in] arg UHCI hc structure to use.
396 * @return EOK (should never return)
[9351353]397 */
[c01cd32]398int hc_interrupt_emulator(void* arg)
[9351353]399{
400 usb_log_debug("Started interrupt emulator.\n");
[6f122df]401 hc_t *instance = arg;
[9351353]402 assert(instance);
403
404 while (1) {
[6f122df]405 /* Read and clear status register */
[9351353]406 uint16_t status = pio_read_16(&instance->registers->usbsts);
[27205841]407 pio_write_16(&instance->registers->usbsts, status);
[9351353]408 if (status != 0)
409 usb_log_debug2("UHCI status: %x.\n", status);
[c01cd32]410 hc_interrupt(instance, status);
[27205841]411 async_usleep(UHCI_INT_EMULATOR_TIMEOUT);
[9351353]412 }
413 return EOK;
414}
[3afb758]415/*----------------------------------------------------------------------------*/
[9351353]416/** Debug function, checks consistency of memory structures.
417 *
418 * @param[in] arg UHCI structure to use.
[17ceb72]419 * @return EOK (should never return)
[9351353]420 */
[c01cd32]421int hc_debug_checker(void *arg)
[9351353]422{
[6f122df]423 hc_t *instance = arg;
[9351353]424 assert(instance);
425
426#define QH(queue) \
427 instance->transfers_##queue.queue_head
428
429 while (1) {
430 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
431 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
432 const uint16_t intr =
433 pio_read_16(&instance->registers->usbintr);
434
435 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
436 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
437 cmd, sts, intr);
438 }
439
[e247d83]440 const uintptr_t frame_list =
[9351353]441 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
442 if (frame_list != addr_to_phys(instance->frame_list)) {
443 usb_log_debug("Framelist address: %p vs. %p.\n",
[4125b7d]444 (void *) frame_list,
445 (void *) addr_to_phys(instance->frame_list));
[9351353]446 }
447
448 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
449
450 uintptr_t expected_pa = instance->frame_list[frnum]
451 & LINK_POINTER_ADDRESS_MASK;
452 uintptr_t real_pa = addr_to_phys(QH(interrupt));
453 if (expected_pa != real_pa) {
[4125b7d]454 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
455 (void *) expected_pa, frnum, (void *) real_pa);
[9351353]456 }
457
458 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
459 real_pa = addr_to_phys(QH(control_slow));
460 if (expected_pa != real_pa) {
461 usb_log_debug("Control Slow QH: %p vs. %p.\n",
[4125b7d]462 (void *) expected_pa, (void *) real_pa);
[9351353]463 }
464
465 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
466 real_pa = addr_to_phys(QH(control_full));
467 if (expected_pa != real_pa) {
468 usb_log_debug("Control Full QH: %p vs. %p.\n",
[4125b7d]469 (void *) expected_pa, (void *) real_pa);
[9351353]470 }
471
472 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
473 real_pa = addr_to_phys(QH(bulk_full));
474 if (expected_pa != real_pa ) {
475 usb_log_debug("Bulk QH: %p vs. %p.\n",
[4125b7d]476 (void *) expected_pa, (void *) real_pa);
[9351353]477 }
478 async_usleep(UHCI_DEBUGER_TIMEOUT);
479 }
480 return EOK;
481#undef QH
482}
483/**
484 * @}
485 */
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