source: mainline/uspace/drv/bus/usb/uhci/hc.c@ 5f57929

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 5f57929 was b991d37, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

uhci: use uhci sepcific structure instead of generic library

revert the way uhci_transfer_batch_t and usb_transfer_batch_t are included,
don't use usb_transfer_batch_t:

-private data and data dtor
-next_step pointer
-buffer_data pointer

  • Property mode set to 100644
File size: 15.8 KB
RevLine 
[9351353]1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
[17ceb72]28/** @addtogroup drvusbuhcihc
[9351353]29 * @{
30 */
31/** @file
[17ceb72]32 * @brief UHCI Host controller driver routines
[9351353]33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41
[c01cd32]42#include "hc.h"
[07f49ae]43#include "uhci_batch.h"
[9351353]44
[8986412]45#define UHCI_INTR_ALLOW_INTERRUPTS \
[af81980]46 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
[8986412]47#define UHCI_STATUS_USED_INTERRUPTS \
48 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
[af81980]49
[5fe0a697]50
[dfe4955]51static const irq_cmd_t uhci_irq_commands[] =
52{
53 { .cmd = CMD_PIO_READ_16, .dstarg = 1, .addr = NULL/*filled later*/},
54 { .cmd = CMD_BTEST, .srcarg = 1, .dstarg = 2,
55 .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS },
56 { .cmd = CMD_PREDICATE, .srcarg = 2, .value = 2 },
57 { .cmd = CMD_PIO_WRITE_A_16, .srcarg = 1, .addr = NULL/*filled later*/},
58 { .cmd = CMD_ACCEPT },
59};
[302a4b6]60
[3afb758]61static void hc_init_hw(const hc_t *instance);
[c01cd32]62static int hc_init_mem_structures(hc_t *instance);
[3afb758]63static int hc_init_transfer_lists(hc_t *instance);
64static int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch);
[9351353]65
[c01cd32]66static int hc_interrupt_emulator(void *arg);
67static int hc_debug_checker(void *arg);
[dfe4955]68
69/*----------------------------------------------------------------------------*/
70/** Get number of commands used in IRQ code.
71 * @return Number of commands.
72 */
73size_t hc_irq_cmd_count(void)
74{
75 return sizeof(uhci_irq_commands) / sizeof(irq_cmd_t);
76}
77/*----------------------------------------------------------------------------*/
78/** Generate IRQ code commands.
79 * @param[out] cmds Place to store the commands.
80 * @param[in] cmd_size Size of the place (bytes).
81 * @param[in] regs Physical address of device's registers.
82 * @param[in] reg_size Size of the register area (bytes).
83 *
84 * @return Error code.
85 */
86int hc_get_irq_commands(
87 irq_cmd_t cmds[], size_t cmd_size, uintptr_t regs, size_t reg_size)
88{
89 if (cmd_size < sizeof(uhci_irq_commands)
90 || reg_size < sizeof(uhci_regs_t))
91 return EOVERFLOW;
92
93 uhci_regs_t *registers = (uhci_regs_t*)regs;
94
95 memcpy(cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
96
97 cmds[0].addr = (void*)&registers->usbsts;
98 cmds[3].addr = (void*)&registers->usbsts;
99 return EOK;
100}
[9351353]101/*----------------------------------------------------------------------------*/
[3afb758]102/** Take action based on the interrupt cause.
103 *
104 * @param[in] instance UHCI structure to use.
105 * @param[in] status Value of the status register at the time of interrupt.
106 *
107 * Interrupt might indicate:
108 * - transaction completed, either by triggering IOC, SPD, or an error
109 * - some kind of device error
110 * - resume from suspend state (not implemented)
111 */
112void hc_interrupt(hc_t *instance, uint16_t status)
113{
114 assert(instance);
115 /* Lower 2 bits are transaction error and transaction complete */
116 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
117 LIST_INITIALIZE(done);
118 transfer_list_remove_finished(
119 &instance->transfers_interrupt, &done);
120 transfer_list_remove_finished(
121 &instance->transfers_control_slow, &done);
122 transfer_list_remove_finished(
123 &instance->transfers_control_full, &done);
124 transfer_list_remove_finished(
125 &instance->transfers_bulk_full, &done);
126
127 while (!list_empty(&done)) {
128 link_t *item = list_first(&done);
129 list_remove(item);
[b991d37]130 uhci_transfer_batch_t *batch =
131 uhci_transfer_batch_from_link(item);
132 uhci_transfer_batch_call_dispose(batch);
[3afb758]133 }
134 }
135 /* Resume interrupts are not supported */
136 if (status & UHCI_STATUS_RESUME) {
137 usb_log_error("Resume interrupt!\n");
138 }
139
140 /* Bits 4 and 5 indicate hc error */
141 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
142 usb_log_error("UHCI hardware failure!.\n");
143 ++instance->hw_failures;
144 transfer_list_abort_all(&instance->transfers_interrupt);
145 transfer_list_abort_all(&instance->transfers_control_slow);
146 transfer_list_abort_all(&instance->transfers_control_full);
147 transfer_list_abort_all(&instance->transfers_bulk_full);
148
149 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
150 /* reinitialize hw, this triggers virtual disconnect*/
151 hc_init_hw(instance);
152 } else {
153 usb_log_fatal("Too many UHCI hardware failures!.\n");
154 hc_fini(instance);
155 }
156 }
157}
158/*----------------------------------------------------------------------------*/
[02cacce]159/** Initialize UHCI hc driver structure
[9351353]160 *
161 * @param[in] instance Memory place to initialize.
162 * @param[in] regs Address of I/O control registers.
[23f40280]163 * @param[in] reg_size Size of I/O control registers.
164 * @param[in] interrupts True if hw interrupts should be used.
[9351353]165 * @return Error code.
166 * @note Should be called only once on any structure.
[17ceb72]167 *
168 * Initializes memory structures, starts up hw, and launches debugger and
169 * interrupt fibrils.
[9351353]170 */
[d2bff2f]171int hc_init(hc_t *instance, void *regs, size_t reg_size, bool interrupts)
[9351353]172{
[dfe4955]173 assert(reg_size >= sizeof(uhci_regs_t));
[9351353]174 int ret;
175
[ea993d18]176#define CHECK_RET_RETURN(ret, message...) \
[9351353]177 if (ret != EOK) { \
178 usb_log_error(message); \
179 return ret; \
180 } else (void) 0
181
[ff34e5a]182 instance->hw_interrupts = interrupts;
[fcc525d]183 instance->hw_failures = 0;
184
[9351353]185 /* allow access to hc control registers */
[dfe4955]186 uhci_regs_t *io;
[e247d83]187 ret = pio_enable(regs, reg_size, (void **)&io);
[26858040]188 CHECK_RET_RETURN(ret, "Failed to gain access to registers at %p: %s.\n",
189 io, str_error(ret));
[9351353]190 instance->registers = io;
[26858040]191 usb_log_debug(
192 "Device registers at %p (%zuB) accessible.\n", io, reg_size);
[3afb758]193
194 ret = hcd_init(&instance->generic, BANDWIDTH_AVAILABLE_USB11);
195 CHECK_RET_RETURN(ret, "Failed to initialize HCD generic driver: %s.\n",
196 str_error(ret));
197
[5fe0a697]198 instance->generic.private_data = instance;
[3afb758]199 instance->generic.schedule = hc_schedule;
[1a02517]200 instance->generic.ep_add_hook = NULL;
[23b0fe8]201
[3afb758]202#undef CHECK_RET_DEST_FUN_RETURN
[9351353]203
[c01cd32]204 ret = hc_init_mem_structures(instance);
[3afb758]205 if (ret != EOK) {
206 usb_log_error(
207 "Failed to initialize UHCI memory structures: %s.\n",
208 str_error(ret));
209 hcd_destroy(&instance->generic);
210 return ret;
211 }
[9351353]212
[c01cd32]213 hc_init_hw(instance);
[ff34e5a]214 if (!interrupts) {
[ea993d18]215 instance->interrupt_emulator =
[c01cd32]216 fibril_create(hc_interrupt_emulator, instance);
[ea993d18]217 fibril_add_ready(instance->interrupt_emulator);
[ff34e5a]218 }
[ea993d18]219 (void)hc_debug_checker;
[9351353]220
221 return EOK;
222}
223/*----------------------------------------------------------------------------*/
[17ceb72]224/** Initialize UHCI hc hw resources.
[9351353]225 *
226 * @param[in] instance UHCI structure to use.
[17ceb72]227 * For magic values see UHCI Design Guide
[9351353]228 */
[3afb758]229void hc_init_hw(const hc_t *instance)
[9351353]230{
231 assert(instance);
[dfe4955]232 uhci_regs_t *registers = instance->registers;
[9351353]233
234 /* Reset everything, who knows what touched it before us */
235 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
[26858040]236 async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
[9351353]237 pio_write_16(&registers->usbcmd, 0);
238
[26858040]239 /* Reset hc, all states and counters. Hope that hw is not broken */
[9351353]240 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
241 do { async_usleep(10); }
242 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
243
[eb2a48a]244 /* Set frame to exactly 1ms */
245 pio_write_8(&registers->sofmod, 64);
246
247 /* Set frame list pointer */
[9351353]248 const uint32_t pa = addr_to_phys(instance->frame_list);
249 pio_write_32(&registers->flbaseadd, pa);
250
[ff34e5a]251 if (instance->hw_interrupts) {
252 /* Enable all interrupts, but resume interrupt */
253 pio_write_16(&instance->registers->usbintr,
[8986412]254 UHCI_INTR_ALLOW_INTERRUPTS);
[ff34e5a]255 }
[9351353]256
[26858040]257 const uint16_t cmd = pio_read_16(&registers->usbcmd);
258 if (cmd != 0)
259 usb_log_warning("Previous command value: %x.\n", cmd);
[9351353]260
261 /* Start the hc with large(64B) packet FSBR */
262 pio_write_16(&registers->usbcmd,
263 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
264}
265/*----------------------------------------------------------------------------*/
[17ceb72]266/** Initialize UHCI hc memory structures.
[9351353]267 *
268 * @param[in] instance UHCI structure to use.
269 * @return Error code
270 * @note Should be called only once on any structure.
[17ceb72]271 *
272 * Structures:
273 * - transfer lists (queue heads need to be accessible by the hw)
274 * - frame list page (needs to be one UHCI hw accessible 4K page)
[9351353]275 */
[c01cd32]276int hc_init_mem_structures(hc_t *instance)
[9351353]277{
278 assert(instance);
279
[3afb758]280 /* Init USB frame list page */
[9351353]281 instance->frame_list = get_page();
[26858040]282 if (!instance->frame_list) {
283 return ENOMEM;
284 }
[001b152]285 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
[9351353]286
[3afb758]287 /* Init transfer lists */
288 int ret = hc_init_transfer_lists(instance);
289 if (ret != EOK) {
290 usb_log_error("Failed to initialize transfer lists.\n");
291 return_page(instance->frame_list);
292 return ENOMEM;
293 }
294 usb_log_debug("Initialized transfer lists.\n");
295
296
[9351353]297 /* Set all frames to point to the first queue head */
[302a4b6]298 const uint32_t queue = LINK_POINTER_QH(
299 addr_to_phys(instance->transfers_interrupt.queue_head));
[9351353]300 unsigned i = 0;
301 for(; i < UHCI_FRAME_LIST_COUNT; ++i) {
302 instance->frame_list[i] = queue;
303 }
304
305 return EOK;
306}
307/*----------------------------------------------------------------------------*/
[17ceb72]308/** Initialize UHCI hc transfer lists.
[9351353]309 *
310 * @param[in] instance UHCI structure to use.
311 * @return Error code
312 * @note Should be called only once on any structure.
[17ceb72]313 *
314 * Initializes transfer lists and sets them in one chain to support proper
315 * USB scheduling. Sets pointer table for quick access.
[9351353]316 */
[c01cd32]317int hc_init_transfer_lists(hc_t *instance)
[9351353]318{
319 assert(instance);
[27205841]320#define SETUP_TRANSFER_LIST(type, name) \
321do { \
322 int ret = transfer_list_init(&instance->transfers_##type, name); \
[9351353]323 if (ret != EOK) { \
[26858040]324 usb_log_error("Failed to setup %s transfer list: %s.\n", \
325 name, str_error(ret)); \
[9351353]326 transfer_list_fini(&instance->transfers_bulk_full); \
327 transfer_list_fini(&instance->transfers_control_full); \
328 transfer_list_fini(&instance->transfers_control_slow); \
329 transfer_list_fini(&instance->transfers_interrupt); \
330 return ret; \
[27205841]331 } \
332} while (0)
333
334 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
335 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
336 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
337 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
338#undef SETUP_TRANSFER_LIST
339 /* Connect lists into one schedule */
[9351353]340 transfer_list_set_next(&instance->transfers_control_full,
341 &instance->transfers_bulk_full);
342 transfer_list_set_next(&instance->transfers_control_slow,
343 &instance->transfers_control_full);
344 transfer_list_set_next(&instance->transfers_interrupt,
345 &instance->transfers_control_slow);
346
[e247d83]347 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
348 * buggy on certain hw, enable at your own risk. */
[9351353]349#ifdef FSBR
350 transfer_list_set_next(&instance->transfers_bulk_full,
[302a4b6]351 &instance->transfers_control_full);
[9351353]352#endif
353
354 /* Assign pointers to be used during scheduling */
355 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
356 &instance->transfers_interrupt;
357 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
358 &instance->transfers_interrupt;
359 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
360 &instance->transfers_control_full;
361 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
362 &instance->transfers_control_slow;
363 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
364 &instance->transfers_bulk_full;
365
366 return EOK;
367#undef CHECK_RET_CLEAR_RETURN
368}
369/*----------------------------------------------------------------------------*/
[17ceb72]370/** Schedule batch for execution.
[9351353]371 *
372 * @param[in] instance UHCI structure to use.
373 * @param[in] batch Transfer batch to schedule.
374 * @return Error code
[17ceb72]375 *
376 * Checks for bandwidth availability and appends the batch to the proper queue.
[9351353]377 */
[3afb758]378int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
[9351353]379{
[3afb758]380 assert(hcd);
381 hc_t *instance = hcd->private_data;
[9351353]382 assert(instance);
383 assert(batch);
[b991d37]384 uhci_transfer_batch_t *uhci_batch = uhci_transfer_batch_get(batch);
385 if (!uhci_batch) {
386 usb_log_error("Failed to create UHCI transfer structures.\n");
387 return ENOMEM;
[23b0fe8]388 }
[9351353]389
390 transfer_list_t *list =
[d017cea]391 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
[9351353]392 assert(list);
[b991d37]393 transfer_list_add_batch(list, uhci_batch);
[9351353]394
395 return EOK;
396}
397/*----------------------------------------------------------------------------*/
398/** Polling function, emulates interrupts.
399 *
[17ceb72]400 * @param[in] arg UHCI hc structure to use.
401 * @return EOK (should never return)
[9351353]402 */
[c01cd32]403int hc_interrupt_emulator(void* arg)
[9351353]404{
405 usb_log_debug("Started interrupt emulator.\n");
[6f122df]406 hc_t *instance = arg;
[9351353]407 assert(instance);
408
409 while (1) {
[6f122df]410 /* Read and clear status register */
[9351353]411 uint16_t status = pio_read_16(&instance->registers->usbsts);
[27205841]412 pio_write_16(&instance->registers->usbsts, status);
[9351353]413 if (status != 0)
414 usb_log_debug2("UHCI status: %x.\n", status);
[c01cd32]415 hc_interrupt(instance, status);
[27205841]416 async_usleep(UHCI_INT_EMULATOR_TIMEOUT);
[9351353]417 }
418 return EOK;
419}
[3afb758]420/*----------------------------------------------------------------------------*/
[9351353]421/** Debug function, checks consistency of memory structures.
422 *
423 * @param[in] arg UHCI structure to use.
[17ceb72]424 * @return EOK (should never return)
[9351353]425 */
[c01cd32]426int hc_debug_checker(void *arg)
[9351353]427{
[6f122df]428 hc_t *instance = arg;
[9351353]429 assert(instance);
430
431#define QH(queue) \
432 instance->transfers_##queue.queue_head
433
434 while (1) {
435 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
436 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
437 const uint16_t intr =
438 pio_read_16(&instance->registers->usbintr);
439
440 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
441 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
442 cmd, sts, intr);
443 }
444
[e247d83]445 const uintptr_t frame_list =
[9351353]446 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
447 if (frame_list != addr_to_phys(instance->frame_list)) {
448 usb_log_debug("Framelist address: %p vs. %p.\n",
[4125b7d]449 (void *) frame_list,
450 (void *) addr_to_phys(instance->frame_list));
[9351353]451 }
452
453 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
454
455 uintptr_t expected_pa = instance->frame_list[frnum]
456 & LINK_POINTER_ADDRESS_MASK;
457 uintptr_t real_pa = addr_to_phys(QH(interrupt));
458 if (expected_pa != real_pa) {
[4125b7d]459 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
460 (void *) expected_pa, frnum, (void *) real_pa);
[9351353]461 }
462
463 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
464 real_pa = addr_to_phys(QH(control_slow));
465 if (expected_pa != real_pa) {
466 usb_log_debug("Control Slow QH: %p vs. %p.\n",
[4125b7d]467 (void *) expected_pa, (void *) real_pa);
[9351353]468 }
469
470 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
471 real_pa = addr_to_phys(QH(control_full));
472 if (expected_pa != real_pa) {
473 usb_log_debug("Control Full QH: %p vs. %p.\n",
[4125b7d]474 (void *) expected_pa, (void *) real_pa);
[9351353]475 }
476
477 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
478 real_pa = addr_to_phys(QH(bulk_full));
479 if (expected_pa != real_pa ) {
480 usb_log_debug("Bulk QH: %p vs. %p.\n",
[4125b7d]481 (void *) expected_pa, (void *) real_pa);
[9351353]482 }
483 async_usleep(UHCI_DEBUGER_TIMEOUT);
484 }
485 return EOK;
486#undef QH
487}
488/**
489 * @}
490 */
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