source: mainline/uspace/drv/bus/usb/uhci/hc.c@ 4ca778b

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 4ca778b was e646c61, checked in by Jan Vesely <jano.vesely@…>, 13 years ago

uhci: Add rh debug messages

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File size: 15.3 KB
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[9351353]1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
[17ceb72]28/** @addtogroup drvusbuhcihc
[9351353]29 * @{
30 */
31/** @file
[17ceb72]32 * @brief UHCI Host controller driver routines
[9351353]33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
[1ae74c6]37#include <ddi.h>
[9351353]38
39#include <usb/debug.h>
40#include <usb/usb.h>
41
[c01cd32]42#include "hc.h"
[07f49ae]43#include "uhci_batch.h"
[9351353]44
[8986412]45#define UHCI_INTR_ALLOW_INTERRUPTS \
[af81980]46 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
[8986412]47#define UHCI_STATUS_USED_INTERRUPTS \
48 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
[af81980]49
[d57122c]50static const irq_pio_range_t uhci_irq_pio_ranges[] = {
51 {
[8486c07]52 .base = 0,
[d57122c]53 .size = sizeof(uhci_regs_t)
54 }
55};
[5fe0a697]56
[d57122c]57static const irq_cmd_t uhci_irq_commands[] = {
[8486c07]58 {
59 .cmd = CMD_PIO_READ_16,
60 .dstarg = 1,
61 .addr = NULL
62 },
63 {
64 .cmd = CMD_AND,
65 .srcarg = 1,
66 .dstarg = 2,
67 .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS
68 },
69 {
70 .cmd = CMD_PREDICATE,
71 .srcarg = 2,
72 .value = 2
73 },
74 {
75 .cmd = CMD_PIO_WRITE_A_16,
76 .srcarg = 1,
77 .addr = NULL
78 },
79 {
80 .cmd = CMD_ACCEPT
81 }
[dfe4955]82};
[302a4b6]83
[3afb758]84static void hc_init_hw(const hc_t *instance);
[c01cd32]85static int hc_init_mem_structures(hc_t *instance);
[3afb758]86static int hc_init_transfer_lists(hc_t *instance);
[9351353]87
[c01cd32]88static int hc_interrupt_emulator(void *arg);
89static int hc_debug_checker(void *arg);
[dfe4955]90
[76fbd9a]91
[d57122c]92/** Get number of PIO ranges used in IRQ code.
93 * @return Number of ranges.
94 */
95size_t hc_irq_pio_range_count(void)
96{
97 return sizeof(uhci_irq_pio_ranges) / sizeof(irq_pio_range_t);
98}
[76fbd9a]99
[dfe4955]100/** Get number of commands used in IRQ code.
101 * @return Number of commands.
102 */
103size_t hc_irq_cmd_count(void)
104{
105 return sizeof(uhci_irq_commands) / sizeof(irq_cmd_t);
106}
[76fbd9a]107
[d57122c]108/** Generate IRQ code.
109 * @param[out] ranges PIO ranges buffer.
110 * @param[in] ranges_size Size of the ranges buffer (bytes).
111 * @param[out] cmds Commands buffer.
112 * @param[in] cmds_size Size of the commands buffer (bytes).
[dfe4955]113 * @param[in] regs Physical address of device's registers.
114 * @param[in] reg_size Size of the register area (bytes).
115 *
116 * @return Error code.
117 */
[d57122c]118int
119hc_get_irq_code(irq_pio_range_t ranges[], size_t ranges_size, irq_cmd_t cmds[],
120 size_t cmds_size, uintptr_t regs, size_t reg_size)
[dfe4955]121{
[d57122c]122 if ((ranges_size < sizeof(uhci_irq_pio_ranges)) ||
123 (cmds_size < sizeof(uhci_irq_commands)) ||
124 (reg_size < sizeof(uhci_regs_t)))
[dfe4955]125 return EOVERFLOW;
126
[d57122c]127 memcpy(ranges, uhci_irq_pio_ranges, sizeof(uhci_irq_pio_ranges));
128 ranges[0].base = regs;
[dfe4955]129
130 memcpy(cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
[d57122c]131 uhci_regs_t *registers = (uhci_regs_t *) regs;
[c95c00e]132 cmds[0].addr = (void*)&registers->usbsts;
133 cmds[3].addr = (void*)&registers->usbsts;
[dfe4955]134
135 return EOK;
136}
[76fbd9a]137
[3afb758]138/** Take action based on the interrupt cause.
139 *
140 * @param[in] instance UHCI structure to use.
141 * @param[in] status Value of the status register at the time of interrupt.
142 *
143 * Interrupt might indicate:
144 * - transaction completed, either by triggering IOC, SPD, or an error
145 * - some kind of device error
146 * - resume from suspend state (not implemented)
147 */
148void hc_interrupt(hc_t *instance, uint16_t status)
149{
150 assert(instance);
151 /* Lower 2 bits are transaction error and transaction complete */
152 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
153 LIST_INITIALIZE(done);
154 transfer_list_remove_finished(
155 &instance->transfers_interrupt, &done);
156 transfer_list_remove_finished(
157 &instance->transfers_control_slow, &done);
158 transfer_list_remove_finished(
159 &instance->transfers_control_full, &done);
160 transfer_list_remove_finished(
161 &instance->transfers_bulk_full, &done);
162
163 while (!list_empty(&done)) {
164 link_t *item = list_first(&done);
165 list_remove(item);
[b991d37]166 uhci_transfer_batch_t *batch =
167 uhci_transfer_batch_from_link(item);
[6bba41d]168 uhci_transfer_batch_finish_dispose(batch);
[3afb758]169 }
170 }
171 /* Resume interrupts are not supported */
172 if (status & UHCI_STATUS_RESUME) {
173 usb_log_error("Resume interrupt!\n");
174 }
175
176 /* Bits 4 and 5 indicate hc error */
177 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
178 usb_log_error("UHCI hardware failure!.\n");
179 ++instance->hw_failures;
180 transfer_list_abort_all(&instance->transfers_interrupt);
181 transfer_list_abort_all(&instance->transfers_control_slow);
182 transfer_list_abort_all(&instance->transfers_control_full);
183 transfer_list_abort_all(&instance->transfers_bulk_full);
184
185 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
186 /* reinitialize hw, this triggers virtual disconnect*/
187 hc_init_hw(instance);
188 } else {
189 usb_log_fatal("Too many UHCI hardware failures!.\n");
190 hc_fini(instance);
191 }
192 }
193}
[76fbd9a]194
[02cacce]195/** Initialize UHCI hc driver structure
[9351353]196 *
197 * @param[in] instance Memory place to initialize.
198 * @param[in] regs Address of I/O control registers.
[23f40280]199 * @param[in] reg_size Size of I/O control registers.
200 * @param[in] interrupts True if hw interrupts should be used.
[9351353]201 * @return Error code.
202 * @note Should be called only once on any structure.
[17ceb72]203 *
204 * Initializes memory structures, starts up hw, and launches debugger and
205 * interrupt fibrils.
[9351353]206 */
[d2bff2f]207int hc_init(hc_t *instance, void *regs, size_t reg_size, bool interrupts)
[9351353]208{
[dfe4955]209 assert(reg_size >= sizeof(uhci_regs_t));
[9351353]210 int ret;
211
[ea993d18]212#define CHECK_RET_RETURN(ret, message...) \
[9351353]213 if (ret != EOK) { \
214 usb_log_error(message); \
215 return ret; \
216 } else (void) 0
217
[ff34e5a]218 instance->hw_interrupts = interrupts;
[fcc525d]219 instance->hw_failures = 0;
220
[9351353]221 /* allow access to hc control registers */
[dfe4955]222 uhci_regs_t *io;
[e247d83]223 ret = pio_enable(regs, reg_size, (void **)&io);
[26858040]224 CHECK_RET_RETURN(ret, "Failed to gain access to registers at %p: %s.\n",
225 io, str_error(ret));
[9351353]226 instance->registers = io;
[26858040]227 usb_log_debug(
228 "Device registers at %p (%zuB) accessible.\n", io, reg_size);
[3afb758]229
[7265558]230 ret = hc_init_mem_structures(instance);
231 CHECK_RET_RETURN(ret,
232 "Failed to initialize UHCI memory structures: %s.\n",
[3afb758]233 str_error(ret));
234
[7265558]235#undef CHECK_RET_RETURN
236
[c01cd32]237 hc_init_hw(instance);
[ff34e5a]238 if (!interrupts) {
[ea993d18]239 instance->interrupt_emulator =
[c01cd32]240 fibril_create(hc_interrupt_emulator, instance);
[ea993d18]241 fibril_add_ready(instance->interrupt_emulator);
[ff34e5a]242 }
[ea993d18]243 (void)hc_debug_checker;
[9351353]244
[e646c61]245 uhci_rh_init(&instance->rh, instance->registers->ports, "uhci");
[c95c00e]246
[9351353]247 return EOK;
248}
[76fbd9a]249
[17ceb72]250/** Initialize UHCI hc hw resources.
[9351353]251 *
252 * @param[in] instance UHCI structure to use.
[17ceb72]253 * For magic values see UHCI Design Guide
[9351353]254 */
[3afb758]255void hc_init_hw(const hc_t *instance)
[9351353]256{
257 assert(instance);
[dfe4955]258 uhci_regs_t *registers = instance->registers;
[9351353]259
260 /* Reset everything, who knows what touched it before us */
261 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
[26858040]262 async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
[9351353]263 pio_write_16(&registers->usbcmd, 0);
264
[26858040]265 /* Reset hc, all states and counters. Hope that hw is not broken */
[9351353]266 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
267 do { async_usleep(10); }
268 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
269
[eb2a48a]270 /* Set frame to exactly 1ms */
271 pio_write_8(&registers->sofmod, 64);
272
273 /* Set frame list pointer */
[9351353]274 const uint32_t pa = addr_to_phys(instance->frame_list);
275 pio_write_32(&registers->flbaseadd, pa);
276
[ff34e5a]277 if (instance->hw_interrupts) {
278 /* Enable all interrupts, but resume interrupt */
279 pio_write_16(&instance->registers->usbintr,
[8986412]280 UHCI_INTR_ALLOW_INTERRUPTS);
[ff34e5a]281 }
[9351353]282
[26858040]283 const uint16_t cmd = pio_read_16(&registers->usbcmd);
284 if (cmd != 0)
285 usb_log_warning("Previous command value: %x.\n", cmd);
[9351353]286
287 /* Start the hc with large(64B) packet FSBR */
288 pio_write_16(&registers->usbcmd,
289 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
290}
[76fbd9a]291
[17ceb72]292/** Initialize UHCI hc memory structures.
[9351353]293 *
294 * @param[in] instance UHCI structure to use.
295 * @return Error code
296 * @note Should be called only once on any structure.
[17ceb72]297 *
298 * Structures:
299 * - transfer lists (queue heads need to be accessible by the hw)
300 * - frame list page (needs to be one UHCI hw accessible 4K page)
[9351353]301 */
[c01cd32]302int hc_init_mem_structures(hc_t *instance)
[9351353]303{
304 assert(instance);
305
[3afb758]306 /* Init USB frame list page */
[9351353]307 instance->frame_list = get_page();
[26858040]308 if (!instance->frame_list) {
309 return ENOMEM;
310 }
[001b152]311 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
[9351353]312
[3afb758]313 /* Init transfer lists */
314 int ret = hc_init_transfer_lists(instance);
315 if (ret != EOK) {
316 usb_log_error("Failed to initialize transfer lists.\n");
317 return_page(instance->frame_list);
318 return ENOMEM;
319 }
320 usb_log_debug("Initialized transfer lists.\n");
321
322
[9351353]323 /* Set all frames to point to the first queue head */
[302a4b6]324 const uint32_t queue = LINK_POINTER_QH(
325 addr_to_phys(instance->transfers_interrupt.queue_head));
[75f9dcd]326
327 for (unsigned i = 0; i < UHCI_FRAME_LIST_COUNT; ++i) {
[9351353]328 instance->frame_list[i] = queue;
329 }
330
331 return EOK;
332}
[76fbd9a]333
[17ceb72]334/** Initialize UHCI hc transfer lists.
[9351353]335 *
336 * @param[in] instance UHCI structure to use.
337 * @return Error code
338 * @note Should be called only once on any structure.
[17ceb72]339 *
340 * Initializes transfer lists and sets them in one chain to support proper
341 * USB scheduling. Sets pointer table for quick access.
[9351353]342 */
[c01cd32]343int hc_init_transfer_lists(hc_t *instance)
[9351353]344{
345 assert(instance);
[27205841]346#define SETUP_TRANSFER_LIST(type, name) \
347do { \
348 int ret = transfer_list_init(&instance->transfers_##type, name); \
[9351353]349 if (ret != EOK) { \
[26858040]350 usb_log_error("Failed to setup %s transfer list: %s.\n", \
351 name, str_error(ret)); \
[9351353]352 transfer_list_fini(&instance->transfers_bulk_full); \
353 transfer_list_fini(&instance->transfers_control_full); \
354 transfer_list_fini(&instance->transfers_control_slow); \
355 transfer_list_fini(&instance->transfers_interrupt); \
356 return ret; \
[27205841]357 } \
358} while (0)
359
360 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
361 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
362 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
363 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
364#undef SETUP_TRANSFER_LIST
365 /* Connect lists into one schedule */
[9351353]366 transfer_list_set_next(&instance->transfers_control_full,
367 &instance->transfers_bulk_full);
368 transfer_list_set_next(&instance->transfers_control_slow,
369 &instance->transfers_control_full);
370 transfer_list_set_next(&instance->transfers_interrupt,
371 &instance->transfers_control_slow);
372
[e247d83]373 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
374 * buggy on certain hw, enable at your own risk. */
[9351353]375#ifdef FSBR
376 transfer_list_set_next(&instance->transfers_bulk_full,
[302a4b6]377 &instance->transfers_control_full);
[9351353]378#endif
379
380 /* Assign pointers to be used during scheduling */
381 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
382 &instance->transfers_interrupt;
383 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
384 &instance->transfers_interrupt;
385 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
386 &instance->transfers_control_full;
387 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
388 &instance->transfers_control_slow;
389 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
390 &instance->transfers_bulk_full;
391
392 return EOK;
393#undef CHECK_RET_CLEAR_RETURN
394}
[76fbd9a]395
[17ceb72]396/** Schedule batch for execution.
[9351353]397 *
398 * @param[in] instance UHCI structure to use.
399 * @param[in] batch Transfer batch to schedule.
400 * @return Error code
[17ceb72]401 *
402 * Checks for bandwidth availability and appends the batch to the proper queue.
[9351353]403 */
[3afb758]404int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
[9351353]405{
[3afb758]406 assert(hcd);
407 hc_t *instance = hcd->private_data;
[9351353]408 assert(instance);
409 assert(batch);
[c95c00e]410
[3848fec]411 if (batch->ep->address == uhci_rh_get_address(&instance->rh))
412 return uhci_rh_schedule(&instance->rh, batch);
[c95c00e]413
[b991d37]414 uhci_transfer_batch_t *uhci_batch = uhci_transfer_batch_get(batch);
415 if (!uhci_batch) {
416 usb_log_error("Failed to create UHCI transfer structures.\n");
417 return ENOMEM;
[23b0fe8]418 }
[9351353]419
420 transfer_list_t *list =
[d017cea]421 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
[9351353]422 assert(list);
[b991d37]423 transfer_list_add_batch(list, uhci_batch);
[9351353]424
425 return EOK;
426}
[76fbd9a]427
[9351353]428/** Polling function, emulates interrupts.
429 *
[17ceb72]430 * @param[in] arg UHCI hc structure to use.
431 * @return EOK (should never return)
[9351353]432 */
[c01cd32]433int hc_interrupt_emulator(void* arg)
[9351353]434{
435 usb_log_debug("Started interrupt emulator.\n");
[6f122df]436 hc_t *instance = arg;
[9351353]437 assert(instance);
438
439 while (1) {
[6f122df]440 /* Read and clear status register */
[9351353]441 uint16_t status = pio_read_16(&instance->registers->usbsts);
[27205841]442 pio_write_16(&instance->registers->usbsts, status);
[9351353]443 if (status != 0)
444 usb_log_debug2("UHCI status: %x.\n", status);
[c01cd32]445 hc_interrupt(instance, status);
[27205841]446 async_usleep(UHCI_INT_EMULATOR_TIMEOUT);
[9351353]447 }
448 return EOK;
449}
[76fbd9a]450
[9351353]451/** Debug function, checks consistency of memory structures.
452 *
453 * @param[in] arg UHCI structure to use.
[17ceb72]454 * @return EOK (should never return)
[9351353]455 */
[c01cd32]456int hc_debug_checker(void *arg)
[9351353]457{
[6f122df]458 hc_t *instance = arg;
[9351353]459 assert(instance);
460
461#define QH(queue) \
462 instance->transfers_##queue.queue_head
463
464 while (1) {
465 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
466 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
467 const uint16_t intr =
468 pio_read_16(&instance->registers->usbintr);
469
470 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
471 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
472 cmd, sts, intr);
473 }
474
[e247d83]475 const uintptr_t frame_list =
[9351353]476 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
477 if (frame_list != addr_to_phys(instance->frame_list)) {
478 usb_log_debug("Framelist address: %p vs. %p.\n",
[4125b7d]479 (void *) frame_list,
480 (void *) addr_to_phys(instance->frame_list));
[9351353]481 }
482
483 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
484
485 uintptr_t expected_pa = instance->frame_list[frnum]
486 & LINK_POINTER_ADDRESS_MASK;
487 uintptr_t real_pa = addr_to_phys(QH(interrupt));
488 if (expected_pa != real_pa) {
[4125b7d]489 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
490 (void *) expected_pa, frnum, (void *) real_pa);
[9351353]491 }
492
493 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
494 real_pa = addr_to_phys(QH(control_slow));
495 if (expected_pa != real_pa) {
496 usb_log_debug("Control Slow QH: %p vs. %p.\n",
[4125b7d]497 (void *) expected_pa, (void *) real_pa);
[9351353]498 }
499
500 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
501 real_pa = addr_to_phys(QH(control_full));
502 if (expected_pa != real_pa) {
503 usb_log_debug("Control Full QH: %p vs. %p.\n",
[4125b7d]504 (void *) expected_pa, (void *) real_pa);
[9351353]505 }
506
507 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
508 real_pa = addr_to_phys(QH(bulk_full));
509 if (expected_pa != real_pa ) {
510 usb_log_debug("Bulk QH: %p vs. %p.\n",
[4125b7d]511 (void *) expected_pa, (void *) real_pa);
[9351353]512 }
513 async_usleep(UHCI_DEBUGER_TIMEOUT);
514 }
515 return EOK;
516#undef QH
517}
518/**
519 * @}
520 */
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