[9351353] | 1 | /*
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| 2 | * Copyright (c) 2011 Jan Vesely
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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[58563585] | 28 |
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[17ceb72] | 29 | /** @addtogroup drvusbuhcihc
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[9351353] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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[17ceb72] | 33 | * @brief UHCI Host controller driver routines
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[9351353] | 34 | */
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[8064c2f6] | 35 |
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[9351353] | 36 | #include <adt/list.h>
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[8064c2f6] | 37 | #include <assert.h>
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| 38 | #include <async.h>
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[1ae74c6] | 39 | #include <ddi.h>
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[8064c2f6] | 40 | #include <device/hw_res_parsed.h>
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| 41 | #include <fibril.h>
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| 42 | #include <errno.h>
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| 43 | #include <macros.h>
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| 44 | #include <mem.h>
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| 45 | #include <stdlib.h>
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[8d2dd7f2] | 46 | #include <stdint.h>
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[8064c2f6] | 47 | #include <str_error.h>
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[9351353] | 48 |
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| 49 | #include <usb/debug.h>
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| 50 | #include <usb/usb.h>
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[8fc61c8] | 51 | #include <usb/host/utils/malloc32.h>
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[9351353] | 52 |
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[07f49ae] | 53 | #include "uhci_batch.h"
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[8064c2f6] | 54 | #include "hc.h"
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[9351353] | 55 |
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[8986412] | 56 | #define UHCI_INTR_ALLOW_INTERRUPTS \
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[af81980] | 57 | (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
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[8986412] | 58 | #define UHCI_STATUS_USED_INTERRUPTS \
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| 59 | (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
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[af81980] | 60 |
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[d57122c] | 61 | static const irq_pio_range_t uhci_irq_pio_ranges[] = {
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| 62 | {
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[8486c07] | 63 | .base = 0,
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[d57122c] | 64 | .size = sizeof(uhci_regs_t)
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| 65 | }
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| 66 | };
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[5fe0a697] | 67 |
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[d57122c] | 68 | static const irq_cmd_t uhci_irq_commands[] = {
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[8486c07] | 69 | {
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| 70 | .cmd = CMD_PIO_READ_16,
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| 71 | .dstarg = 1,
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| 72 | .addr = NULL
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| 73 | },
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| 74 | {
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| 75 | .cmd = CMD_AND,
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| 76 | .srcarg = 1,
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| 77 | .dstarg = 2,
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| 78 | .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS
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| 79 | },
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| 80 | {
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| 81 | .cmd = CMD_PREDICATE,
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| 82 | .srcarg = 2,
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| 83 | .value = 2
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| 84 | },
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| 85 | {
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| 86 | .cmd = CMD_PIO_WRITE_A_16,
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| 87 | .srcarg = 1,
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| 88 | .addr = NULL
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| 89 | },
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| 90 | {
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| 91 | .cmd = CMD_ACCEPT
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| 92 | }
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[dfe4955] | 93 | };
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[302a4b6] | 94 |
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[3afb758] | 95 | static void hc_init_hw(const hc_t *instance);
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[c01cd32] | 96 | static int hc_init_mem_structures(hc_t *instance);
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[3afb758] | 97 | static int hc_init_transfer_lists(hc_t *instance);
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[9351353] | 98 |
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[c01cd32] | 99 | static int hc_debug_checker(void *arg);
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[dfe4955] | 100 |
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[76fbd9a] | 101 |
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[d57122c] | 102 | /** Generate IRQ code.
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[6210a333] | 103 | * @param[out] code IRQ code structure.
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[ba4a03a5] | 104 | * @param[in] hw_res Device's resources.
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[dfe4955] | 105 | *
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| 106 | * @return Error code.
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| 107 | */
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[e4d7363] | 108 | int uhci_hc_gen_irq_code(irq_code_t *code, hcd_t *hcd, const hw_res_list_parsed_t *hw_res)
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[dfe4955] | 109 | {
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[6210a333] | 110 | assert(code);
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[ba4a03a5] | 111 | assert(hw_res);
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[6210a333] | 112 |
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[ba4a03a5] | 113 | if (hw_res->irqs.count != 1 || hw_res->io_ranges.count != 1)
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| 114 | return EINVAL;
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| 115 | const addr_range_t regs = hw_res->io_ranges.ranges[0];
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| 116 |
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| 117 | if (RNGSZ(regs) < sizeof(uhci_regs_t))
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[dfe4955] | 118 | return EOVERFLOW;
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| 119 |
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[6210a333] | 120 | code->ranges = malloc(sizeof(uhci_irq_pio_ranges));
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| 121 | if (code->ranges == NULL)
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| 122 | return ENOMEM;
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| 123 |
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| 124 | code->cmds = malloc(sizeof(uhci_irq_commands));
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| 125 | if (code->cmds == NULL) {
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| 126 | free(code->ranges);
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| 127 | return ENOMEM;
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| 128 | }
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| 129 |
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| 130 | code->rangecount = ARRAY_SIZE(uhci_irq_pio_ranges);
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| 131 | code->cmdcount = ARRAY_SIZE(uhci_irq_commands);
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[dfe4955] | 132 |
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[6210a333] | 133 | memcpy(code->ranges, uhci_irq_pio_ranges, sizeof(uhci_irq_pio_ranges));
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[ba4a03a5] | 134 | code->ranges[0].base = RNGABS(regs);
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[6210a333] | 135 |
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| 136 | memcpy(code->cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
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[ba4a03a5] | 137 | uhci_regs_t *registers = (uhci_regs_t *) RNGABSPTR(regs);
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[6210a333] | 138 | code->cmds[0].addr = (void*)®isters->usbsts;
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| 139 | code->cmds[3].addr = (void*)®isters->usbsts;
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[dfe4955] | 140 |
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[ba4a03a5] | 141 | usb_log_debug("I/O regs at %p (size %zu), IRQ %d.\n",
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| 142 | RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
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| 143 |
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| 144 | return hw_res->irqs.irqs[0];
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[dfe4955] | 145 | }
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[76fbd9a] | 146 |
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[3afb758] | 147 | /** Take action based on the interrupt cause.
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| 148 | *
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[4bfcf22] | 149 | * @param[in] hcd HCD structure to use.
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[3afb758] | 150 | * @param[in] status Value of the status register at the time of interrupt.
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| 151 | *
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| 152 | * Interrupt might indicate:
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| 153 | * - transaction completed, either by triggering IOC, SPD, or an error
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| 154 | * - some kind of device error
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| 155 | * - resume from suspend state (not implemented)
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| 156 | */
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[9f6cb910] | 157 | void uhci_hc_interrupt(hcd_t *hcd, uint32_t status)
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[3afb758] | 158 | {
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[4bfcf22] | 159 | assert(hcd);
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[b5f813c] | 160 | hc_t *instance = hcd_get_driver_data(hcd);
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[3afb758] | 161 | assert(instance);
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| 162 | /* Lower 2 bits are transaction error and transaction complete */
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| 163 | if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
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| 164 | LIST_INITIALIZE(done);
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| 165 | transfer_list_remove_finished(
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| 166 | &instance->transfers_interrupt, &done);
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| 167 | transfer_list_remove_finished(
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| 168 | &instance->transfers_control_slow, &done);
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| 169 | transfer_list_remove_finished(
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| 170 | &instance->transfers_control_full, &done);
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| 171 | transfer_list_remove_finished(
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| 172 | &instance->transfers_bulk_full, &done);
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| 173 |
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[ad5f149] | 174 | list_foreach_safe(done, current, next) {
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| 175 | list_remove(current);
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[b991d37] | 176 | uhci_transfer_batch_t *batch =
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[ad5f149] | 177 | uhci_transfer_batch_from_link(current);
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[6bba41d] | 178 | uhci_transfer_batch_finish_dispose(batch);
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[3afb758] | 179 | }
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| 180 | }
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| 181 | /* Resume interrupts are not supported */
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| 182 | if (status & UHCI_STATUS_RESUME) {
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| 183 | usb_log_error("Resume interrupt!\n");
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| 184 | }
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| 185 |
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| 186 | /* Bits 4 and 5 indicate hc error */
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| 187 | if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
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| 188 | usb_log_error("UHCI hardware failure!.\n");
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| 189 | ++instance->hw_failures;
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| 190 | transfer_list_abort_all(&instance->transfers_interrupt);
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| 191 | transfer_list_abort_all(&instance->transfers_control_slow);
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| 192 | transfer_list_abort_all(&instance->transfers_control_full);
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| 193 | transfer_list_abort_all(&instance->transfers_bulk_full);
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| 194 |
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| 195 | if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
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| 196 | /* reinitialize hw, this triggers virtual disconnect*/
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| 197 | hc_init_hw(instance);
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| 198 | } else {
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| 199 | usb_log_fatal("Too many UHCI hardware failures!.\n");
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| 200 | hc_fini(instance);
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| 201 | }
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| 202 | }
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| 203 | }
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[76fbd9a] | 204 |
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[02cacce] | 205 | /** Initialize UHCI hc driver structure
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[9351353] | 206 | *
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| 207 | * @param[in] instance Memory place to initialize.
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[7de1988c] | 208 | * @param[in] regs Range of device's I/O control registers.
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[23f40280] | 209 | * @param[in] interrupts True if hw interrupts should be used.
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[9351353] | 210 | * @return Error code.
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| 211 | * @note Should be called only once on any structure.
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[17ceb72] | 212 | *
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| 213 | * Initializes memory structures, starts up hw, and launches debugger and
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| 214 | * interrupt fibrils.
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[9351353] | 215 | */
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[e4d7363] | 216 | int hc_init(hc_t *instance, const hw_res_list_parsed_t *hw_res)
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[9351353] | 217 | {
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[3f03199] | 218 | assert(instance);
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[7813516] | 219 | assert(hw_res);
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| 220 | if (hw_res->io_ranges.count != 1 ||
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| 221 | hw_res->io_ranges.ranges[0].size < sizeof(uhci_regs_t))
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| 222 | return EINVAL;
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[9351353] | 223 |
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[fcc525d] | 224 | instance->hw_failures = 0;
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| 225 |
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[9351353] | 226 | /* allow access to hc control registers */
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[7813516] | 227 | int ret = pio_enable_range(&hw_res->io_ranges.ranges[0],
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| 228 | (void **) &instance->registers);
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[e0d8b740] | 229 | if (ret != EOK) {
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[7813516] | 230 | usb_log_error("Failed to gain access to registers: %s.\n",
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| 231 | str_error(ret));
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[e0d8b740] | 232 | return ret;
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| 233 | }
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| 234 |
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[7813516] | 235 | usb_log_debug("Device registers at %" PRIx64 " (%zuB) accessible.\n",
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| 236 | hw_res->io_ranges.ranges[0].address.absolute,
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| 237 | hw_res->io_ranges.ranges[0].size);
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[3afb758] | 238 |
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[7265558] | 239 | ret = hc_init_mem_structures(instance);
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[e0d8b740] | 240 | if (ret != EOK) {
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| 241 | usb_log_error("Failed to init UHCI memory structures: %s.\n",
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| 242 | str_error(ret));
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| 243 | // TODO: we should disable pio here
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| 244 | return ret;
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| 245 | }
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[7265558] | 246 |
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[e4d7363] | 247 | return EOK;
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| 248 | }
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| 249 |
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| 250 | void hc_start(hc_t *instance)
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| 251 | {
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[c01cd32] | 252 | hc_init_hw(instance);
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[ea993d18] | 253 | (void)hc_debug_checker;
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[9351353] | 254 |
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[e646c61] | 255 | uhci_rh_init(&instance->rh, instance->registers->ports, "uhci");
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[9351353] | 256 | }
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[76fbd9a] | 257 |
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[7813516] | 258 | /** Safely dispose host controller internal structures
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| 259 | *
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| 260 | * @param[in] instance Host controller structure to use.
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| 261 | */
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| 262 | void hc_fini(hc_t *instance)
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| 263 | {
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| 264 | assert(instance);
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| 265 | //TODO Implement
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| 266 | }
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| 267 |
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[17ceb72] | 268 | /** Initialize UHCI hc hw resources.
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[9351353] | 269 | *
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| 270 | * @param[in] instance UHCI structure to use.
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[17ceb72] | 271 | * For magic values see UHCI Design Guide
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[9351353] | 272 | */
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[3afb758] | 273 | void hc_init_hw(const hc_t *instance)
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[9351353] | 274 | {
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| 275 | assert(instance);
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[dfe4955] | 276 | uhci_regs_t *registers = instance->registers;
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[9351353] | 277 |
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| 278 | /* Reset everything, who knows what touched it before us */
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| 279 | pio_write_16(®isters->usbcmd, UHCI_CMD_GLOBAL_RESET);
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[26858040] | 280 | async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
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[9351353] | 281 | pio_write_16(®isters->usbcmd, 0);
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| 282 |
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[26858040] | 283 | /* Reset hc, all states and counters. Hope that hw is not broken */
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[9351353] | 284 | pio_write_16(®isters->usbcmd, UHCI_CMD_HCRESET);
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| 285 | do { async_usleep(10); }
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| 286 | while ((pio_read_16(®isters->usbcmd) & UHCI_CMD_HCRESET) != 0);
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| 287 |
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[eb2a48a] | 288 | /* Set frame to exactly 1ms */
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| 289 | pio_write_8(®isters->sofmod, 64);
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| 290 |
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| 291 | /* Set frame list pointer */
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[9351353] | 292 | const uint32_t pa = addr_to_phys(instance->frame_list);
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| 293 | pio_write_32(®isters->flbaseadd, pa);
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| 294 |
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[ff34e5a] | 295 | if (instance->hw_interrupts) {
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| 296 | /* Enable all interrupts, but resume interrupt */
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| 297 | pio_write_16(&instance->registers->usbintr,
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[8986412] | 298 | UHCI_INTR_ALLOW_INTERRUPTS);
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[ff34e5a] | 299 | }
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[9351353] | 300 |
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[26858040] | 301 | const uint16_t cmd = pio_read_16(®isters->usbcmd);
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| 302 | if (cmd != 0)
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| 303 | usb_log_warning("Previous command value: %x.\n", cmd);
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[9351353] | 304 |
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| 305 | /* Start the hc with large(64B) packet FSBR */
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| 306 | pio_write_16(®isters->usbcmd,
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| 307 | UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
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| 308 | }
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[76fbd9a] | 309 |
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[17ceb72] | 310 | /** Initialize UHCI hc memory structures.
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[9351353] | 311 | *
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| 312 | * @param[in] instance UHCI structure to use.
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| 313 | * @return Error code
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| 314 | * @note Should be called only once on any structure.
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[17ceb72] | 315 | *
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| 316 | * Structures:
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| 317 | * - transfer lists (queue heads need to be accessible by the hw)
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| 318 | * - frame list page (needs to be one UHCI hw accessible 4K page)
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[9351353] | 319 | */
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[c01cd32] | 320 | int hc_init_mem_structures(hc_t *instance)
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[9351353] | 321 | {
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| 322 | assert(instance);
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| 323 |
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[3afb758] | 324 | /* Init USB frame list page */
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[9351353] | 325 | instance->frame_list = get_page();
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[26858040] | 326 | if (!instance->frame_list) {
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| 327 | return ENOMEM;
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| 328 | }
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[001b152] | 329 | usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
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[9351353] | 330 |
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[3afb758] | 331 | /* Init transfer lists */
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| 332 | int ret = hc_init_transfer_lists(instance);
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| 333 | if (ret != EOK) {
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| 334 | usb_log_error("Failed to initialize transfer lists.\n");
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| 335 | return_page(instance->frame_list);
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| 336 | return ENOMEM;
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| 337 | }
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| 338 | usb_log_debug("Initialized transfer lists.\n");
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| 339 |
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| 340 |
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[9351353] | 341 | /* Set all frames to point to the first queue head */
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[302a4b6] | 342 | const uint32_t queue = LINK_POINTER_QH(
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| 343 | addr_to_phys(instance->transfers_interrupt.queue_head));
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[75f9dcd] | 344 |
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| 345 | for (unsigned i = 0; i < UHCI_FRAME_LIST_COUNT; ++i) {
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[9351353] | 346 | instance->frame_list[i] = queue;
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| 347 | }
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| 348 |
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| 349 | return EOK;
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| 350 | }
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[76fbd9a] | 351 |
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[17ceb72] | 352 | /** Initialize UHCI hc transfer lists.
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[9351353] | 353 | *
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| 354 | * @param[in] instance UHCI structure to use.
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| 355 | * @return Error code
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| 356 | * @note Should be called only once on any structure.
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[17ceb72] | 357 | *
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| 358 | * Initializes transfer lists and sets them in one chain to support proper
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| 359 | * USB scheduling. Sets pointer table for quick access.
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[9351353] | 360 | */
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[c01cd32] | 361 | int hc_init_transfer_lists(hc_t *instance)
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[9351353] | 362 | {
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| 363 | assert(instance);
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[27205841] | 364 | #define SETUP_TRANSFER_LIST(type, name) \
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| 365 | do { \
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| 366 | int ret = transfer_list_init(&instance->transfers_##type, name); \
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[9351353] | 367 | if (ret != EOK) { \
|
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[26858040] | 368 | usb_log_error("Failed to setup %s transfer list: %s.\n", \
|
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| 369 | name, str_error(ret)); \
|
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[9351353] | 370 | transfer_list_fini(&instance->transfers_bulk_full); \
|
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| 371 | transfer_list_fini(&instance->transfers_control_full); \
|
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| 372 | transfer_list_fini(&instance->transfers_control_slow); \
|
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| 373 | transfer_list_fini(&instance->transfers_interrupt); \
|
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| 374 | return ret; \
|
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[27205841] | 375 | } \
|
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| 376 | } while (0)
|
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| 377 |
|
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| 378 | SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
|
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| 379 | SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
|
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| 380 | SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
|
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| 381 | SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
|
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| 382 | #undef SETUP_TRANSFER_LIST
|
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| 383 | /* Connect lists into one schedule */
|
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[9351353] | 384 | transfer_list_set_next(&instance->transfers_control_full,
|
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| 385 | &instance->transfers_bulk_full);
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| 386 | transfer_list_set_next(&instance->transfers_control_slow,
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| 387 | &instance->transfers_control_full);
|
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| 388 | transfer_list_set_next(&instance->transfers_interrupt,
|
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| 389 | &instance->transfers_control_slow);
|
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| 390 |
|
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[e247d83] | 391 | /*FSBR, This feature is not needed (adds no benefit) and is supposedly
|
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| 392 | * buggy on certain hw, enable at your own risk. */
|
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[9351353] | 393 | #ifdef FSBR
|
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| 394 | transfer_list_set_next(&instance->transfers_bulk_full,
|
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[302a4b6] | 395 | &instance->transfers_control_full);
|
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[9351353] | 396 | #endif
|
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| 397 |
|
---|
| 398 | /* Assign pointers to be used during scheduling */
|
---|
| 399 | instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
|
---|
| 400 | &instance->transfers_interrupt;
|
---|
| 401 | instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
|
---|
| 402 | &instance->transfers_interrupt;
|
---|
| 403 | instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
|
---|
| 404 | &instance->transfers_control_full;
|
---|
| 405 | instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
|
---|
| 406 | &instance->transfers_control_slow;
|
---|
| 407 | instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
|
---|
| 408 | &instance->transfers_bulk_full;
|
---|
| 409 |
|
---|
| 410 | return EOK;
|
---|
| 411 | }
|
---|
[76fbd9a] | 412 |
|
---|
[9f6cb910] | 413 | int uhci_hc_status(hcd_t *hcd, uint32_t *status)
|
---|
[e26a9d95] | 414 | {
|
---|
| 415 | assert(hcd);
|
---|
| 416 | assert(status);
|
---|
[b5f813c] | 417 | hc_t *instance = hcd_get_driver_data(hcd);
|
---|
[e26a9d95] | 418 | assert(instance);
|
---|
| 419 |
|
---|
| 420 | *status = 0;
|
---|
| 421 | if (instance->registers) {
|
---|
| 422 | uint16_t s = pio_read_16(&instance->registers->usbsts);
|
---|
| 423 | pio_write_16(&instance->registers->usbsts, s);
|
---|
| 424 | *status = s;
|
---|
| 425 | }
|
---|
| 426 | return EOK;
|
---|
| 427 | }
|
---|
| 428 |
|
---|
[17ceb72] | 429 | /** Schedule batch for execution.
|
---|
[9351353] | 430 | *
|
---|
| 431 | * @param[in] instance UHCI structure to use.
|
---|
| 432 | * @param[in] batch Transfer batch to schedule.
|
---|
| 433 | * @return Error code
|
---|
[17ceb72] | 434 | *
|
---|
| 435 | * Checks for bandwidth availability and appends the batch to the proper queue.
|
---|
[9351353] | 436 | */
|
---|
[9f6cb910] | 437 | int uhci_hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
|
---|
[9351353] | 438 | {
|
---|
[3afb758] | 439 | assert(hcd);
|
---|
[b5f813c] | 440 | hc_t *instance = hcd_get_driver_data(hcd);
|
---|
[9351353] | 441 | assert(instance);
|
---|
| 442 | assert(batch);
|
---|
[c95c00e] | 443 |
|
---|
[3848fec] | 444 | if (batch->ep->address == uhci_rh_get_address(&instance->rh))
|
---|
| 445 | return uhci_rh_schedule(&instance->rh, batch);
|
---|
[c95c00e] | 446 |
|
---|
[b991d37] | 447 | uhci_transfer_batch_t *uhci_batch = uhci_transfer_batch_get(batch);
|
---|
| 448 | if (!uhci_batch) {
|
---|
| 449 | usb_log_error("Failed to create UHCI transfer structures.\n");
|
---|
| 450 | return ENOMEM;
|
---|
[23b0fe8] | 451 | }
|
---|
[9351353] | 452 |
|
---|
| 453 | transfer_list_t *list =
|
---|
[d017cea] | 454 | instance->transfers[batch->ep->speed][batch->ep->transfer_type];
|
---|
[9351353] | 455 | assert(list);
|
---|
[b991d37] | 456 | transfer_list_add_batch(list, uhci_batch);
|
---|
[9351353] | 457 |
|
---|
| 458 | return EOK;
|
---|
| 459 | }
|
---|
[76fbd9a] | 460 |
|
---|
[9351353] | 461 | /** Debug function, checks consistency of memory structures.
|
---|
| 462 | *
|
---|
| 463 | * @param[in] arg UHCI structure to use.
|
---|
[17ceb72] | 464 | * @return EOK (should never return)
|
---|
[9351353] | 465 | */
|
---|
[c01cd32] | 466 | int hc_debug_checker(void *arg)
|
---|
[9351353] | 467 | {
|
---|
[6f122df] | 468 | hc_t *instance = arg;
|
---|
[9351353] | 469 | assert(instance);
|
---|
| 470 |
|
---|
| 471 | #define QH(queue) \
|
---|
| 472 | instance->transfers_##queue.queue_head
|
---|
| 473 |
|
---|
| 474 | while (1) {
|
---|
| 475 | const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
|
---|
| 476 | const uint16_t sts = pio_read_16(&instance->registers->usbsts);
|
---|
| 477 | const uint16_t intr =
|
---|
| 478 | pio_read_16(&instance->registers->usbintr);
|
---|
| 479 |
|
---|
| 480 | if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
|
---|
| 481 | usb_log_debug2("Command: %X Status: %X Intr: %x\n",
|
---|
| 482 | cmd, sts, intr);
|
---|
| 483 | }
|
---|
| 484 |
|
---|
[e247d83] | 485 | const uintptr_t frame_list =
|
---|
[9351353] | 486 | pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
|
---|
| 487 | if (frame_list != addr_to_phys(instance->frame_list)) {
|
---|
| 488 | usb_log_debug("Framelist address: %p vs. %p.\n",
|
---|
[4125b7d] | 489 | (void *) frame_list,
|
---|
| 490 | (void *) addr_to_phys(instance->frame_list));
|
---|
[9351353] | 491 | }
|
---|
| 492 |
|
---|
| 493 | int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
|
---|
| 494 |
|
---|
| 495 | uintptr_t expected_pa = instance->frame_list[frnum]
|
---|
| 496 | & LINK_POINTER_ADDRESS_MASK;
|
---|
| 497 | uintptr_t real_pa = addr_to_phys(QH(interrupt));
|
---|
| 498 | if (expected_pa != real_pa) {
|
---|
[4125b7d] | 499 | usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
|
---|
| 500 | (void *) expected_pa, frnum, (void *) real_pa);
|
---|
[9351353] | 501 | }
|
---|
| 502 |
|
---|
| 503 | expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
|
---|
| 504 | real_pa = addr_to_phys(QH(control_slow));
|
---|
| 505 | if (expected_pa != real_pa) {
|
---|
| 506 | usb_log_debug("Control Slow QH: %p vs. %p.\n",
|
---|
[4125b7d] | 507 | (void *) expected_pa, (void *) real_pa);
|
---|
[9351353] | 508 | }
|
---|
| 509 |
|
---|
| 510 | expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
|
---|
| 511 | real_pa = addr_to_phys(QH(control_full));
|
---|
| 512 | if (expected_pa != real_pa) {
|
---|
| 513 | usb_log_debug("Control Full QH: %p vs. %p.\n",
|
---|
[4125b7d] | 514 | (void *) expected_pa, (void *) real_pa);
|
---|
[9351353] | 515 | }
|
---|
| 516 |
|
---|
| 517 | expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
|
---|
| 518 | real_pa = addr_to_phys(QH(bulk_full));
|
---|
| 519 | if (expected_pa != real_pa ) {
|
---|
| 520 | usb_log_debug("Bulk QH: %p vs. %p.\n",
|
---|
[4125b7d] | 521 | (void *) expected_pa, (void *) real_pa);
|
---|
[9351353] | 522 | }
|
---|
| 523 | async_usleep(UHCI_DEBUGER_TIMEOUT);
|
---|
| 524 | }
|
---|
| 525 | return EOK;
|
---|
| 526 | #undef QH
|
---|
| 527 | }
|
---|
| 528 | /**
|
---|
| 529 | * @}
|
---|
| 530 | */
|
---|