source: mainline/uspace/drv/bus/usb/uhci/hc.c@ 30e8ab4

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 30e8ab4 was 9348862, checked in by Jan Vesely <jano.vesely@…>, 12 years ago

usb: Move HC driver implementation functions to a separate structure.

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File size: 16.2 KB
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[9351353]1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
[17ceb72]28/** @addtogroup drvusbuhcihc
[9351353]29 * @{
30 */
31/** @file
[17ceb72]32 * @brief UHCI Host controller driver routines
[9351353]33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
[1ae74c6]37#include <ddi.h>
[9351353]38
39#include <usb/debug.h>
40#include <usb/usb.h>
41
[c01cd32]42#include "hc.h"
[07f49ae]43#include "uhci_batch.h"
[9351353]44
[8986412]45#define UHCI_INTR_ALLOW_INTERRUPTS \
[af81980]46 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
[8986412]47#define UHCI_STATUS_USED_INTERRUPTS \
48 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
[af81980]49
[d57122c]50static const irq_pio_range_t uhci_irq_pio_ranges[] = {
51 {
[8486c07]52 .base = 0,
[d57122c]53 .size = sizeof(uhci_regs_t)
54 }
55};
[5fe0a697]56
[d57122c]57static const irq_cmd_t uhci_irq_commands[] = {
[8486c07]58 {
59 .cmd = CMD_PIO_READ_16,
60 .dstarg = 1,
61 .addr = NULL
62 },
63 {
64 .cmd = CMD_AND,
65 .srcarg = 1,
66 .dstarg = 2,
67 .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS
68 },
69 {
70 .cmd = CMD_PREDICATE,
71 .srcarg = 2,
72 .value = 2
73 },
74 {
75 .cmd = CMD_PIO_WRITE_A_16,
76 .srcarg = 1,
77 .addr = NULL
78 },
79 {
80 .cmd = CMD_ACCEPT
81 }
[dfe4955]82};
[302a4b6]83
[3afb758]84static void hc_init_hw(const hc_t *instance);
[c01cd32]85static int hc_init_mem_structures(hc_t *instance);
[3afb758]86static int hc_init_transfer_lists(hc_t *instance);
[9351353]87
[c01cd32]88static int hc_interrupt_emulator(void *arg);
89static int hc_debug_checker(void *arg);
[dfe4955]90
[76fbd9a]91
[d57122c]92/** Get number of PIO ranges used in IRQ code.
93 * @return Number of ranges.
94 */
95size_t hc_irq_pio_range_count(void)
96{
97 return sizeof(uhci_irq_pio_ranges) / sizeof(irq_pio_range_t);
98}
[76fbd9a]99
[dfe4955]100/** Get number of commands used in IRQ code.
101 * @return Number of commands.
102 */
103size_t hc_irq_cmd_count(void)
104{
105 return sizeof(uhci_irq_commands) / sizeof(irq_cmd_t);
106}
[76fbd9a]107
[d57122c]108/** Generate IRQ code.
109 * @param[out] ranges PIO ranges buffer.
110 * @param[in] ranges_size Size of the ranges buffer (bytes).
111 * @param[out] cmds Commands buffer.
112 * @param[in] cmds_size Size of the commands buffer (bytes).
[7de1988c]113 * @param[in] regs Device's register range.
[dfe4955]114 *
115 * @return Error code.
116 */
[d57122c]117int
118hc_get_irq_code(irq_pio_range_t ranges[], size_t ranges_size, irq_cmd_t cmds[],
[7de1988c]119 size_t cmds_size, addr_range_t *regs)
[dfe4955]120{
[d57122c]121 if ((ranges_size < sizeof(uhci_irq_pio_ranges)) ||
122 (cmds_size < sizeof(uhci_irq_commands)) ||
[7de1988c]123 (RNGSZ(*regs) < sizeof(uhci_regs_t)))
[dfe4955]124 return EOVERFLOW;
125
[d57122c]126 memcpy(ranges, uhci_irq_pio_ranges, sizeof(uhci_irq_pio_ranges));
[7de1988c]127 ranges[0].base = RNGABS(*regs);
[dfe4955]128
129 memcpy(cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
[7de1988c]130 uhci_regs_t *registers = (uhci_regs_t *) RNGABSPTR(*regs);
[c95c00e]131 cmds[0].addr = (void*)&registers->usbsts;
132 cmds[3].addr = (void*)&registers->usbsts;
[dfe4955]133
134 return EOK;
135}
[76fbd9a]136
[c53007f]137/** Register interrupt handler.
138 *
139 * @param[in] device Host controller DDF device
[7de1988c]140 * @param[in] regs Register range
[c53007f]141 * @param[in] irq Interrupt number
142 * @paran[in] handler Interrupt handler
143 *
144 * @return EOK on success or negative error code
145 */
[7de1988c]146int hc_register_irq_handler(ddf_dev_t *device, addr_range_t *regs, int irq,
147 interrupt_handler_t handler)
[c53007f]148{
[3f03199]149 assert(device);
150 irq_pio_range_t irq_ranges[hc_irq_pio_range_count()];
151 irq_cmd_t irq_cmds[hc_irq_cmd_count()];
152
153 int ret = hc_get_irq_code(irq_ranges, sizeof(irq_ranges), irq_cmds,
[7de1988c]154 sizeof(irq_cmds), regs);
[3f03199]155 if (ret != EOK) {
[c53007f]156 usb_log_error("Failed to generate IRQ commands: %s.\n",
[3f03199]157 str_error(ret));
158 return ret;
[c53007f]159 }
160
161 irq_code_t irq_code = {
[3f03199]162 .rangecount = hc_irq_pio_range_count(),
[c53007f]163 .ranges = irq_ranges,
[3f03199]164 .cmdcount = hc_irq_cmd_count(),
[c53007f]165 .cmds = irq_cmds
166 };
167
168 /* Register handler to avoid interrupt lockup */
[3f03199]169 ret = register_interrupt_handler(device, irq, handler, &irq_code);
170 if (ret != EOK) {
171 usb_log_error("Failed to register interrupt handler: %s.\n",
172 str_error(ret));
173 return ret;
174 }
[c53007f]175
176 return EOK;
177}
178
[3afb758]179/** Take action based on the interrupt cause.
180 *
181 * @param[in] instance UHCI structure to use.
182 * @param[in] status Value of the status register at the time of interrupt.
183 *
184 * Interrupt might indicate:
185 * - transaction completed, either by triggering IOC, SPD, or an error
186 * - some kind of device error
187 * - resume from suspend state (not implemented)
188 */
189void hc_interrupt(hc_t *instance, uint16_t status)
190{
191 assert(instance);
192 /* Lower 2 bits are transaction error and transaction complete */
193 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
194 LIST_INITIALIZE(done);
195 transfer_list_remove_finished(
196 &instance->transfers_interrupt, &done);
197 transfer_list_remove_finished(
198 &instance->transfers_control_slow, &done);
199 transfer_list_remove_finished(
200 &instance->transfers_control_full, &done);
201 transfer_list_remove_finished(
202 &instance->transfers_bulk_full, &done);
203
204 while (!list_empty(&done)) {
205 link_t *item = list_first(&done);
206 list_remove(item);
[b991d37]207 uhci_transfer_batch_t *batch =
208 uhci_transfer_batch_from_link(item);
[6bba41d]209 uhci_transfer_batch_finish_dispose(batch);
[3afb758]210 }
211 }
212 /* Resume interrupts are not supported */
213 if (status & UHCI_STATUS_RESUME) {
214 usb_log_error("Resume interrupt!\n");
215 }
216
217 /* Bits 4 and 5 indicate hc error */
218 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
219 usb_log_error("UHCI hardware failure!.\n");
220 ++instance->hw_failures;
221 transfer_list_abort_all(&instance->transfers_interrupt);
222 transfer_list_abort_all(&instance->transfers_control_slow);
223 transfer_list_abort_all(&instance->transfers_control_full);
224 transfer_list_abort_all(&instance->transfers_bulk_full);
225
226 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
227 /* reinitialize hw, this triggers virtual disconnect*/
228 hc_init_hw(instance);
229 } else {
230 usb_log_fatal("Too many UHCI hardware failures!.\n");
231 hc_fini(instance);
232 }
233 }
234}
[76fbd9a]235
[02cacce]236/** Initialize UHCI hc driver structure
[9351353]237 *
238 * @param[in] instance Memory place to initialize.
[7de1988c]239 * @param[in] regs Range of device's I/O control registers.
[23f40280]240 * @param[in] interrupts True if hw interrupts should be used.
[9351353]241 * @return Error code.
242 * @note Should be called only once on any structure.
[17ceb72]243 *
244 * Initializes memory structures, starts up hw, and launches debugger and
245 * interrupt fibrils.
[9351353]246 */
[7de1988c]247int hc_init(hc_t *instance, addr_range_t *regs, bool interrupts)
[9351353]248{
[3f03199]249 assert(instance);
250 assert(regs);
[7de1988c]251 assert(regs->size >= sizeof(uhci_regs_t));
[9351353]252
[ff34e5a]253 instance->hw_interrupts = interrupts;
[fcc525d]254 instance->hw_failures = 0;
255
[9351353]256 /* allow access to hc control registers */
[dfe4955]257 uhci_regs_t *io;
[3f03199]258 int ret = pio_enable_range(regs, (void **) &io);
[e0d8b740]259 if (ret != EOK) {
260 usb_log_error("Failed to gain access to registers at %p: %s.\n",
261 io, str_error(ret));
262 return ret;
263 }
[9351353]264 instance->registers = io;
[e0d8b740]265
[26858040]266 usb_log_debug(
[7de1988c]267 "Device registers at %p (%zuB) accessible.\n", io, regs->size);
[3afb758]268
[7265558]269 ret = hc_init_mem_structures(instance);
[e0d8b740]270 if (ret != EOK) {
271 usb_log_error("Failed to init UHCI memory structures: %s.\n",
272 str_error(ret));
273 // TODO: we should disable pio here
274 return ret;
275 }
[7265558]276
[c01cd32]277 hc_init_hw(instance);
[ff34e5a]278 if (!interrupts) {
[ea993d18]279 instance->interrupt_emulator =
[c01cd32]280 fibril_create(hc_interrupt_emulator, instance);
[ea993d18]281 fibril_add_ready(instance->interrupt_emulator);
[ff34e5a]282 }
[ea993d18]283 (void)hc_debug_checker;
[9351353]284
[e646c61]285 uhci_rh_init(&instance->rh, instance->registers->ports, "uhci");
[c95c00e]286
[9351353]287 return EOK;
288}
[76fbd9a]289
[17ceb72]290/** Initialize UHCI hc hw resources.
[9351353]291 *
292 * @param[in] instance UHCI structure to use.
[17ceb72]293 * For magic values see UHCI Design Guide
[9351353]294 */
[3afb758]295void hc_init_hw(const hc_t *instance)
[9351353]296{
297 assert(instance);
[dfe4955]298 uhci_regs_t *registers = instance->registers;
[9351353]299
300 /* Reset everything, who knows what touched it before us */
301 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
[26858040]302 async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
[9351353]303 pio_write_16(&registers->usbcmd, 0);
304
[26858040]305 /* Reset hc, all states and counters. Hope that hw is not broken */
[9351353]306 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
307 do { async_usleep(10); }
308 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
309
[eb2a48a]310 /* Set frame to exactly 1ms */
311 pio_write_8(&registers->sofmod, 64);
312
313 /* Set frame list pointer */
[9351353]314 const uint32_t pa = addr_to_phys(instance->frame_list);
315 pio_write_32(&registers->flbaseadd, pa);
316
[ff34e5a]317 if (instance->hw_interrupts) {
318 /* Enable all interrupts, but resume interrupt */
319 pio_write_16(&instance->registers->usbintr,
[8986412]320 UHCI_INTR_ALLOW_INTERRUPTS);
[ff34e5a]321 }
[9351353]322
[26858040]323 const uint16_t cmd = pio_read_16(&registers->usbcmd);
324 if (cmd != 0)
325 usb_log_warning("Previous command value: %x.\n", cmd);
[9351353]326
327 /* Start the hc with large(64B) packet FSBR */
328 pio_write_16(&registers->usbcmd,
329 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
330}
[76fbd9a]331
[17ceb72]332/** Initialize UHCI hc memory structures.
[9351353]333 *
334 * @param[in] instance UHCI structure to use.
335 * @return Error code
336 * @note Should be called only once on any structure.
[17ceb72]337 *
338 * Structures:
339 * - transfer lists (queue heads need to be accessible by the hw)
340 * - frame list page (needs to be one UHCI hw accessible 4K page)
[9351353]341 */
[c01cd32]342int hc_init_mem_structures(hc_t *instance)
[9351353]343{
344 assert(instance);
345
[3afb758]346 /* Init USB frame list page */
[9351353]347 instance->frame_list = get_page();
[26858040]348 if (!instance->frame_list) {
349 return ENOMEM;
350 }
[001b152]351 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
[9351353]352
[3afb758]353 /* Init transfer lists */
354 int ret = hc_init_transfer_lists(instance);
355 if (ret != EOK) {
356 usb_log_error("Failed to initialize transfer lists.\n");
357 return_page(instance->frame_list);
358 return ENOMEM;
359 }
360 usb_log_debug("Initialized transfer lists.\n");
361
362
[9351353]363 /* Set all frames to point to the first queue head */
[302a4b6]364 const uint32_t queue = LINK_POINTER_QH(
365 addr_to_phys(instance->transfers_interrupt.queue_head));
[75f9dcd]366
367 for (unsigned i = 0; i < UHCI_FRAME_LIST_COUNT; ++i) {
[9351353]368 instance->frame_list[i] = queue;
369 }
370
371 return EOK;
372}
[76fbd9a]373
[17ceb72]374/** Initialize UHCI hc transfer lists.
[9351353]375 *
376 * @param[in] instance UHCI structure to use.
377 * @return Error code
378 * @note Should be called only once on any structure.
[17ceb72]379 *
380 * Initializes transfer lists and sets them in one chain to support proper
381 * USB scheduling. Sets pointer table for quick access.
[9351353]382 */
[c01cd32]383int hc_init_transfer_lists(hc_t *instance)
[9351353]384{
385 assert(instance);
[27205841]386#define SETUP_TRANSFER_LIST(type, name) \
387do { \
388 int ret = transfer_list_init(&instance->transfers_##type, name); \
[9351353]389 if (ret != EOK) { \
[26858040]390 usb_log_error("Failed to setup %s transfer list: %s.\n", \
391 name, str_error(ret)); \
[9351353]392 transfer_list_fini(&instance->transfers_bulk_full); \
393 transfer_list_fini(&instance->transfers_control_full); \
394 transfer_list_fini(&instance->transfers_control_slow); \
395 transfer_list_fini(&instance->transfers_interrupt); \
396 return ret; \
[27205841]397 } \
398} while (0)
399
400 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
401 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
402 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
403 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
404#undef SETUP_TRANSFER_LIST
405 /* Connect lists into one schedule */
[9351353]406 transfer_list_set_next(&instance->transfers_control_full,
407 &instance->transfers_bulk_full);
408 transfer_list_set_next(&instance->transfers_control_slow,
409 &instance->transfers_control_full);
410 transfer_list_set_next(&instance->transfers_interrupt,
411 &instance->transfers_control_slow);
412
[e247d83]413 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
414 * buggy on certain hw, enable at your own risk. */
[9351353]415#ifdef FSBR
416 transfer_list_set_next(&instance->transfers_bulk_full,
[302a4b6]417 &instance->transfers_control_full);
[9351353]418#endif
419
420 /* Assign pointers to be used during scheduling */
421 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
422 &instance->transfers_interrupt;
423 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
424 &instance->transfers_interrupt;
425 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
426 &instance->transfers_control_full;
427 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
428 &instance->transfers_control_slow;
429 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
430 &instance->transfers_bulk_full;
431
432 return EOK;
433}
[76fbd9a]434
[17ceb72]435/** Schedule batch for execution.
[9351353]436 *
437 * @param[in] instance UHCI structure to use.
438 * @param[in] batch Transfer batch to schedule.
439 * @return Error code
[17ceb72]440 *
441 * Checks for bandwidth availability and appends the batch to the proper queue.
[9351353]442 */
[3afb758]443int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
[9351353]444{
[3afb758]445 assert(hcd);
[9348862]446 hc_t *instance = hcd->driver.data;
[9351353]447 assert(instance);
448 assert(batch);
[c95c00e]449
[3848fec]450 if (batch->ep->address == uhci_rh_get_address(&instance->rh))
451 return uhci_rh_schedule(&instance->rh, batch);
[c95c00e]452
[b991d37]453 uhci_transfer_batch_t *uhci_batch = uhci_transfer_batch_get(batch);
454 if (!uhci_batch) {
455 usb_log_error("Failed to create UHCI transfer structures.\n");
456 return ENOMEM;
[23b0fe8]457 }
[9351353]458
459 transfer_list_t *list =
[d017cea]460 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
[9351353]461 assert(list);
[b991d37]462 transfer_list_add_batch(list, uhci_batch);
[9351353]463
464 return EOK;
465}
[76fbd9a]466
[9351353]467/** Polling function, emulates interrupts.
468 *
[17ceb72]469 * @param[in] arg UHCI hc structure to use.
470 * @return EOK (should never return)
[9351353]471 */
[c01cd32]472int hc_interrupt_emulator(void* arg)
[9351353]473{
474 usb_log_debug("Started interrupt emulator.\n");
[6f122df]475 hc_t *instance = arg;
[9351353]476 assert(instance);
477
478 while (1) {
[6f122df]479 /* Read and clear status register */
[9351353]480 uint16_t status = pio_read_16(&instance->registers->usbsts);
[27205841]481 pio_write_16(&instance->registers->usbsts, status);
[9351353]482 if (status != 0)
483 usb_log_debug2("UHCI status: %x.\n", status);
[c01cd32]484 hc_interrupt(instance, status);
[27205841]485 async_usleep(UHCI_INT_EMULATOR_TIMEOUT);
[9351353]486 }
487 return EOK;
488}
[76fbd9a]489
[9351353]490/** Debug function, checks consistency of memory structures.
491 *
492 * @param[in] arg UHCI structure to use.
[17ceb72]493 * @return EOK (should never return)
[9351353]494 */
[c01cd32]495int hc_debug_checker(void *arg)
[9351353]496{
[6f122df]497 hc_t *instance = arg;
[9351353]498 assert(instance);
499
500#define QH(queue) \
501 instance->transfers_##queue.queue_head
502
503 while (1) {
504 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
505 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
506 const uint16_t intr =
507 pio_read_16(&instance->registers->usbintr);
508
509 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
510 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
511 cmd, sts, intr);
512 }
513
[e247d83]514 const uintptr_t frame_list =
[9351353]515 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
516 if (frame_list != addr_to_phys(instance->frame_list)) {
517 usb_log_debug("Framelist address: %p vs. %p.\n",
[4125b7d]518 (void *) frame_list,
519 (void *) addr_to_phys(instance->frame_list));
[9351353]520 }
521
522 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
523
524 uintptr_t expected_pa = instance->frame_list[frnum]
525 & LINK_POINTER_ADDRESS_MASK;
526 uintptr_t real_pa = addr_to_phys(QH(interrupt));
527 if (expected_pa != real_pa) {
[4125b7d]528 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
529 (void *) expected_pa, frnum, (void *) real_pa);
[9351353]530 }
531
532 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
533 real_pa = addr_to_phys(QH(control_slow));
534 if (expected_pa != real_pa) {
535 usb_log_debug("Control Slow QH: %p vs. %p.\n",
[4125b7d]536 (void *) expected_pa, (void *) real_pa);
[9351353]537 }
538
539 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
540 real_pa = addr_to_phys(QH(control_full));
541 if (expected_pa != real_pa) {
542 usb_log_debug("Control Full QH: %p vs. %p.\n",
[4125b7d]543 (void *) expected_pa, (void *) real_pa);
[9351353]544 }
545
546 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
547 real_pa = addr_to_phys(QH(bulk_full));
548 if (expected_pa != real_pa ) {
549 usb_log_debug("Bulk QH: %p vs. %p.\n",
[4125b7d]550 (void *) expected_pa, (void *) real_pa);
[9351353]551 }
552 async_usleep(UHCI_DEBUGER_TIMEOUT);
553 }
554 return EOK;
555#undef QH
556}
557/**
558 * @}
559 */
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