source: mainline/uspace/drv/bus/usb/ohci/ohci_regs.h@ f8dfb40

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since f8dfb40 was 5d36062, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

OHCI: Replace volatile uint with ioport type.

  • Property mode set to 100644
File size: 9.4 KB
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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbohcihc
29 * @{
30 */
31/** @file
32 * @brief OHCI host controller register structure
33 */
34#ifndef DRV_OHCI_OHCI_REGS_H
35#define DRV_OHCI_OHCI_REGS_H
36#include <sys/types.h>
37
38#define LEGACY_REGS_OFFSET 0x100
39
40/** OHCI memory mapped registers structure */
41typedef struct ohci_regs {
42 const ioport32_t revision;
43#define R_REVISION_MASK (0x3f)
44#define R_REVISION_SHIFT (0)
45#define R_LEGACY_FLAG (0x80)
46
47 ioport32_t control;
48#define C_CBSR_MASK (0x3) /* Control-bulk service ratio */
49#define C_CBSR_1_1 (0x0)
50#define C_CBSR_1_2 (0x1)
51#define C_CBSR_1_3 (0x2)
52#define C_CBSR_1_4 (0x3)
53#define C_CBSR_SHIFT (0)
54
55#define C_PLE (1 << 2) /* Periodic list enable */
56#define C_IE (1 << 3) /* Isochronous enable */
57#define C_CLE (1 << 4) /* Control list enable */
58#define C_BLE (1 << 5) /* Bulk list enable */
59
60#define C_HCFS_MASK (0x3) /* Host controller functional state */
61#define C_HCFS_RESET (0x0)
62#define C_HCFS_RESUME (0x1)
63#define C_HCFS_OPERATIONAL (0x2)
64#define C_HCFS_SUSPEND (0x3)
65#define C_HCFS_SHIFT (6)
66
67#define C_HCFS_GET(reg) \
68 ((reg >> C_HCFS_SHIFT) & C_HCFS_MASK)
69#define C_HCFS_SET(reg, hcfs_state) \
70do { \
71 reg = (reg & ~(C_HCFS_MASK << C_HCFS_SHIFT)) \
72 | ((hcfs_state & C_HCFS_MASK) << C_HCFS_SHIFT); \
73} while (0)
74
75
76#define C_IR (1 << 8) /* Interrupt routing, make sure it's 0 */
77#define C_RWC (1 << 9) /* Remote wakeup connected, host specific */
78#define C_RWE (1 << 10) /* Remote wakeup enable */
79
80 ioport32_t command_status;
81#define CS_HCR (1 << 0) /* Host controller reset */
82#define CS_CLF (1 << 1) /* Control list filled */
83#define CS_BLF (1 << 2) /* Bulk list filled */
84#define CS_OCR (1 << 3) /* Ownership change request */
85#define CS_SOC_MASK (0x3) /* Scheduling overrun count */
86#define CS_SOC_SHIFT (16)
87
88 /** Interupt enable/disable/status,
89 * reads give the same value,
90 * writing causes enable/disable,
91 * status is write-clean (writing 1 clears the bit*/
92 ioport32_t interrupt_status;
93 ioport32_t interrupt_enable;
94 ioport32_t interrupt_disable;
95#define I_SO (1 << 0) /* Scheduling overrun */
96#define I_WDH (1 << 1) /* Done head write-back */
97#define I_SF (1 << 2) /* Start of frame */
98#define I_RD (1 << 3) /* Resume detect */
99#define I_UE (1 << 4) /* Unrecoverable error */
100#define I_FNO (1 << 5) /* Frame number overflow */
101#define I_RHSC (1 << 6) /* Root hub status change */
102#define I_OC (1 << 30) /* Ownership change */
103#define I_MI (1 << 31) /* Master interrupt (all/any interrupts) */
104
105 /** HCCA pointer (see hw_struct hcca.h) */
106 ioport32_t hcca;
107#define HCCA_PTR_MASK 0xffffff00 /* HCCA is 256B aligned */
108
109 /** Currently executed periodic endpoint */
110 const ioport32_t periodic_current;
111
112 /** The first control endpoint */
113 ioport32_t control_head;
114
115 /** Currently executed control endpoint */
116 ioport32_t control_current;
117
118 /** The first bulk endpoint */
119 ioport32_t bulk_head;
120
121 /** Currently executed bulk endpoint */
122 ioport32_t bulk_current;
123
124 /** Done TD list, this value is periodically written to HCCA */
125 const ioport32_t done_head;
126
127 /** Frame time and max packet size for all transfers */
128 ioport32_t fm_interval;
129#define FMI_FI_MASK (0x3fff) /* Frame interval in bit times (should be 11999)*/
130#define FMI_FI_SHIFT (0)
131#define FMI_FSMPS_MASK (0x7fff) /* Full speed max packet size */
132#define FMI_FSMPS_SHIFT (16)
133#define FMI_TOGGLE_FLAG (1 << 31)
134
135 /** Bit times remaining in current frame */
136 const ioport32_t fm_remaining;
137#define FMR_FR_MASK FMI_FI_MASK
138#define FMR_FR_SHIFT FMI_FI_SHIFT
139#define FMR_TOGGLE_FLAG FMI_TOGGLE_FLAG
140
141 /** Frame number */
142 const ioport32_t fm_number;
143#define FMN_NUMBER_MASK (0xffff)
144
145 /** Remaining bit time in frame to start periodic transfers */
146 ioport32_t periodic_start;
147#define PS_PS_MASK (0x3fff) /* bit time when periodic get priority (0x3e67) */
148
149 /** Threshold for starting LS transaction */
150 ioport32_t ls_threshold;
151#define LST_LST_MASK (0x7fff)
152
153 /** The first root hub control register */
154 ioport32_t rh_desc_a;
155#define RHDA_NDS_MASK (0xff) /* Number of downstream ports, max 15 */
156#define RHDA_NDS_SHIFT (0)
157#define RHDA_PSM_FLAG (1 << 8) /* Power switching mode: 0-global, 1-per port*/
158#define RHDA_NPS_FLAG (1 << 9) /* No power switch: 1-power on, 0-use PSM*/
159#define RHDA_DT_FLAG (1 << 10) /* 1-Compound device, must be 0 */
160#define RHDA_OCPM_FLAG (1 << 11) /* Over-current mode: 0-global, 1-per port */
161#define RHDA_NOCP_FLAG (1 << 12) /* OC control: 0-use OCPM, 1-OC off */
162#define RHDA_POTPGT_MASK (0xff) /* Power on to power good time */
163#define RHDA_POTPGT_SHIFT (24)
164
165 /** The other root hub control register */
166 ioport32_t rh_desc_b;
167#define RHDB_DR_MASK (0xffff) /* Device removable mask */
168#define RHDB_DR_SHIFT (0)
169#define RHDB_PCC_MASK (0xffff) /* Power control mask */
170#define RHDB_PCC_SHIFT (16)
171
172/* Port device removable status */
173#define RHDB_DR_FLAG(port) (((1 << port) & RHDB_DR_MASK) << RHDB_DR_SHIFT)
174/* Port power control status: 1-per port power control, 0-global power switch */
175#define RHDB_PPC_FLAG(port) (((1 << port) & RHDB_DR_MASK) << RHDB_DR_SHIFT)
176
177 /** Root hub status register */
178 ioport32_t rh_status;
179#define RHS_LPS_FLAG (1 << 0)/* read: 0,
180 * write: 0-no effect,
181 * 1-turn off port power for ports
182 * specified in PPCM(RHDB), or all ports,
183 * if power is set globally */
184#define RHS_CLEAR_GLOBAL_POWER RHS_LPS_FLAG /* synonym for the above */
185#define RHS_OCI_FLAG (1 << 1)/* Over-current indicator, if per-port: 0 */
186#define RHS_DRWE_FLAG (1 << 15)/* read: 0-connect status change does not wake HC
187 * 1-connect status change wakes HC
188 * write: 1-set DRWE, 0-no effect */
189#define RHS_SET_DRWE RHS_DRWE_FLAG
190#define RHS_LPSC_FLAG (1 << 16)/* read: 0,
191 * write: 0-no effect
192 * 1-turn on port power for ports
193 * specified in PPCM(RHDB), or all ports,
194 * if power is set globally */
195#define RHS_SET_GLOBAL_POWER RHS_LPSC_FLAG /* synonym for the above */
196#define RHS_OCIC_FLAG (1 << 17)/* Over-current indicator change */
197#define RHS_CLEAR_DRWE (1 << 31)
198
199 /** Root hub per port status */
200 ioport32_t rh_port_status[];
201#define RHPS_CCS_FLAG (1 << 0) /* r: current connect status,
202 * w: 1-clear port enable, 0-nothing */
203#define RHPS_CLEAR_PORT_ENABLE RHPS_CCS_FLAG
204#define RHPS_PES_FLAG (1 << 1) /* r: port enable status
205 * w: 1-set port enable, 0-nothing */
206#define RHPS_SET_PORT_ENABLE RHPS_PES_FLAG
207#define RHPS_PSS_FLAG (1 << 2) /* r: port suspend status
208 * w: 1-set port suspend, 0-nothing */
209#define RHPS_SET_PORT_SUSPEND RHPS_PSS_FLAG
210#define RHPS_POCI_FLAG (1 << 3) /* r: port over-current (if reports are per-port
211 * w: 1-clear port suspend (start resume
212 * if suspened)
213 * 0-nothing */
214#define RHPS_CLEAR_PORT_SUSPEND RHPS_POCI_FLAG
215#define RHPS_PRS_FLAG (1 << 4) /* r: port reset status
216 * w: 1-set port reset, 0-nothing */
217#define RHPS_SET_PORT_RESET RHPS_PRS_FLAG
218#define RHPS_PPS_FLAG (1 << 8) /* r: port power status
219 * w: 1-set port power, 0-nothing */
220#define RHPS_SET_PORT_POWER RHPS_PPS_FLAG
221#define RHPS_LSDA_FLAG (1 << 9) /* r: low speed device attached
222 * w: 1-clear port power, 0-nothing */
223#define RHPS_CLEAR_PORT_POWER RHPS_LSDA_FLAG
224#define RHPS_CSC_FLAG (1 << 16) /* connect status change Write-Clean */
225#define RHPS_PESC_FLAG (1 << 17) /* port enable status change WC */
226#define RHPS_PSSC_FLAG (1 << 18) /* port suspend status change WC */
227#define RHPS_OCIC_FLAG (1 << 19) /* port over-current change WC */
228#define RHPS_PRSC_FLAG (1 << 20) /* port reset status change WC */
229#define RHPS_CHANGE_WC_MASK 0x1f0000
230} __attribute__((packed)) ohci_regs_t;
231#endif
232/**
233 * @}
234 */
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