source: mainline/uspace/drv/bus/usb/ohci/ohci_bus.c@ 6d5d3ae2

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 6d5d3ae2 was c6f82e5, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago

libusbhost: do not try to handle the toggle bit in a generic way

  • Property mode set to 100644
File size: 5.2 KB
RevLine 
[2759c52]1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
[58563585]28
[2759c52]29/** @addtogroup drvusbohci
30 * @{
31 */
32/** @file
33 * @brief OHCI driver
34 */
[0d4b110]35
36#include <assert.h>
37#include <stdlib.h>
[2dbfe44]38#include <usb/host/utils/malloc32.h>
[e6b9182]39#include <usb/host/bandwidth.h>
[0d4b110]40
[e6b9182]41#include "ohci_bus.h"
[5fd9c30]42#include "ohci_batch.h"
[620c710]43#include "hc.h"
[2759c52]44
[c6f82e5]45/**
46 * Callback to reset toggle on ED.
[02cacce]47 *
48 * @param[in] hcd_ep hcd endpoint structure
49 * @param[in] toggle new value of toggle bit
50 */
[c6f82e5]51void ohci_ep_toggle_reset(endpoint_t *ep)
[545764b]52{
[e6b9182]53 ohci_endpoint_t *instance = ohci_endpoint_get(ep);
[545764b]54 assert(instance);
55 assert(instance->ed);
[56257ba]56 ed_toggle_set(instance->ed, 0);
[545764b]57}
[76fbd9a]58
[02cacce]59/** Creates new hcd endpoint representation.
60 */
[9efad54]61static endpoint_t *ohci_endpoint_create(device_t *dev, const usb_endpoint_descriptors_t *desc)
[2759c52]62{
[6832245]63 assert(dev);
[e6b9182]64
[e20eaed]65 ohci_endpoint_t *ohci_ep = malloc(sizeof(ohci_endpoint_t));
66 if (ohci_ep == NULL)
[e6b9182]67 return NULL;
[2759c52]68
[6832245]69 endpoint_init(&ohci_ep->base, dev, desc);
[741bcdeb]70
[e20eaed]71 ohci_ep->ed = malloc32(sizeof(ed_t));
72 if (ohci_ep->ed == NULL) {
73 free(ohci_ep);
[e6b9182]74 return NULL;
[2759c52]75 }
76
[e20eaed]77 ohci_ep->td = malloc32(sizeof(td_t));
78 if (ohci_ep->td == NULL) {
79 free32(ohci_ep->ed);
80 free(ohci_ep);
[e6b9182]81 return NULL;
[2759c52]82 }
83
[d60115a]84 link_initialize(&ohci_ep->eplist_link);
85 link_initialize(&ohci_ep->pending_link);
[5995383c]86 return &ohci_ep->base;
[2759c52]87}
[76fbd9a]88
[48ae3ef]89/** Disposes hcd endpoint structure
90 *
[57e06ef]91 * @param[in] hcd driver using this instance.
92 * @param[in] ep endpoint structure.
[48ae3ef]93 */
[e6b9182]94static void ohci_endpoint_destroy(endpoint_t *ep)
[48ae3ef]95{
96 assert(ep);
97 ohci_endpoint_t *instance = ohci_endpoint_get(ep);
[e6b9182]98
99 free32(instance->ed);
100 free32(instance->td);
101 free(instance);
102}
103
104
[6832245]105static int ohci_register_ep(endpoint_t *ep)
[e6b9182]106{
[6832245]107 bus_t *bus_base = endpoint_get_bus(ep);
[e6b9182]108 ohci_bus_t *bus = (ohci_bus_t *) bus_base;
109 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
110
[6832245]111 const int err = usb2_bus_ops.endpoint_register(ep);
[e6b9182]112 if (err)
113 return err;
114
115 ed_init(ohci_ep->ed, ep, ohci_ep->td);
116 hc_enqueue_endpoint(bus->hc, ep);
117
118 return EOK;
119}
120
[bad4a05]121static void ohci_unregister_ep(endpoint_t *ep)
[e6b9182]122{
[d60115a]123 ohci_bus_t * const bus = (ohci_bus_t *) endpoint_get_bus(ep);
124 hc_t * const hc = bus->hc;
[e6b9182]125 assert(ep);
126
[bad4a05]127 usb2_bus_ops.endpoint_unregister(ep);
[e6b9182]128 hc_dequeue_endpoint(bus->hc, ep);
[d60115a]129
130 ohci_endpoint_t * const ohci_ep = ohci_endpoint_get(ep);
131
132 /*
133 * Now we can be sure the active transfer will not be completed. But first,
134 * make sure that the handling fibril won't use its link in pending list.
135 */
136 fibril_mutex_lock(&hc->guard);
137 if (link_in_use(&ohci_ep->pending_link))
138 /* pending list reference */
139 endpoint_del_ref(ep);
140 list_remove(&ohci_ep->pending_link);
141 fibril_mutex_unlock(&hc->guard);
142
143 /*
144 * Finally, the endpoint shall not be used anywhere else. Finish the
145 * pending batch.
146 */
147 fibril_mutex_lock(&ep->guard);
148 usb_transfer_batch_t * const batch = ep->active_batch;
149 endpoint_deactivate_locked(ep);
150 fibril_mutex_unlock(&ep->guard);
151
152 if (batch) {
153 batch->error = EINTR;
154 batch->transfered_size = 0;
155 usb_transfer_batch_finish(batch);
156 }
[5fd9c30]157}
158
[6832245]159static usb_transfer_batch_t *ohci_create_batch(endpoint_t *ep)
[5fd9c30]160{
161 ohci_transfer_batch_t *batch = ohci_transfer_batch_create(ep);
162 return &batch->base;
163}
[e6b9182]164
[6832245]165static void ohci_destroy_batch(usb_transfer_batch_t *batch)
[5fd9c30]166{
167 ohci_transfer_batch_destroy(ohci_transfer_batch_get(batch));
[e6b9182]168}
169
[6832245]170static const bus_ops_t ohci_bus_ops = {
171 .parent = &usb2_bus_ops,
172
[32fb6bce]173 .interrupt = ohci_hc_interrupt,
174 .status = ohci_hc_status,
175
[6832245]176 .endpoint_destroy = ohci_endpoint_destroy,
177 .endpoint_create = ohci_endpoint_create,
178 .endpoint_register = ohci_register_ep,
179 .endpoint_unregister = ohci_unregister_ep,
180 .endpoint_count_bw = bandwidth_count_usb11,
[c6f82e5]181
[6832245]182 .batch_create = ohci_create_batch,
183 .batch_destroy = ohci_destroy_batch,
[32fb6bce]184 .batch_schedule = ohci_hc_schedule,
[6832245]185};
186
187
[32fb6bce]188int ohci_bus_init(ohci_bus_t *bus, hc_t *hc)
[e6b9182]189{
190 assert(hc);
191 assert(bus);
192
[6832245]193 usb2_bus_t *usb2_bus = (usb2_bus_t *) bus;
194 bus_t *bus_base = (bus_t *) bus;
[e6b9182]195
[32fb6bce]196 usb2_bus_init(usb2_bus, BANDWIDTH_AVAILABLE_USB11);
[6832245]197 bus_base->ops = &ohci_bus_ops;
[5fd9c30]198
[5995383c]199 bus->hc = hc;
200
[e6b9182]201 return EOK;
[48ae3ef]202}
[58563585]203
[2759c52]204/**
205 * @}
206 */
Note: See TracBrowser for help on using the repository browser.