1 | /*
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2 | * Copyright (c) 2011 Jan Vesely
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3 | * Copyright (c) 2018 Ondrej Hlavaty
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4 | * All rights reserved.
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5 | *
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6 | * Redistribution and use in source and binary forms, with or without
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7 | * modification, are permitted provided that the following conditions
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8 | * are met:
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9 | *
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10 | * - Redistributions of source code must retain the above copyright
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11 | * notice, this list of conditions and the following disclaimer.
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12 | * - Redistributions in binary form must reproduce the above copyright
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13 | * notice, this list of conditions and the following disclaimer in the
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14 | * documentation and/or other materials provided with the distribution.
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15 | * - The name of the author may not be used to endorse or promote products
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16 | * derived from this software without specific prior written permission.
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17 | *
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18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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28 | */
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29 |
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30 | /** @addtogroup drvusbohci
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31 | * @{
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32 | */
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33 | /** @file
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34 | * @brief OHCI driver USB transaction structure
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35 | */
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36 |
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37 | #include <assert.h>
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38 | #include <errno.h>
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39 | #include <macros.h>
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40 | #include <mem.h>
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41 | #include <stdbool.h>
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42 |
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43 | #include <usb/usb.h>
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44 | #include <usb/debug.h>
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45 | #include <usb/host/utils/malloc32.h>
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46 |
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47 | #include "ohci_batch.h"
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48 | #include "ohci_bus.h"
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49 |
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50 | static void (*const batch_setup[])(ohci_transfer_batch_t *);
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51 |
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52 | /** Safely destructs ohci_transfer_batch_t structure
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53 | *
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54 | * @param[in] ohci_batch Instance to destroy.
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55 | */
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56 | void ohci_transfer_batch_destroy(ohci_transfer_batch_t *ohci_batch)
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57 | {
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58 | assert(ohci_batch);
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59 | dma_buffer_free(&ohci_batch->ohci_dma_buffer);
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60 | free(ohci_batch);
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61 | }
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62 |
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63 | /** Allocate memory and initialize internal data structure.
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64 | *
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65 | * @param[in] ep Endpoint for which the batch will be created
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66 | * @return Valid pointer if all structures were successfully created,
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67 | * NULL otherwise.
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68 | */
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69 | ohci_transfer_batch_t *ohci_transfer_batch_create(endpoint_t *ep)
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70 | {
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71 | assert(ep);
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72 |
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73 | ohci_transfer_batch_t *ohci_batch =
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74 | calloc(1, sizeof(ohci_transfer_batch_t));
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75 | if (!ohci_batch) {
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76 | usb_log_error("Failed to allocate OHCI batch data.");
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77 | return NULL;
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78 | }
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79 |
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80 | usb_transfer_batch_init(&ohci_batch->base, ep);
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81 |
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82 | return ohci_batch;
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83 | }
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84 |
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85 | /** Prepares a batch to be sent.
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86 | *
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87 | * Determines the number of needed transfer descriptors (TDs).
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88 | * Prepares a transport buffer (that is accessible by the hardware).
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89 | * Initializes parameters needed for the transfer and callback.
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90 | */
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91 | int ohci_transfer_batch_prepare(ohci_transfer_batch_t *ohci_batch)
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92 | {
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93 | assert(ohci_batch);
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94 | usb_transfer_batch_t *usb_batch = &ohci_batch->base;
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95 |
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96 | if (!batch_setup[usb_batch->ep->transfer_type])
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97 | return ENOTSUP;
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98 |
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99 | ohci_batch->td_count = (usb_batch->size + OHCI_TD_MAX_TRANSFER - 1) /
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100 | OHCI_TD_MAX_TRANSFER;
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101 | /* Control transfer need Setup and Status stage */
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102 | if (usb_batch->ep->transfer_type == USB_TRANSFER_CONTROL) {
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103 | ohci_batch->td_count += 2;
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104 | }
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105 |
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106 | /* Alloc one more to NULL terminate */
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107 | ohci_batch->tds = calloc(ohci_batch->td_count + 1, sizeof(td_t *));
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108 | if (!ohci_batch->tds)
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109 | return ENOMEM;
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110 |
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111 | const size_t td_size = ohci_batch->td_count * sizeof(td_t);
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112 | const size_t setup_size = (usb_batch->ep->transfer_type == USB_TRANSFER_CONTROL) ?
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113 | USB_SETUP_PACKET_SIZE :
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114 | 0;
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115 |
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116 | if (dma_buffer_alloc(&ohci_batch->ohci_dma_buffer, td_size + setup_size)) {
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117 | usb_log_error("Failed to allocate OHCI DMA buffer.");
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118 | return ENOMEM;
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119 | }
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120 |
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121 | td_t *tds = ohci_batch->ohci_dma_buffer.virt;
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122 |
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123 | for (size_t i = 0; i < ohci_batch->td_count; i++)
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124 | ohci_batch->tds[i] = &tds[i];
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125 |
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126 | /* Presence of this terminator makes TD initialization easier */
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127 | ohci_batch->tds[ohci_batch->td_count] = NULL;
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128 |
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129 | ohci_batch->setup_buffer = (void *) (&tds[ohci_batch->td_count]);
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130 | memcpy(ohci_batch->setup_buffer, usb_batch->setup.buffer, setup_size);
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131 |
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132 | ohci_batch->data_buffer = usb_batch->dma_buffer.virt;
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133 |
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134 | batch_setup[usb_batch->ep->transfer_type](ohci_batch);
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135 |
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136 | return EOK;
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137 | }
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138 |
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139 | /** Check batch TDs' status.
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140 | *
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141 | * @param[in] ohci_batch Batch structure to use.
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142 | * @return False, if there is an active TD, true otherwise.
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143 | *
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144 | * Walk all TDs (usually there is just one). Stop with false if there is an
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145 | * active TD. Stop with true if an error is found. Return true if the walk
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146 | * completes with the last TD.
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147 | */
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148 | bool ohci_transfer_batch_check_completed(ohci_transfer_batch_t *ohci_batch)
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149 | {
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150 | assert(ohci_batch);
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151 |
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152 | usb_transfer_batch_t *usb_batch = &ohci_batch->base;
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153 | ohci_endpoint_t *ohci_ep = ohci_endpoint_get(usb_batch->ep);
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154 | assert(ohci_ep);
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155 |
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156 | usb_log_debug("Batch %p checking %zu td(s) for completion.",
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157 | ohci_batch, ohci_batch->td_count);
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158 | usb_log_debug2("ED: %08x:%08x:%08x:%08x.",
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159 | ohci_ep->ed->status, ohci_ep->ed->td_head,
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160 | ohci_ep->ed->td_tail, ohci_ep->ed->next);
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161 |
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162 | if (!ed_inactive(ohci_ep->ed) && ed_transfer_pending(ohci_ep->ed))
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163 | return false;
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164 |
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165 | /* Now we may be sure that either the ED is inactive because of errors
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166 | * or all transfer descriptors completed successfully */
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167 |
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168 | /* Assume all data got through */
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169 | usb_batch->transferred_size = usb_batch->size;
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170 |
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171 | /* Check all TDs */
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172 | for (size_t i = 0; i < ohci_batch->td_count; ++i) {
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173 | assert(ohci_batch->tds[i] != NULL);
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174 | usb_log_debug("TD %zu: %08x:%08x:%08x:%08x.", i,
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175 | ohci_batch->tds[i]->status, ohci_batch->tds[i]->cbp,
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176 | ohci_batch->tds[i]->next, ohci_batch->tds[i]->be);
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177 |
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178 | usb_batch->error = td_error(ohci_batch->tds[i]);
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179 | if (usb_batch->error == EOK) {
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180 | /* If the TD got all its data through, it will report
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181 | * 0 bytes remain, the sole exception is INPUT with
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182 | * data rounding flag (short), i.e. every INPUT.
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183 | * Nice thing is that short packets will correctly
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184 | * report remaining data, thus making this computation
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185 | * correct (short packets need to be produced by the
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186 | * last TD)
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187 | * NOTE: This also works for CONTROL transfer as
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188 | * the first TD will return 0 remain.
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189 | * NOTE: Short packets don't break the assumption that
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190 | * we leave the very last(unused) TD behind.
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191 | */
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192 | usb_batch->transferred_size -=
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193 | td_remain_size(ohci_batch->tds[i]);
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194 | } else {
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195 | usb_log_debug("Batch %p found error TD(%zu):%08x.",
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196 | ohci_batch, i, ohci_batch->tds[i]->status);
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197 |
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198 | /* ED should be stopped because of errors */
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199 | assert((ohci_ep->ed->td_head & ED_TDHEAD_HALTED_FLAG) != 0);
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200 |
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201 | /* We don't care where the processing stopped, we just
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202 | * need to make sure it's not using any of the TDs owned
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203 | * by the transfer.
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204 | *
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205 | * As the chain is terminated by a TD in ownership of
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206 | * the EP, set it.
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207 | */
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208 | ed_set_head_td(ohci_ep->ed, ohci_ep->tds[0]);
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209 |
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210 | /* Clear the halted condition for the next transfer */
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211 | ed_clear_halt(ohci_ep->ed);
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212 | break;
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213 | }
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214 | }
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215 | assert(usb_batch->transferred_size <= usb_batch->size);
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216 |
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217 | /* Make sure that we are leaving the right TD behind */
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218 | assert(addr_to_phys(ohci_ep->tds[0]) == ed_tail_td(ohci_ep->ed));
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219 | assert(ed_tail_td(ohci_ep->ed) == ed_head_td(ohci_ep->ed));
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220 |
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221 | return true;
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222 | }
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223 |
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224 | /** Starts execution of the TD list
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225 | *
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226 | * @param[in] ohci_batch Batch structure to use
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227 | */
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228 | void ohci_transfer_batch_commit(const ohci_transfer_batch_t *ohci_batch)
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229 | {
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230 | assert(ohci_batch);
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231 |
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232 | ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ohci_batch->base.ep);
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233 |
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234 | usb_log_debug("Using ED(%p): %08x:%08x:%08x:%08x.", ohci_ep->ed,
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235 | ohci_ep->ed->status, ohci_ep->ed->td_tail,
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236 | ohci_ep->ed->td_head, ohci_ep->ed->next);
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237 |
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238 | /*
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239 | * According to spec, we need to copy the first TD to the currently
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240 | * enqueued one.
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241 | */
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242 | memcpy(ohci_ep->tds[0], ohci_batch->tds[0], sizeof(td_t));
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243 | ohci_batch->tds[0] = ohci_ep->tds[0];
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244 |
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245 | td_t *last = ohci_batch->tds[ohci_batch->td_count - 1];
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246 | td_set_next(last, ohci_ep->tds[1]);
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247 |
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248 | ed_set_tail_td(ohci_ep->ed, ohci_ep->tds[1]);
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249 |
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250 | /* Swap the EP TDs for the next transfer */
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251 | td_t *tmp = ohci_ep->tds[0];
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252 | ohci_ep->tds[0] = ohci_ep->tds[1];
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253 | ohci_ep->tds[1] = tmp;
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254 | }
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255 |
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256 | /** Prepare generic control transfer
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257 | *
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258 | * @param[in] ohci_batch Batch structure to use.
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259 | * @param[in] dir Communication direction
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260 | *
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261 | * Setup stage with toggle 0 and direction BOTH(SETUP_PID)
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262 | * Data stage with alternating toggle and direction supplied by parameter.
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263 | * Status stage with toggle 1 and direction supplied by parameter.
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264 | */
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265 | static void batch_control(ohci_transfer_batch_t *ohci_batch)
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266 | {
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267 | assert(ohci_batch);
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268 |
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269 | usb_direction_t dir = ohci_batch->base.dir;
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270 | assert(dir == USB_DIRECTION_IN || dir == USB_DIRECTION_OUT);
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271 |
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272 | static const usb_direction_t reverse_dir[] = {
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273 | [USB_DIRECTION_IN] = USB_DIRECTION_OUT,
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274 | [USB_DIRECTION_OUT] = USB_DIRECTION_IN,
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275 | };
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276 |
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277 | int toggle = 0;
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278 | const usb_direction_t data_dir = dir;
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279 | const usb_direction_t status_dir = reverse_dir[dir];
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280 |
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281 | /* Setup stage */
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282 | td_init(
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283 | ohci_batch->tds[0], ohci_batch->tds[1], USB_DIRECTION_BOTH,
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284 | ohci_batch->setup_buffer, USB_SETUP_PACKET_SIZE, toggle);
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285 | usb_log_debug("Created CONTROL SETUP TD: %08x:%08x:%08x:%08x.",
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286 | ohci_batch->tds[0]->status, ohci_batch->tds[0]->cbp,
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287 | ohci_batch->tds[0]->next, ohci_batch->tds[0]->be);
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288 |
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289 | /* Data stage */
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290 | size_t td_current = 1;
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291 | const char *buffer = ohci_batch->data_buffer;
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292 | size_t remain_size = ohci_batch->base.size;
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293 | while (remain_size > 0) {
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294 | const size_t transfer_size =
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295 | min(remain_size, OHCI_TD_MAX_TRANSFER);
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296 | toggle = 1 - toggle;
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297 |
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298 | td_init(ohci_batch->tds[td_current],
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299 | ohci_batch->tds[td_current + 1],
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300 | data_dir, buffer, transfer_size, toggle);
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301 | usb_log_debug("Created CONTROL DATA TD: %08x:%08x:%08x:%08x.",
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302 | ohci_batch->tds[td_current]->status,
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303 | ohci_batch->tds[td_current]->cbp,
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304 | ohci_batch->tds[td_current]->next,
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305 | ohci_batch->tds[td_current]->be);
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306 |
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307 | buffer += transfer_size;
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308 | remain_size -= transfer_size;
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309 | assert(td_current < ohci_batch->td_count - 1);
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310 | ++td_current;
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311 | }
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312 |
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313 | /* Status stage */
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314 | assert(td_current == ohci_batch->td_count - 1);
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315 | td_init(ohci_batch->tds[td_current], ohci_batch->tds[td_current + 1],
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316 | status_dir, NULL, 0, 1);
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317 | usb_log_debug("Created CONTROL STATUS TD: %08x:%08x:%08x:%08x.",
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318 | ohci_batch->tds[td_current]->status,
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319 | ohci_batch->tds[td_current]->cbp,
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320 | ohci_batch->tds[td_current]->next,
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321 | ohci_batch->tds[td_current]->be);
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322 | usb_log_debug2(
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323 | "Batch %p %s %s " USB_TRANSFER_BATCH_FMT " initialized.",
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324 | &ohci_batch->base,
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325 | usb_str_transfer_type(ohci_batch->base.ep->transfer_type),
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326 | usb_str_direction(dir),
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327 | USB_TRANSFER_BATCH_ARGS(ohci_batch->base));
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328 | }
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329 |
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330 | /** Prepare generic data transfer
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331 | *
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332 | * @param[in] ohci_batch Batch structure to use.
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333 | * @paramp[in] dir Communication direction.
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334 | *
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335 | * Direction is supplied by the associated ep and toggle is maintained by the
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336 | * OHCI hw in ED.
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337 | */
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338 | static void batch_data(ohci_transfer_batch_t *ohci_batch)
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339 | {
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340 | assert(ohci_batch);
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341 |
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342 | usb_direction_t dir = ohci_batch->base.dir;
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343 | assert(dir == USB_DIRECTION_IN || dir == USB_DIRECTION_OUT);
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344 |
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345 | size_t td_current = 0;
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346 | size_t remain_size = ohci_batch->base.size;
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347 | char *buffer = ohci_batch->data_buffer;
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348 | while (remain_size > 0) {
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349 | const size_t transfer_size = remain_size > OHCI_TD_MAX_TRANSFER ?
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350 | OHCI_TD_MAX_TRANSFER : remain_size;
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351 |
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352 | td_init(
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353 | ohci_batch->tds[td_current], ohci_batch->tds[td_current + 1],
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354 | dir, buffer, transfer_size, -1);
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355 |
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356 | usb_log_debug("Created DATA TD: %08x:%08x:%08x:%08x.",
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357 | ohci_batch->tds[td_current]->status,
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358 | ohci_batch->tds[td_current]->cbp,
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359 | ohci_batch->tds[td_current]->next,
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360 | ohci_batch->tds[td_current]->be);
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361 |
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362 | buffer += transfer_size;
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363 | remain_size -= transfer_size;
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364 | assert(td_current < ohci_batch->td_count);
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365 | ++td_current;
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366 | }
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367 | usb_log_debug2(
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368 | "Batch %p %s %s " USB_TRANSFER_BATCH_FMT " initialized.",
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369 | &ohci_batch->base,
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370 | usb_str_transfer_type(ohci_batch->base.ep->transfer_type),
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371 | usb_str_direction(dir),
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372 | USB_TRANSFER_BATCH_ARGS(ohci_batch->base));
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373 | }
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374 |
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375 | /** Transfer setup table. */
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376 | static void (*const batch_setup[])(ohci_transfer_batch_t *) =
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377 | {
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378 | [USB_TRANSFER_CONTROL] = batch_control,
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379 | [USB_TRANSFER_BULK] = batch_data,
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380 | [USB_TRANSFER_INTERRUPT] = batch_data,
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381 | [USB_TRANSFER_ISOCHRONOUS] = NULL,
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382 | };
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383 | /**
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384 | * @}
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385 | */
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