[41b96b4] | 1 | /*
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| 2 | * Copyright (c) 2011 Jan Vesely
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[e0a5d4c] | 3 | * Copyright (c) 2018 Ondrej Hlavaty
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[41b96b4] | 4 | * All rights reserved.
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| 5 | *
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| 6 | * Redistribution and use in source and binary forms, with or without
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| 7 | * modification, are permitted provided that the following conditions
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| 8 | * are met:
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| 9 | *
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| 10 | * - Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions and the following disclaimer.
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| 12 | * - Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | * - The name of the author may not be used to endorse or promote products
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| 16 | * derived from this software without specific prior written permission.
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| 17 | *
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | */
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[58563585] | 29 |
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[81dce9f] | 30 | /** @addtogroup drvusbohci
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[41b96b4] | 31 | * @{
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| 32 | */
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| 33 | /** @file
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| 34 | * @brief OHCI driver USB transaction structure
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| 35 | */
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[0d4b110] | 36 |
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| 37 | #include <assert.h>
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[41b96b4] | 38 | #include <errno.h>
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[3f162ab] | 39 | #include <macros.h>
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[0d4b110] | 40 | #include <mem.h>
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| 41 | #include <stdbool.h>
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[41b96b4] | 42 |
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| 43 | #include <usb/usb.h>
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| 44 | #include <usb/debug.h>
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[2dbfe44] | 45 | #include <usb/host/utils/malloc32.h>
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[41b96b4] | 46 |
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[ff6dd73] | 47 | #include "ohci_batch.h"
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[e6b9182] | 48 | #include "ohci_bus.h"
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[09ace19] | 49 |
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[3bacee1] | 50 | static void (*const batch_setup[])(ohci_transfer_batch_t *);
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[76fbd9a] | 51 |
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[28d9c95] | 52 | /** Safely destructs ohci_transfer_batch_t structure
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| 53 | *
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| 54 | * @param[in] ohci_batch Instance to destroy.
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| 55 | */
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[5fd9c30] | 56 | void ohci_transfer_batch_destroy(ohci_transfer_batch_t *ohci_batch)
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[2cc6e97] | 57 | {
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[5fd9c30] | 58 | assert(ohci_batch);
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[e67c50a] | 59 | dma_buffer_free(&ohci_batch->ohci_dma_buffer);
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[9c10e51] | 60 | free(ohci_batch);
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[2cc6e97] | 61 | }
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[76fbd9a] | 62 |
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[6fa04db] | 63 | /** Allocate memory and initialize internal data structure.
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| 64 | *
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[9162b27] | 65 | * @param[in] ep Endpoint for which the batch will be created
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[6fa04db] | 66 | * @return Valid pointer if all structures were successfully created,
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| 67 | * NULL otherwise.
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| 68 | */
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[3bacee1] | 69 | ohci_transfer_batch_t *ohci_transfer_batch_create(endpoint_t *ep)
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[9c10e51] | 70 | {
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[5fd9c30] | 71 | assert(ep);
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[e2976bb] | 72 |
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[9c10e51] | 73 | ohci_transfer_batch_t *ohci_batch =
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[8e3d17f] | 74 | calloc(1, sizeof(ohci_transfer_batch_t));
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[584aa38] | 75 | if (!ohci_batch) {
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| 76 | usb_log_error("Failed to allocate OHCI batch data.");
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[5fd9c30] | 77 | return NULL;
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[584aa38] | 78 | }
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[5fd9c30] | 79 |
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| 80 | usb_transfer_batch_init(&ohci_batch->base, ep);
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| 81 |
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| 82 | return ohci_batch;
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| 83 | }
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| 84 |
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| 85 | /** Prepares a batch to be sent.
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| 86 | *
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| 87 | * Determines the number of needed transfer descriptors (TDs).
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| 88 | * Prepares a transport buffer (that is accessible by the hardware).
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| 89 | * Initializes parameters needed for the transfer and callback.
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| 90 | */
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| 91 | int ohci_transfer_batch_prepare(ohci_transfer_batch_t *ohci_batch)
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| 92 | {
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| 93 | assert(ohci_batch);
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| 94 | usb_transfer_batch_t *usb_batch = &ohci_batch->base;
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| 95 |
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[e67c50a] | 96 | if (!batch_setup[usb_batch->ep->transfer_type])
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| 97 | return ENOTSUP;
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| 98 |
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[3bacee1] | 99 | ohci_batch->td_count = (usb_batch->size + OHCI_TD_MAX_TRANSFER - 1) /
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| 100 | OHCI_TD_MAX_TRANSFER;
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[e2976bb] | 101 | /* Control transfer need Setup and Status stage */
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[9c10e51] | 102 | if (usb_batch->ep->transfer_type == USB_TRANSFER_CONTROL) {
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| 103 | ohci_batch->td_count += 2;
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[e2976bb] | 104 | }
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| 105 |
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[e67c50a] | 106 | /* Alloc one more to NULL terminate */
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| 107 | ohci_batch->tds = calloc(ohci_batch->td_count + 1, sizeof(td_t *));
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| 108 | if (!ohci_batch->tds)
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[5fd9c30] | 109 | return ENOMEM;
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[e2976bb] | 110 |
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[e67c50a] | 111 | const size_t td_size = ohci_batch->td_count * sizeof(td_t);
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[3bacee1] | 112 | const size_t setup_size = (usb_batch->ep->transfer_type == USB_TRANSFER_CONTROL) ?
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| 113 | USB_SETUP_PACKET_SIZE :
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| 114 | 0;
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[9b8958b] | 115 |
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[c21e6a5] | 116 | if (dma_buffer_alloc(&ohci_batch->ohci_dma_buffer, td_size + setup_size)) {
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[e67c50a] | 117 | usb_log_error("Failed to allocate OHCI DMA buffer.");
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| 118 | return ENOMEM;
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[e2976bb] | 119 | }
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| 120 |
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[e67c50a] | 121 | td_t *tds = ohci_batch->ohci_dma_buffer.virt;
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| 122 |
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| 123 | for (size_t i = 0; i < ohci_batch->td_count; i++)
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| 124 | ohci_batch->tds[i] = &tds[i];
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| 125 |
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| 126 | /* Presence of this terminator makes TD initialization easier */
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| 127 | ohci_batch->tds[ohci_batch->td_count] = NULL;
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| 128 |
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| 129 | ohci_batch->setup_buffer = (void *) (&tds[ohci_batch->td_count]);
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| 130 | memcpy(ohci_batch->setup_buffer, usb_batch->setup.buffer, setup_size);
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| 131 |
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[c21e6a5] | 132 | ohci_batch->data_buffer = usb_batch->dma_buffer.virt;
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[e67c50a] | 133 |
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[5fd9c30] | 134 | batch_setup[usb_batch->ep->transfer_type](ohci_batch);
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[90dd59dc] | 135 |
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[5fd9c30] | 136 | return EOK;
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[e2976bb] | 137 | }
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[76fbd9a] | 138 |
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[28d9c95] | 139 | /** Check batch TDs' status.
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| 140 | *
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[5f57929] | 141 | * @param[in] ohci_batch Batch structure to use.
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[28d9c95] | 142 | * @return False, if there is an active TD, true otherwise.
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| 143 | *
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| 144 | * Walk all TDs (usually there is just one). Stop with false if there is an
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| 145 | * active TD. Stop with true if an error is found. Return true if the walk
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| 146 | * completes with the last TD.
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| 147 | */
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[5fd9c30] | 148 | bool ohci_transfer_batch_check_completed(ohci_transfer_batch_t *ohci_batch)
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[f98b8269] | 149 | {
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[9c10e51] | 150 | assert(ohci_batch);
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| 151 |
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[c21e6a5] | 152 | usb_transfer_batch_t *usb_batch = &ohci_batch->base;
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| 153 | ohci_endpoint_t *ohci_ep = ohci_endpoint_get(usb_batch->ep);
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[e67c50a] | 154 | assert(ohci_ep);
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| 155 |
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[a1732929] | 156 | usb_log_debug("Batch %p checking %zu td(s) for completion.",
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[c21e6a5] | 157 | ohci_batch, ohci_batch->td_count);
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[a1732929] | 158 | usb_log_debug2("ED: %08x:%08x:%08x:%08x.",
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[e67c50a] | 159 | ohci_ep->ed->status, ohci_ep->ed->td_head,
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| 160 | ohci_ep->ed->td_tail, ohci_ep->ed->next);
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[9c10e51] | 161 |
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[e67c50a] | 162 | if (!ed_inactive(ohci_ep->ed) && ed_transfer_pending(ohci_ep->ed))
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[d5abaf4] | 163 | return false;
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| 164 |
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[7c3fb9b] | 165 | /*
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| 166 | * Now we may be sure that either the ED is inactive because of errors
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| 167 | * or all transfer descriptors completed successfully
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| 168 | */
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[d5abaf4] | 169 |
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| 170 | /* Assume all data got through */
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[1d758fc] | 171 | usb_batch->transferred_size = usb_batch->size;
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[dab3112] | 172 |
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[d5abaf4] | 173 | /* Check all TDs */
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| 174 | for (size_t i = 0; i < ohci_batch->td_count; ++i) {
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[9c10e51] | 175 | assert(ohci_batch->tds[i] != NULL);
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[a1732929] | 176 | usb_log_debug("TD %zu: %08x:%08x:%08x:%08x.", i,
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[9c10e51] | 177 | ohci_batch->tds[i]->status, ohci_batch->tds[i]->cbp,
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| 178 | ohci_batch->tds[i]->next, ohci_batch->tds[i]->be);
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[d5abaf4] | 179 |
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[c21e6a5] | 180 | usb_batch->error = td_error(ohci_batch->tds[i]);
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| 181 | if (usb_batch->error == EOK) {
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[7c3fb9b] | 182 | /*
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| 183 | * If the TD got all its data through, it will report
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[7f7e6f5] | 184 | * 0 bytes remain, the sole exception is INPUT with
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| 185 | * data rounding flag (short), i.e. every INPUT.
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| 186 | * Nice thing is that short packets will correctly
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| 187 | * report remaining data, thus making this computation
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| 188 | * correct (short packets need to be produced by the
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| 189 | * last TD)
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| 190 | * NOTE: This also works for CONTROL transfer as
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| 191 | * the first TD will return 0 remain.
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| 192 | * NOTE: Short packets don't break the assumption that
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| 193 | * we leave the very last(unused) TD behind.
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| 194 | */
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[3bacee1] | 195 | usb_batch->transferred_size -=
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| 196 | td_remain_size(ohci_batch->tds[i]);
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[7f7e6f5] | 197 | } else {
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[a1732929] | 198 | usb_log_debug("Batch %p found error TD(%zu):%08x.",
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[c21e6a5] | 199 | ohci_batch, i, ohci_batch->tds[i]->status);
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[d5abaf4] | 200 |
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| 201 | /* ED should be stopped because of errors */
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[e67c50a] | 202 | assert((ohci_ep->ed->td_head & ED_TDHEAD_HALTED_FLAG) != 0);
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| 203 |
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[7c3fb9b] | 204 | /*
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| 205 | * We don't care where the processing stopped, we just
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[e67c50a] | 206 | * need to make sure it's not using any of the TDs owned
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| 207 | * by the transfer.
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| 208 | *
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| 209 | * As the chain is terminated by a TD in ownership of
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| 210 | * the EP, set it.
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[d5abaf4] | 211 | */
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[e67c50a] | 212 | ed_set_head_td(ohci_ep->ed, ohci_ep->tds[0]);
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[d5abaf4] | 213 |
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[e67c50a] | 214 | /* Clear the halted condition for the next transfer */
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| 215 | ed_clear_halt(ohci_ep->ed);
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[9a6fde4] | 216 | break;
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[f1be95c8] | 217 | }
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| 218 | }
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[1d758fc] | 219 | assert(usb_batch->transferred_size <= usb_batch->size);
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[e20eaed] | 220 |
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[dab3112] | 221 | /* Make sure that we are leaving the right TD behind */
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[e67c50a] | 222 | assert(addr_to_phys(ohci_ep->tds[0]) == ed_tail_td(ohci_ep->ed));
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| 223 | assert(ed_tail_td(ohci_ep->ed) == ed_head_td(ohci_ep->ed));
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[d6522dd] | 224 |
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[f1be95c8] | 225 | return true;
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[f98b8269] | 226 | }
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[76fbd9a] | 227 |
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[28d9c95] | 228 | /** Starts execution of the TD list
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| 229 | *
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[5f57929] | 230 | * @param[in] ohci_batch Batch structure to use
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[28d9c95] | 231 | */
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[11cb0565] | 232 | void ohci_transfer_batch_commit(const ohci_transfer_batch_t *ohci_batch)
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[7013b14] | 233 | {
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[9c10e51] | 234 | assert(ohci_batch);
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[e67c50a] | 235 |
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| 236 | ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ohci_batch->base.ep);
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| 237 |
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| 238 | usb_log_debug("Using ED(%p): %08x:%08x:%08x:%08x.", ohci_ep->ed,
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| 239 | ohci_ep->ed->status, ohci_ep->ed->td_tail,
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| 240 | ohci_ep->ed->td_head, ohci_ep->ed->next);
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| 241 |
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| 242 | /*
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| 243 | * According to spec, we need to copy the first TD to the currently
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| 244 | * enqueued one.
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| 245 | */
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| 246 | memcpy(ohci_ep->tds[0], ohci_batch->tds[0], sizeof(td_t));
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| 247 | ohci_batch->tds[0] = ohci_ep->tds[0];
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| 248 |
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| 249 | td_t *last = ohci_batch->tds[ohci_batch->td_count - 1];
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| 250 | td_set_next(last, ohci_ep->tds[1]);
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| 251 |
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| 252 | ed_set_tail_td(ohci_ep->ed, ohci_ep->tds[1]);
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| 253 |
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| 254 | /* Swap the EP TDs for the next transfer */
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| 255 | td_t *tmp = ohci_ep->tds[0];
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| 256 | ohci_ep->tds[0] = ohci_ep->tds[1];
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| 257 | ohci_ep->tds[1] = tmp;
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[7013b14] | 258 | }
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[76fbd9a] | 259 |
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[28d9c95] | 260 | /** Prepare generic control transfer
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| 261 | *
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[5f57929] | 262 | * @param[in] ohci_batch Batch structure to use.
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[058fd76] | 263 | * @param[in] dir Communication direction
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[28d9c95] | 264 | *
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| 265 | * Setup stage with toggle 0 and direction BOTH(SETUP_PID)
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| 266 | * Data stage with alternating toggle and direction supplied by parameter.
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| 267 | * Status stage with toggle 1 and direction supplied by parameter.
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| 268 | */
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[5fd9c30] | 269 | static void batch_control(ohci_transfer_batch_t *ohci_batch)
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[7786cea] | 270 | {
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[9c10e51] | 271 | assert(ohci_batch);
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[5fd9c30] | 272 |
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| 273 | usb_direction_t dir = ohci_batch->base.dir;
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[058fd76] | 274 | assert(dir == USB_DIRECTION_IN || dir == USB_DIRECTION_OUT);
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[5fd9c30] | 275 |
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[058fd76] | 276 | static const usb_direction_t reverse_dir[] = {
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| 277 | [USB_DIRECTION_IN] = USB_DIRECTION_OUT,
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| 278 | [USB_DIRECTION_OUT] = USB_DIRECTION_IN,
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| 279 | };
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[9c10e51] | 280 |
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[e42dd32] | 281 | int toggle = 0;
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[058fd76] | 282 | const usb_direction_t data_dir = dir;
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| 283 | const usb_direction_t status_dir = reverse_dir[dir];
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[9c10e51] | 284 |
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[dab3112] | 285 | /* Setup stage */
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[70d72dd] | 286 | td_init(
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| 287 | ohci_batch->tds[0], ohci_batch->tds[1], USB_DIRECTION_BOTH,
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[e67c50a] | 288 | ohci_batch->setup_buffer, USB_SETUP_PACKET_SIZE, toggle);
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[a1732929] | 289 | usb_log_debug("Created CONTROL SETUP TD: %08x:%08x:%08x:%08x.",
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[9c10e51] | 290 | ohci_batch->tds[0]->status, ohci_batch->tds[0]->cbp,
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| 291 | ohci_batch->tds[0]->next, ohci_batch->tds[0]->be);
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[e42dd32] | 292 |
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[dab3112] | 293 | /* Data stage */
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[e42dd32] | 294 | size_t td_current = 1;
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[3bacee1] | 295 | const char *buffer = ohci_batch->data_buffer;
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[1d758fc] | 296 | size_t remain_size = ohci_batch->base.size;
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[e42dd32] | 297 | while (remain_size > 0) {
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[9c10e51] | 298 | const size_t transfer_size =
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[3f162ab] | 299 | min(remain_size, OHCI_TD_MAX_TRANSFER);
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[e42dd32] | 300 | toggle = 1 - toggle;
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| 301 |
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[70d72dd] | 302 | td_init(ohci_batch->tds[td_current],
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| 303 | ohci_batch->tds[td_current + 1],
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| 304 | data_dir, buffer, transfer_size, toggle);
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[a1732929] | 305 | usb_log_debug("Created CONTROL DATA TD: %08x:%08x:%08x:%08x.",
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[9c10e51] | 306 | ohci_batch->tds[td_current]->status,
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| 307 | ohci_batch->tds[td_current]->cbp,
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| 308 | ohci_batch->tds[td_current]->next,
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| 309 | ohci_batch->tds[td_current]->be);
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[e42dd32] | 310 |
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[d017cea] | 311 | buffer += transfer_size;
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[e42dd32] | 312 | remain_size -= transfer_size;
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[9c10e51] | 313 | assert(td_current < ohci_batch->td_count - 1);
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[e42dd32] | 314 | ++td_current;
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| 315 | }
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| 316 |
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[dab3112] | 317 | /* Status stage */
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[9c10e51] | 318 | assert(td_current == ohci_batch->td_count - 1);
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[70d72dd] | 319 | td_init(ohci_batch->tds[td_current], ohci_batch->tds[td_current + 1],
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| 320 | status_dir, NULL, 0, 1);
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[a1732929] | 321 | usb_log_debug("Created CONTROL STATUS TD: %08x:%08x:%08x:%08x.",
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[9c10e51] | 322 | ohci_batch->tds[td_current]->status,
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| 323 | ohci_batch->tds[td_current]->cbp,
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| 324 | ohci_batch->tds[td_current]->next,
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| 325 | ohci_batch->tds[td_current]->be);
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[058fd76] | 326 | usb_log_debug2(
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[5ef16903] | 327 | "Batch %p %s %s " USB_TRANSFER_BATCH_FMT " initialized.",
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[9162b27] | 328 | &ohci_batch->base,
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| 329 | usb_str_transfer_type(ohci_batch->base.ep->transfer_type),
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[058fd76] | 330 | usb_str_direction(dir),
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[9162b27] | 331 | USB_TRANSFER_BATCH_ARGS(ohci_batch->base));
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[f98b8269] | 332 | }
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[76fbd9a] | 333 |
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[28d9c95] | 334 | /** Prepare generic data transfer
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| 335 | *
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[5f57929] | 336 | * @param[in] ohci_batch Batch structure to use.
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[058fd76] | 337 | * @paramp[in] dir Communication direction.
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[28d9c95] | 338 | *
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| 339 | * Direction is supplied by the associated ep and toggle is maintained by the
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| 340 | * OHCI hw in ED.
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| 341 | */
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[5fd9c30] | 342 | static void batch_data(ohci_transfer_batch_t *ohci_batch)
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[c6fe469] | 343 | {
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[9c10e51] | 344 | assert(ohci_batch);
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[5fd9c30] | 345 |
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| 346 | usb_direction_t dir = ohci_batch->base.dir;
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[058fd76] | 347 | assert(dir == USB_DIRECTION_IN || dir == USB_DIRECTION_OUT);
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[c6fe469] | 348 |
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[aa9ccf7] | 349 | size_t td_current = 0;
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[1d758fc] | 350 | size_t remain_size = ohci_batch->base.size;
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[e67c50a] | 351 | char *buffer = ohci_batch->data_buffer;
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[c6fe469] | 352 | while (remain_size > 0) {
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[3bacee1] | 353 | const size_t transfer_size = remain_size > OHCI_TD_MAX_TRANSFER ?
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| 354 | OHCI_TD_MAX_TRANSFER : remain_size;
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[c6fe469] | 355 |
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[70d72dd] | 356 | td_init(
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| 357 | ohci_batch->tds[td_current], ohci_batch->tds[td_current + 1],
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| 358 | dir, buffer, transfer_size, -1);
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[058fd76] | 359 |
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[a1732929] | 360 | usb_log_debug("Created DATA TD: %08x:%08x:%08x:%08x.",
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[9c10e51] | 361 | ohci_batch->tds[td_current]->status,
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| 362 | ohci_batch->tds[td_current]->cbp,
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| 363 | ohci_batch->tds[td_current]->next,
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| 364 | ohci_batch->tds[td_current]->be);
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[c6fe469] | 365 |
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[d017cea] | 366 | buffer += transfer_size;
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[c6fe469] | 367 | remain_size -= transfer_size;
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[9c10e51] | 368 | assert(td_current < ohci_batch->td_count);
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[c6fe469] | 369 | ++td_current;
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| 370 | }
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[5f57929] | 371 | usb_log_debug2(
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[5ef16903] | 372 | "Batch %p %s %s " USB_TRANSFER_BATCH_FMT " initialized.",
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[9162b27] | 373 | &ohci_batch->base,
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| 374 | usb_str_transfer_type(ohci_batch->base.ep->transfer_type),
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[058fd76] | 375 | usb_str_direction(dir),
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[9162b27] | 376 | USB_TRANSFER_BATCH_ARGS(ohci_batch->base));
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[7bce1fc] | 377 | }
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[76fbd9a] | 378 |
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[6fa04db] | 379 | /** Transfer setup table. */
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[3bacee1] | 380 | static void (*const batch_setup[])(ohci_transfer_batch_t *) =
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| 381 | {
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[790318e] | 382 | [USB_TRANSFER_CONTROL] = batch_control,
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| 383 | [USB_TRANSFER_BULK] = batch_data,
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| 384 | [USB_TRANSFER_INTERRUPT] = batch_data,
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| 385 | [USB_TRANSFER_ISOCHRONOUS] = NULL,
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[7bce1fc] | 386 | };
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[41b96b4] | 387 | /**
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| 388 | * @}
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| 389 | */
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