source: mainline/uspace/drv/bus/usb/ohci/hw_struct/endpoint_descriptor.h@ 0d4b110

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 0d4b110 was 0d4b110, checked in by Jan Vesely <jano.vesely@…>, 12 years ago

ohci: Sanitize includes.

Include what you use.

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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbohci
29 * @{
30 */
31/** @file
32 * @brief OHCI driver
33 */
34#ifndef DRV_OHCI_HW_STRUCT_ENDPOINT_DESCRIPTOR_H
35#define DRV_OHCI_HW_STRUCT_ENDPOINT_DESCRIPTOR_H
36
37#include <assert.h>
38#include <stdbool.h>
39#include <sys/types.h>
40
41#include <usb/host/endpoint.h>
42
43#include "../utils/malloc32.h"
44#include "transfer_descriptor.h"
45
46#include "completion_codes.h"
47#include "mem_access.h"
48
49/**
50 * OHCI Endpoint Descriptor representation.
51 *
52 * See OHCI spec. Chapter 4.2, page 16 (pdf page 30) for details */
53typedef struct ed {
54 /**
55 * Status field.
56 *
57 * See table 4-1, p. 17 OHCI spec (pdf page 31).
58 */
59 volatile uint32_t status;
60#define ED_STATUS_FA_MASK (0x7f) /* USB device address */
61#define ED_STATUS_FA_SHIFT (0)
62#define ED_STATUS_EN_MASK (0xf) /* USB endpoint address */
63#define ED_STATUS_EN_SHIFT (7)
64#define ED_STATUS_D_MASK (0x3) /* Direction */
65#define ED_STATUS_D_SHIFT (11)
66#define ED_STATUS_D_OUT (0x1)
67#define ED_STATUS_D_IN (0x2)
68#define ED_STATUS_D_TD (0x3) /* Direction is specified by TD */
69
70#define ED_STATUS_S_FLAG (1 << 13) /* Speed flag: 1 = low */
71#define ED_STATUS_K_FLAG (1 << 14) /* Skip flag (no not execute this ED) */
72#define ED_STATUS_F_FLAG (1 << 15) /* Format: 1 = isochronous */
73#define ED_STATUS_MPS_MASK (0x3ff) /* Maximum packet size */
74#define ED_STATUS_MPS_SHIFT (16)
75
76 /**
77 * Pointer to the last TD.
78 *
79 * OHCI hw never changes this field and uses it only for a reference.
80 */
81 volatile uint32_t td_tail;
82#define ED_TDTAIL_PTR_MASK (0xfffffff0)
83#define ED_TDTAIL_PTR_SHIFT (0)
84
85 /**
86 * Pointer to the first TD.
87 *
88 * Driver should not change this field if the ED is active.
89 * This field is updated by OHCI hw and points to the next TD
90 * to be executed.
91 */
92 volatile uint32_t td_head;
93#define ED_TDHEAD_PTR_MASK (0xfffffff0)
94#define ED_TDHEAD_PTR_SHIFT (0)
95#define ED_TDHEAD_ZERO_MASK (0x3)
96#define ED_TDHEAD_ZERO_SHIFT (2)
97#define ED_TDHEAD_TOGGLE_CARRY (0x2)
98#define ED_TDHEAD_HALTED_FLAG (0x1)
99
100 /**
101 * Pointer to the next ED.
102 *
103 * Driver should not change this field on active EDs.
104 */
105 volatile uint32_t next;
106#define ED_NEXT_PTR_MASK (0xfffffff0)
107#define ED_NEXT_PTR_SHIFT (0)
108} __attribute__((packed)) ed_t;
109
110void ed_init(ed_t *instance, const endpoint_t *ep, const td_t *td);
111
112/**
113 * Check for SKIP or HALTED flag being set.
114 * @param instance ED
115 * @return true if either SKIP or HALTED flag is set, false otherwise.
116 */
117static inline bool ed_inactive(const ed_t *instance)
118{
119 assert(instance);
120 return (OHCI_MEM32_RD(instance->td_head) & ED_TDHEAD_HALTED_FLAG)
121 || (OHCI_MEM32_RD(instance->status) & ED_STATUS_K_FLAG);
122}
123
124static inline void ed_clear_halt(ed_t *instance)
125{
126 assert(instance);
127 OHCI_MEM32_CLR(instance->td_head, ED_TDHEAD_HALTED_FLAG);
128}
129
130/**
131 * Check whether this ED contains TD to be executed.
132 * @param instance ED
133 * @return true if there are pending TDs, false otherwise.
134 */
135static inline bool ed_transfer_pending(const ed_t *instance)
136{
137 assert(instance);
138 return (OHCI_MEM32_RD(instance->td_head) & ED_TDHEAD_PTR_MASK)
139 != (OHCI_MEM32_RD(instance->td_tail) & ED_TDTAIL_PTR_MASK);
140}
141
142/**
143 * Set the last element of TD list
144 * @param instance ED
145 * @param instance TD to set as the last item.
146 */
147static inline void ed_set_tail_td(ed_t *instance, const td_t *td)
148{
149 assert(instance);
150 const uintptr_t pa = addr_to_phys(td);
151 OHCI_MEM32_WR(instance->td_tail, pa & ED_TDTAIL_PTR_MASK);
152}
153
154static inline uint32_t ed_tail_td(const ed_t *instance)
155{
156 assert(instance);
157 return OHCI_MEM32_RD(instance->td_tail) & ED_TDTAIL_PTR_MASK;
158}
159
160static inline uint32_t ed_head_td(const ed_t *instance)
161{
162 assert(instance);
163 return OHCI_MEM32_RD(instance->td_head) & ED_TDHEAD_PTR_MASK;
164}
165
166/**
167 * Set next ED in ED chain.
168 * @param instance ED to modify
169 * @param next ED to append
170 */
171static inline void ed_append_ed(ed_t *instance, const ed_t *next)
172{
173 assert(instance);
174 assert(next);
175 const uint32_t pa = addr_to_phys(next);
176 assert((pa & ED_NEXT_PTR_MASK) << ED_NEXT_PTR_SHIFT == pa);
177 OHCI_MEM32_WR(instance->next, pa);
178}
179
180static inline uint32_t ed_next(const ed_t *instance)
181{
182 assert(instance);
183 return OHCI_MEM32_RD(instance->next) & ED_NEXT_PTR_MASK;
184}
185
186/**
187 * Get toggle bit value stored in this ED
188 * @param instance ED
189 * @return Toggle bit value
190 */
191static inline int ed_toggle_get(const ed_t *instance)
192{
193 assert(instance);
194 return (OHCI_MEM32_RD(instance->td_head) & ED_TDHEAD_TOGGLE_CARRY) ? 1 : 0;
195}
196
197/**
198 * Set toggle bit value stored in this ED
199 * @param instance ED
200 * @param toggle Toggle bit value
201 */
202static inline void ed_toggle_set(ed_t *instance, bool toggle)
203{
204 assert(instance);
205 if (toggle) {
206 OHCI_MEM32_SET(instance->td_head, ED_TDHEAD_TOGGLE_CARRY);
207 } else {
208 /* Clear halted flag when reseting toggle TODO: Why? */
209 OHCI_MEM32_CLR(instance->td_head, ED_TDHEAD_TOGGLE_CARRY);
210 OHCI_MEM32_CLR(instance->td_head, ED_TDHEAD_HALTED_FLAG);
211 }
212}
213#endif
214/**
215 * @}
216 */
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