source: mainline/uspace/drv/bus/usb/ohci/hw_struct/endpoint_descriptor.h

Last change on this file was 7c3fb9b, checked in by Jiri Svoboda <jiri@…>, 7 years ago

Fix block comment formatting (ccheck).

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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * Copyright (c) 2018 Ondrej Hlavaty
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29/** @addtogroup drvusbohci
30 * @{
31 */
32/** @file
33 * @brief OHCI driver
34 */
35#ifndef DRV_OHCI_HW_STRUCT_ENDPOINT_DESCRIPTOR_H
36#define DRV_OHCI_HW_STRUCT_ENDPOINT_DESCRIPTOR_H
37
38#include <assert.h>
39#include <stdbool.h>
40#include <stdint.h>
41
42#include <usb/host/endpoint.h>
43#include <usb/host/utils/malloc32.h>
44
45#include "transfer_descriptor.h"
46
47#include "completion_codes.h"
48#include "mem_access.h"
49
50/**
51 * OHCI Endpoint Descriptor representation.
52 *
53 * See OHCI spec. Chapter 4.2, page 16 (pdf page 30) for details
54 */
55typedef struct ed {
56 /**
57 * Status field.
58 *
59 * See table 4-1, p. 17 OHCI spec (pdf page 31).
60 */
61 volatile uint32_t status;
62#define ED_STATUS_FA_MASK (0x7f) /* USB device address */
63#define ED_STATUS_FA_SHIFT (0)
64#define ED_STATUS_EN_MASK (0xf) /* USB endpoint address */
65#define ED_STATUS_EN_SHIFT (7)
66#define ED_STATUS_D_MASK (0x3) /* Direction */
67#define ED_STATUS_D_SHIFT (11)
68#define ED_STATUS_D_OUT (0x1)
69#define ED_STATUS_D_IN (0x2)
70#define ED_STATUS_D_TD (0x3) /* Direction is specified by TD */
71
72#define ED_STATUS_S_FLAG (1 << 13) /* Speed flag: 1 = low */
73#define ED_STATUS_K_FLAG (1 << 14) /* Skip flag (no not execute this ED) */
74#define ED_STATUS_F_FLAG (1 << 15) /* Format: 1 = isochronous */
75#define ED_STATUS_MPS_MASK (0x3ff) /* Maximum packet size */
76#define ED_STATUS_MPS_SHIFT (16)
77
78 /**
79 * Pointer to the last TD.
80 *
81 * OHCI hw never changes this field and uses it only for a reference.
82 */
83 volatile uint32_t td_tail;
84#define ED_TDTAIL_PTR_MASK (0xfffffff0)
85#define ED_TDTAIL_PTR_SHIFT (0)
86
87 /**
88 * Pointer to the first TD.
89 *
90 * Driver should not change this field if the ED is active.
91 * This field is updated by OHCI hw and points to the next TD
92 * to be executed.
93 */
94 volatile uint32_t td_head;
95#define ED_TDHEAD_PTR_MASK (0xfffffff0)
96#define ED_TDHEAD_PTR_SHIFT (0)
97#define ED_TDHEAD_ZERO_MASK (0x3)
98#define ED_TDHEAD_ZERO_SHIFT (2)
99#define ED_TDHEAD_TOGGLE_CARRY (0x2)
100#define ED_TDHEAD_HALTED_FLAG (0x1)
101
102 /**
103 * Pointer to the next ED.
104 *
105 * Driver should not change this field on active EDs.
106 */
107 volatile uint32_t next;
108#define ED_NEXT_PTR_MASK (0xfffffff0)
109#define ED_NEXT_PTR_SHIFT (0)
110} __attribute__((packed, aligned(32))) ed_t;
111
112void ed_init(ed_t *instance, const endpoint_t *ep, const td_t *td);
113
114/**
115 * Check for SKIP or HALTED flag being set.
116 * @param instance ED
117 * @return true if either SKIP or HALTED flag is set, false otherwise.
118 */
119static inline bool ed_inactive(const ed_t *instance)
120{
121 assert(instance);
122 return (OHCI_MEM32_RD(instance->td_head) & ED_TDHEAD_HALTED_FLAG) ||
123 (OHCI_MEM32_RD(instance->status) & ED_STATUS_K_FLAG);
124}
125
126static inline void ed_clear_halt(ed_t *instance)
127{
128 assert(instance);
129 OHCI_MEM32_CLR(instance->td_head, ED_TDHEAD_HALTED_FLAG);
130}
131
132/**
133 * Check whether this ED contains TD to be executed.
134 * @param instance ED
135 * @return true if there are pending TDs, false otherwise.
136 */
137static inline bool ed_transfer_pending(const ed_t *instance)
138{
139 assert(instance);
140 return (OHCI_MEM32_RD(instance->td_head) & ED_TDHEAD_PTR_MASK) !=
141 (OHCI_MEM32_RD(instance->td_tail) & ED_TDTAIL_PTR_MASK);
142}
143
144/**
145 * Set the last element of TD list
146 * @param instance ED
147 * @param instance TD to set as the last item.
148 */
149static inline void ed_set_tail_td(ed_t *instance, const td_t *td)
150{
151 assert(instance);
152 const uintptr_t pa = addr_to_phys(td);
153 OHCI_MEM32_WR(instance->td_tail, pa & ED_TDTAIL_PTR_MASK);
154}
155
156static inline uint32_t ed_tail_td(const ed_t *instance)
157{
158 assert(instance);
159 return OHCI_MEM32_RD(instance->td_tail) & ED_TDTAIL_PTR_MASK;
160}
161
162static inline uint32_t ed_head_td(const ed_t *instance)
163{
164 assert(instance);
165 return OHCI_MEM32_RD(instance->td_head) & ED_TDHEAD_PTR_MASK;
166}
167
168/**
169 * Set the HeadP of ED. Do not call unless the ED is Halted.
170 * @param instance ED
171 */
172static inline void ed_set_head_td(ed_t *instance, const td_t *td)
173{
174 assert(instance);
175 const uintptr_t pa = addr_to_phys(td);
176 OHCI_MEM32_WR(instance->td_head, pa & ED_TDHEAD_PTR_MASK);
177}
178
179/**
180 * Set next ED in ED chain.
181 * @param instance ED to modify
182 * @param next ED to append
183 */
184static inline void ed_append_ed(ed_t *instance, const ed_t *next)
185{
186 assert(instance);
187 assert(next);
188 const uint32_t pa = addr_to_phys(next);
189 assert((pa & ED_NEXT_PTR_MASK) << ED_NEXT_PTR_SHIFT == pa);
190 OHCI_MEM32_WR(instance->next, pa);
191}
192
193static inline uint32_t ed_next(const ed_t *instance)
194{
195 assert(instance);
196 return OHCI_MEM32_RD(instance->next) & ED_NEXT_PTR_MASK;
197}
198
199/**
200 * Get toggle bit value stored in this ED
201 * @param instance ED
202 * @return Toggle bit value
203 */
204static inline int ed_toggle_get(const ed_t *instance)
205{
206 assert(instance);
207 return !!(OHCI_MEM32_RD(instance->td_head) & ED_TDHEAD_TOGGLE_CARRY);
208}
209
210/**
211 * Set toggle bit value stored in this ED
212 * @param instance ED
213 * @param toggle Toggle bit value
214 */
215static inline void ed_toggle_set(ed_t *instance, bool toggle)
216{
217 assert(instance);
218 if (toggle) {
219 OHCI_MEM32_SET(instance->td_head, ED_TDHEAD_TOGGLE_CARRY);
220 } else {
221 /* Clear halted flag when reseting toggle TODO: Why? */
222 OHCI_MEM32_CLR(instance->td_head, ED_TDHEAD_TOGGLE_CARRY);
223 OHCI_MEM32_CLR(instance->td_head, ED_TDHEAD_HALTED_FLAG);
224 }
225}
226#endif
227/**
228 * @}
229 */
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