1 | /*
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2 | * Copyright (c) 2011 Jan Vesely
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3 | * Copyright (c) 2018 Ondrej Hlavaty
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4 | * All rights reserved.
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5 | *
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6 | * Redistribution and use in source and binary forms, with or without
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7 | * modification, are permitted provided that the following conditions
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8 | * are met:
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9 | *
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10 | * - Redistributions of source code must retain the above copyright
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11 | * notice, this list of conditions and the following disclaimer.
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12 | * - Redistributions in binary form must reproduce the above copyright
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13 | * notice, this list of conditions and the following disclaimer in the
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14 | * documentation and/or other materials provided with the distribution.
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15 | * - The name of the author may not be used to endorse or promote products
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16 | * derived from this software without specific prior written permission.
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17 | *
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18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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28 | */
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29 | /** @addtogroup drvusbohci
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30 | * @{
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31 | */
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32 | /** @file
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33 | * @brief OHCI driver
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34 | */
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35 | #ifndef DRV_OHCI_HW_STRUCT_ENDPOINT_DESCRIPTOR_H
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36 | #define DRV_OHCI_HW_STRUCT_ENDPOINT_DESCRIPTOR_H
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37 |
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38 | #include <assert.h>
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39 | #include <stdbool.h>
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40 | #include <stdint.h>
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41 |
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42 | #include <usb/host/endpoint.h>
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43 | #include <usb/host/utils/malloc32.h>
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44 |
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45 | #include "transfer_descriptor.h"
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46 |
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47 | #include "completion_codes.h"
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48 | #include "mem_access.h"
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49 |
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50 | /**
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51 | * OHCI Endpoint Descriptor representation.
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52 | *
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53 | * See OHCI spec. Chapter 4.2, page 16 (pdf page 30) for details
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54 | */
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55 | typedef struct ed {
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56 | /**
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57 | * Status field.
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58 | *
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59 | * See table 4-1, p. 17 OHCI spec (pdf page 31).
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60 | */
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61 | volatile uint32_t status;
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62 | #define ED_STATUS_FA_MASK (0x7f) /* USB device address */
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63 | #define ED_STATUS_FA_SHIFT (0)
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64 | #define ED_STATUS_EN_MASK (0xf) /* USB endpoint address */
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65 | #define ED_STATUS_EN_SHIFT (7)
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66 | #define ED_STATUS_D_MASK (0x3) /* Direction */
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67 | #define ED_STATUS_D_SHIFT (11)
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68 | #define ED_STATUS_D_OUT (0x1)
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69 | #define ED_STATUS_D_IN (0x2)
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70 | #define ED_STATUS_D_TD (0x3) /* Direction is specified by TD */
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71 |
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72 | #define ED_STATUS_S_FLAG (1 << 13) /* Speed flag: 1 = low */
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73 | #define ED_STATUS_K_FLAG (1 << 14) /* Skip flag (no not execute this ED) */
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74 | #define ED_STATUS_F_FLAG (1 << 15) /* Format: 1 = isochronous */
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75 | #define ED_STATUS_MPS_MASK (0x3ff) /* Maximum packet size */
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76 | #define ED_STATUS_MPS_SHIFT (16)
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77 |
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78 | /**
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79 | * Pointer to the last TD.
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80 | *
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81 | * OHCI hw never changes this field and uses it only for a reference.
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82 | */
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83 | volatile uint32_t td_tail;
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84 | #define ED_TDTAIL_PTR_MASK (0xfffffff0)
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85 | #define ED_TDTAIL_PTR_SHIFT (0)
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86 |
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87 | /**
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88 | * Pointer to the first TD.
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89 | *
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90 | * Driver should not change this field if the ED is active.
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91 | * This field is updated by OHCI hw and points to the next TD
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92 | * to be executed.
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93 | */
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94 | volatile uint32_t td_head;
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95 | #define ED_TDHEAD_PTR_MASK (0xfffffff0)
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96 | #define ED_TDHEAD_PTR_SHIFT (0)
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97 | #define ED_TDHEAD_ZERO_MASK (0x3)
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98 | #define ED_TDHEAD_ZERO_SHIFT (2)
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99 | #define ED_TDHEAD_TOGGLE_CARRY (0x2)
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100 | #define ED_TDHEAD_HALTED_FLAG (0x1)
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101 |
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102 | /**
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103 | * Pointer to the next ED.
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104 | *
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105 | * Driver should not change this field on active EDs.
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106 | */
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107 | volatile uint32_t next;
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108 | #define ED_NEXT_PTR_MASK (0xfffffff0)
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109 | #define ED_NEXT_PTR_SHIFT (0)
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110 | } __attribute__((packed, aligned(32))) ed_t;
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111 |
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112 | void ed_init(ed_t *instance, const endpoint_t *ep, const td_t *td);
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113 |
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114 | /**
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115 | * Check for SKIP or HALTED flag being set.
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116 | * @param instance ED
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117 | * @return true if either SKIP or HALTED flag is set, false otherwise.
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118 | */
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119 | static inline bool ed_inactive(const ed_t *instance)
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120 | {
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121 | assert(instance);
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122 | return (OHCI_MEM32_RD(instance->td_head) & ED_TDHEAD_HALTED_FLAG) ||
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123 | (OHCI_MEM32_RD(instance->status) & ED_STATUS_K_FLAG);
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124 | }
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125 |
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126 | static inline void ed_clear_halt(ed_t *instance)
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127 | {
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128 | assert(instance);
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129 | OHCI_MEM32_CLR(instance->td_head, ED_TDHEAD_HALTED_FLAG);
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130 | }
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131 |
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132 | /**
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133 | * Check whether this ED contains TD to be executed.
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134 | * @param instance ED
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135 | * @return true if there are pending TDs, false otherwise.
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136 | */
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137 | static inline bool ed_transfer_pending(const ed_t *instance)
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138 | {
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139 | assert(instance);
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140 | return (OHCI_MEM32_RD(instance->td_head) & ED_TDHEAD_PTR_MASK) !=
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141 | (OHCI_MEM32_RD(instance->td_tail) & ED_TDTAIL_PTR_MASK);
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142 | }
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143 |
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144 | /**
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145 | * Set the last element of TD list
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146 | * @param instance ED
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147 | * @param instance TD to set as the last item.
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148 | */
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149 | static inline void ed_set_tail_td(ed_t *instance, const td_t *td)
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150 | {
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151 | assert(instance);
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152 | const uintptr_t pa = addr_to_phys(td);
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153 | OHCI_MEM32_WR(instance->td_tail, pa & ED_TDTAIL_PTR_MASK);
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154 | }
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155 |
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156 | static inline uint32_t ed_tail_td(const ed_t *instance)
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157 | {
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158 | assert(instance);
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159 | return OHCI_MEM32_RD(instance->td_tail) & ED_TDTAIL_PTR_MASK;
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160 | }
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161 |
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162 | static inline uint32_t ed_head_td(const ed_t *instance)
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163 | {
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164 | assert(instance);
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165 | return OHCI_MEM32_RD(instance->td_head) & ED_TDHEAD_PTR_MASK;
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166 | }
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167 |
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168 | /**
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169 | * Set the HeadP of ED. Do not call unless the ED is Halted.
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170 | * @param instance ED
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171 | */
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172 | static inline void ed_set_head_td(ed_t *instance, const td_t *td)
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173 | {
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174 | assert(instance);
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175 | const uintptr_t pa = addr_to_phys(td);
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176 | OHCI_MEM32_WR(instance->td_head, pa & ED_TDHEAD_PTR_MASK);
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177 | }
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178 |
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179 | /**
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180 | * Set next ED in ED chain.
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181 | * @param instance ED to modify
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182 | * @param next ED to append
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183 | */
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184 | static inline void ed_append_ed(ed_t *instance, const ed_t *next)
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185 | {
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186 | assert(instance);
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187 | assert(next);
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188 | const uint32_t pa = addr_to_phys(next);
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189 | assert((pa & ED_NEXT_PTR_MASK) << ED_NEXT_PTR_SHIFT == pa);
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190 | OHCI_MEM32_WR(instance->next, pa);
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191 | }
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192 |
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193 | static inline uint32_t ed_next(const ed_t *instance)
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194 | {
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195 | assert(instance);
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196 | return OHCI_MEM32_RD(instance->next) & ED_NEXT_PTR_MASK;
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197 | }
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198 |
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199 | /**
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200 | * Get toggle bit value stored in this ED
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201 | * @param instance ED
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202 | * @return Toggle bit value
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203 | */
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204 | static inline int ed_toggle_get(const ed_t *instance)
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205 | {
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206 | assert(instance);
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207 | return !!(OHCI_MEM32_RD(instance->td_head) & ED_TDHEAD_TOGGLE_CARRY);
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208 | }
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209 |
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210 | /**
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211 | * Set toggle bit value stored in this ED
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212 | * @param instance ED
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213 | * @param toggle Toggle bit value
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214 | */
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215 | static inline void ed_toggle_set(ed_t *instance, bool toggle)
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216 | {
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217 | assert(instance);
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218 | if (toggle) {
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219 | OHCI_MEM32_SET(instance->td_head, ED_TDHEAD_TOGGLE_CARRY);
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220 | } else {
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221 | /* Clear halted flag when reseting toggle TODO: Why? */
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222 | OHCI_MEM32_CLR(instance->td_head, ED_TDHEAD_TOGGLE_CARRY);
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223 | OHCI_MEM32_CLR(instance->td_head, ED_TDHEAD_HALTED_FLAG);
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224 | }
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225 | }
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226 | #endif
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227 | /**
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228 | * @}
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229 | */
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