source: mainline/uspace/drv/bus/usb/ohci/hc.c@ e6d7df1

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since e6d7df1 was a25d893, checked in by Jan Vesely <jano.vesely@…>, 10 years ago

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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbohcihc
30 * @{
31 */
32/** @file
33 * @brief OHCI Host controller driver routines
34 */
35
36#include <assert.h>
37#include <async.h>
38#include <errno.h>
39#include <macros.h>
40#include <mem.h>
41#include <stdlib.h>
42#include <str_error.h>
43#include <sys/types.h>
44
45#include <usb/debug.h>
46#include <usb/usb.h>
47
48#include "ohci_endpoint.h"
49#include "ohci_batch.h"
50#include "utils/malloc32.h"
51
52#include "hc.h"
53
54#define OHCI_USED_INTERRUPTS \
55 (I_SO | I_WDH | I_UE | I_RHSC)
56
57static const irq_pio_range_t ohci_pio_ranges[] = {
58 {
59 .base = 0,
60 .size = sizeof(ohci_regs_t)
61 }
62};
63
64static const irq_cmd_t ohci_irq_commands[] = {
65 {
66 .cmd = CMD_PIO_READ_32,
67 .dstarg = 1,
68 .addr = NULL
69 },
70 {
71 .cmd = CMD_AND,
72 .srcarg = 1,
73 .dstarg = 2,
74 .value = 0
75 },
76 {
77 .cmd = CMD_PREDICATE,
78 .srcarg = 2,
79 .value = 2
80 },
81 {
82 .cmd = CMD_PIO_WRITE_A_32,
83 .srcarg = 1,
84 .addr = NULL
85 },
86 {
87 .cmd = CMD_ACCEPT
88 }
89};
90
91static void hc_gain_control(hc_t *instance);
92static void hc_start(hc_t *instance);
93static int hc_init_transfer_lists(hc_t *instance);
94static int hc_init_memory(hc_t *instance);
95
96/** Generate IRQ code.
97 * @param[out] ranges PIO ranges buffer.
98 * @param[in] ranges_size Size of the ranges buffer (bytes).
99 * @param[out] cmds Commands buffer.
100 * @param[in] cmds_size Size of the commands buffer (bytes).
101 * @param[in] hw_res Device's resources.
102 *
103 * @return Error code.
104 */
105int ohci_hc_gen_irq_code(irq_code_t *code, const hw_res_list_parsed_t *hw_res)
106{
107 assert(code);
108 assert(hw_res);
109
110 if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
111 return EINVAL;
112
113 const addr_range_t regs = hw_res->mem_ranges.ranges[0];
114
115 if (RNGSZ(regs) < sizeof(ohci_regs_t))
116 return EOVERFLOW;
117
118 code->ranges = malloc(sizeof(ohci_pio_ranges));
119 if (code->ranges == NULL)
120 return ENOMEM;
121
122 code->cmds = malloc(sizeof(ohci_irq_commands));
123 if (code->cmds == NULL) {
124 free(code->ranges);
125 return ENOMEM;
126 }
127
128 code->rangecount = ARRAY_SIZE(ohci_pio_ranges);
129 code->cmdcount = ARRAY_SIZE(ohci_irq_commands);
130
131 memcpy(code->ranges, ohci_pio_ranges, sizeof(ohci_pio_ranges));
132 code->ranges[0].base = RNGABS(regs);
133
134 memcpy(code->cmds, ohci_irq_commands, sizeof(ohci_irq_commands));
135 ohci_regs_t *registers = (ohci_regs_t *) RNGABSPTR(regs);
136 code->cmds[0].addr = (void *) &registers->interrupt_status;
137 code->cmds[3].addr = (void *) &registers->interrupt_status;
138 OHCI_WR(code->cmds[1].value, OHCI_USED_INTERRUPTS);
139
140 usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.\n",
141 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
142
143 return hw_res->irqs.irqs[0];
144}
145
146/** Initialize OHCI hc driver structure
147 *
148 * @param[in] instance Memory place for the structure.
149 * @param[in] regs Device's resources
150 * @param[in] interrupts True if w interrupts should be used
151 * @return Error code
152 */
153int hc_init(hc_t *instance, const hw_res_list_parsed_t *hw_res, bool interrupts)
154{
155 assert(instance);
156 assert(hw_res);
157 if (hw_res->mem_ranges.count != 1 ||
158 hw_res->mem_ranges.ranges[0].size < sizeof(ohci_regs_t))
159 return EINVAL;
160
161 int ret = pio_enable_range(&hw_res->mem_ranges.ranges[0],
162 (void **) &instance->registers);
163 if (ret != EOK) {
164 usb_log_error("Failed to gain access to registers: %s.\n",
165 str_error(ret));
166 return ret;
167 }
168 usb_log_debug("Device registers at %" PRIx64 " (%zuB) accessible.\n",
169 hw_res->mem_ranges.ranges[0].address.absolute,
170 hw_res->mem_ranges.ranges[0].size);
171
172 list_initialize(&instance->pending_batches);
173 fibril_mutex_initialize(&instance->guard);
174 instance->hw_interrupts = interrupts;
175
176 ret = hc_init_memory(instance);
177 if (ret != EOK) {
178 usb_log_error("Failed to create OHCI memory structures: %s.\n",
179 str_error(ret));
180 //TODO: We should disable pio access here
181 return ret;
182 }
183
184 hc_gain_control(instance);
185
186 ohci_rh_init(&instance->rh, instance->registers, "ohci rh");
187 hc_start(instance);
188
189 return EOK;
190}
191
192/** Safely dispose host controller internal structures
193 *
194 * @param[in] instance Host controller structure to use.
195 */
196void hc_fini(hc_t *instance)
197{
198 assert(instance);
199 /* TODO: implement*/
200};
201
202void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
203{
204 assert(instance);
205 assert(ep);
206
207 endpoint_list_t *list = &instance->lists[ep->transfer_type];
208 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
209 assert(list);
210 assert(ohci_ep);
211
212 /* Enqueue ep */
213 switch (ep->transfer_type) {
214 case USB_TRANSFER_CONTROL:
215 OHCI_CLR(instance->registers->control, C_CLE);
216 endpoint_list_add_ep(list, ohci_ep);
217 OHCI_WR(instance->registers->control_current, 0);
218 OHCI_SET(instance->registers->control, C_CLE);
219 break;
220 case USB_TRANSFER_BULK:
221 OHCI_CLR(instance->registers->control, C_BLE);
222 endpoint_list_add_ep(list, ohci_ep);
223 OHCI_WR(instance->registers->bulk_current, 0);
224 OHCI_SET(instance->registers->control, C_BLE);
225 break;
226 case USB_TRANSFER_ISOCHRONOUS:
227 case USB_TRANSFER_INTERRUPT:
228 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
229 endpoint_list_add_ep(list, ohci_ep);
230 OHCI_SET(instance->registers->control, C_PLE | C_IE);
231 break;
232 }
233}
234
235void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
236{
237 assert(instance);
238 assert(ep);
239
240 /* Dequeue ep */
241 endpoint_list_t *list = &instance->lists[ep->transfer_type];
242 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
243
244 assert(list);
245 assert(ohci_ep);
246 switch (ep->transfer_type) {
247 case USB_TRANSFER_CONTROL:
248 OHCI_CLR(instance->registers->control, C_CLE);
249 endpoint_list_remove_ep(list, ohci_ep);
250 OHCI_WR(instance->registers->control_current, 0);
251 OHCI_SET(instance->registers->control, C_CLE);
252 break;
253 case USB_TRANSFER_BULK:
254 OHCI_CLR(instance->registers->control, C_BLE);
255 endpoint_list_remove_ep(list, ohci_ep);
256 OHCI_WR(instance->registers->bulk_current, 0);
257 OHCI_SET(instance->registers->control, C_BLE);
258 break;
259 case USB_TRANSFER_ISOCHRONOUS:
260 case USB_TRANSFER_INTERRUPT:
261 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
262 endpoint_list_remove_ep(list, ohci_ep);
263 OHCI_SET(instance->registers->control, C_PLE | C_IE);
264 break;
265 default:
266 break;
267 }
268}
269
270int ohci_hc_status(hcd_t *hcd, uint32_t *status)
271{
272 assert(hcd);
273 assert(status);
274 hc_t *instance = hcd->driver.data;
275 assert(instance);
276
277 if (instance->registers){
278 *status = OHCI_RD(instance->registers->interrupt_status);
279 OHCI_WR(instance->registers->interrupt_status, *status);
280 }
281 return EOK;
282}
283
284/** Add USB transfer to the schedule.
285 *
286 * @param[in] hcd HCD driver structure.
287 * @param[in] batch Batch representing the transfer.
288 * @return Error code.
289 */
290int ohci_hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
291{
292 assert(hcd);
293 hc_t *instance = hcd->driver.data;
294 assert(instance);
295
296 /* Check for root hub communication */
297 if (batch->ep->address == ohci_rh_get_address(&instance->rh)) {
298 usb_log_debug("OHCI root hub request.\n");
299 return ohci_rh_schedule(&instance->rh, batch);
300 }
301 ohci_transfer_batch_t *ohci_batch = ohci_transfer_batch_get(batch);
302 if (!ohci_batch)
303 return ENOMEM;
304
305 fibril_mutex_lock(&instance->guard);
306 list_append(&ohci_batch->link, &instance->pending_batches);
307 ohci_transfer_batch_commit(ohci_batch);
308
309 /* Control and bulk schedules need a kick to start working */
310 switch (batch->ep->transfer_type)
311 {
312 case USB_TRANSFER_CONTROL:
313 OHCI_SET(instance->registers->command_status, CS_CLF);
314 break;
315 case USB_TRANSFER_BULK:
316 OHCI_SET(instance->registers->command_status, CS_BLF);
317 break;
318 default:
319 break;
320 }
321 fibril_mutex_unlock(&instance->guard);
322 return EOK;
323}
324
325/** Interrupt handling routine
326 *
327 * @param[in] hcd HCD driver structure.
328 * @param[in] status Value of the status register at the time of interrupt.
329 */
330void ohci_hc_interrupt(hcd_t *hcd, uint32_t status)
331{
332 assert(hcd);
333 hc_t *instance = hcd->driver.data;
334 status = OHCI_RD(status);
335 assert(instance);
336 if ((status & ~I_SF) == 0) /* ignore sof status */
337 return;
338 usb_log_debug2("OHCI(%p) interrupt: %x.\n", instance, status);
339 if (status & I_RHSC)
340 ohci_rh_interrupt(&instance->rh);
341
342 if (status & I_WDH) {
343 fibril_mutex_lock(&instance->guard);
344 usb_log_debug2("HCCA: %p-%#" PRIx32 " (%p).\n", instance->hcca,
345 OHCI_RD(instance->registers->hcca),
346 (void *) addr_to_phys(instance->hcca));
347 usb_log_debug2("Periodic current: %#" PRIx32 ".\n",
348 OHCI_RD(instance->registers->periodic_current));
349
350 link_t *current = list_first(&instance->pending_batches);
351 while (current && current != &instance->pending_batches.head) {
352 link_t *next = current->next;
353 ohci_transfer_batch_t *batch =
354 ohci_transfer_batch_from_link(current);
355
356 if (ohci_transfer_batch_is_complete(batch)) {
357 list_remove(current);
358 ohci_transfer_batch_finish_dispose(batch);
359 }
360
361 current = next;
362 }
363 fibril_mutex_unlock(&instance->guard);
364 }
365
366 if (status & I_UE) {
367 usb_log_fatal("Error like no other!\n");
368 hc_start(instance);
369 }
370
371}
372
373/** Turn off any (BIOS)driver that might be in control of the device.
374 *
375 * This function implements routines described in chapter 5.1.1.3 of the OHCI
376 * specification (page 40, pdf page 54).
377 *
378 * @param[in] instance OHCI hc driver structure.
379 */
380void hc_gain_control(hc_t *instance)
381{
382 assert(instance);
383
384 usb_log_debug("Requesting OHCI control.\n");
385 if (OHCI_RD(instance->registers->revision) & R_LEGACY_FLAG) {
386 /* Turn off legacy emulation, it should be enough to zero
387 * the lowest bit, but it caused problems. Thus clear all
388 * except GateA20 (causes restart on some hw).
389 * See page 145 of the specs for details.
390 */
391 volatile uint32_t *ohci_emulation_reg =
392 (uint32_t*)((char*)instance->registers + LEGACY_REGS_OFFSET);
393 usb_log_debug("OHCI legacy register %p: %x.\n",
394 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
395 /* Zero everything but A20State */
396 //TODO: should we ack interrupts before doing this?
397 OHCI_CLR(*ohci_emulation_reg, ~0x100);
398 usb_log_debug(
399 "OHCI legacy register (should be 0 or 0x100) %p: %x.\n",
400 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
401 }
402
403 /* Interrupt routing enabled => smm driver is active */
404 if (OHCI_RD(instance->registers->control) & C_IR) {
405 usb_log_debug("SMM driver: request ownership change.\n");
406 //TODO: should we ack interrupts before doing this?
407 OHCI_SET(instance->registers->command_status, CS_OCR);
408 /* Hope that SMM actually knows its stuff or we can hang here */
409 while (OHCI_RD(instance->registers->control) & C_IR) {
410 async_usleep(1000);
411 }
412 usb_log_info("SMM driver: Ownership taken.\n");
413 C_HCFS_SET(instance->registers->control, C_HCFS_RESET);
414 async_usleep(50000);
415 return;
416 }
417
418 const unsigned hc_status = C_HCFS_GET(instance->registers->control);
419 /* Interrupt routing disabled && status != USB_RESET => BIOS active */
420 if (hc_status != C_HCFS_RESET) {
421 usb_log_debug("BIOS driver found.\n");
422 if (hc_status == C_HCFS_OPERATIONAL) {
423 usb_log_info("BIOS driver: HC operational.\n");
424 return;
425 }
426 /* HC is suspended assert resume for 20ms */
427 C_HCFS_SET(instance->registers->control, C_HCFS_RESUME);
428 async_usleep(20000);
429 usb_log_info("BIOS driver: HC resumed.\n");
430 return;
431 }
432
433 /* HC is in reset (hw startup) => no other driver
434 * maintain reset for at least the time specified in USB spec (50 ms)*/
435 usb_log_debug("Host controller found in reset state.\n");
436 async_usleep(50000);
437}
438
439/** OHCI hw initialization routine.
440 *
441 * @param[in] instance OHCI hc driver structure.
442 */
443void hc_start(hc_t *instance)
444{
445 /* OHCI guide page 42 */
446 assert(instance);
447 usb_log_debug2("Started hc initialization routine.\n");
448
449 /* Save contents of fm_interval register */
450 const uint32_t fm_interval = OHCI_RD(instance->registers->fm_interval);
451 usb_log_debug2("Old value of HcFmInterval: %x.\n", fm_interval);
452
453 /* Reset hc */
454 usb_log_debug2("HC reset.\n");
455 size_t time = 0;
456 OHCI_WR(instance->registers->command_status, CS_HCR);
457 while (OHCI_RD(instance->registers->command_status) & CS_HCR) {
458 async_usleep(10);
459 time += 10;
460 }
461 usb_log_debug2("HC reset complete in %zu us.\n", time);
462
463 /* Restore fm_interval */
464 OHCI_WR(instance->registers->fm_interval, fm_interval);
465 assert((OHCI_RD(instance->registers->command_status) & CS_HCR) == 0);
466
467 /* hc is now in suspend state */
468 usb_log_debug2("HC should be in suspend state(%x).\n",
469 OHCI_RD(instance->registers->control));
470
471 /* Use HCCA */
472 OHCI_WR(instance->registers->hcca, addr_to_phys(instance->hcca));
473
474 /* Use queues */
475 OHCI_WR(instance->registers->bulk_head,
476 instance->lists[USB_TRANSFER_BULK].list_head_pa);
477 usb_log_debug2("Bulk HEAD set to: %p (%#" PRIx32 ").\n",
478 instance->lists[USB_TRANSFER_BULK].list_head,
479 instance->lists[USB_TRANSFER_BULK].list_head_pa);
480
481 OHCI_WR(instance->registers->control_head,
482 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
483 usb_log_debug2("Control HEAD set to: %p (%#" PRIx32 ").\n",
484 instance->lists[USB_TRANSFER_CONTROL].list_head,
485 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
486
487 /* Enable queues */
488 OHCI_SET(instance->registers->control, (C_PLE | C_IE | C_CLE | C_BLE));
489 usb_log_debug("Queues enabled(%x).\n",
490 OHCI_RD(instance->registers->control));
491
492 /* Enable interrupts */
493 if (instance->hw_interrupts) {
494 OHCI_WR(instance->registers->interrupt_enable,
495 OHCI_USED_INTERRUPTS);
496 usb_log_debug("Enabled interrupts: %x.\n",
497 OHCI_RD(instance->registers->interrupt_enable));
498 OHCI_WR(instance->registers->interrupt_enable, I_MI);
499 }
500
501 /* Set periodic start to 90% */
502 const uint32_t frame_length =
503 (fm_interval >> FMI_FI_SHIFT) & FMI_FI_MASK;
504 OHCI_WR(instance->registers->periodic_start,
505 ((frame_length / 10) * 9) & PS_MASK << PS_SHIFT);
506 usb_log_debug2("All periodic start set to: %x(%u - 90%% of %d).\n",
507 OHCI_RD(instance->registers->periodic_start),
508 OHCI_RD(instance->registers->periodic_start), frame_length);
509 C_HCFS_SET(instance->registers->control, C_HCFS_OPERATIONAL);
510 usb_log_debug("OHCI HC up and running (ctl_reg=0x%x).\n",
511 OHCI_RD(instance->registers->control));
512}
513
514/** Initialize schedule queues
515 *
516 * @param[in] instance OHCI hc driver structure
517 * @return Error code
518 */
519int hc_init_transfer_lists(hc_t *instance)
520{
521 assert(instance);
522#define SETUP_ENDPOINT_LIST(type) \
523do { \
524 const char *name = usb_str_transfer_type(type); \
525 const int ret = endpoint_list_init(&instance->lists[type], name); \
526 if (ret != EOK) { \
527 usb_log_error("Failed to setup %s endpoint list: %s.\n", \
528 name, str_error(ret)); \
529 endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]);\
530 endpoint_list_fini(&instance->lists[USB_TRANSFER_INTERRUPT]); \
531 endpoint_list_fini(&instance->lists[USB_TRANSFER_CONTROL]); \
532 endpoint_list_fini(&instance->lists[USB_TRANSFER_BULK]); \
533 return ret; \
534 } \
535} while (0)
536
537 SETUP_ENDPOINT_LIST(USB_TRANSFER_ISOCHRONOUS);
538 SETUP_ENDPOINT_LIST(USB_TRANSFER_INTERRUPT);
539 SETUP_ENDPOINT_LIST(USB_TRANSFER_CONTROL);
540 SETUP_ENDPOINT_LIST(USB_TRANSFER_BULK);
541#undef SETUP_ENDPOINT_LIST
542 endpoint_list_set_next(&instance->lists[USB_TRANSFER_INTERRUPT],
543 &instance->lists[USB_TRANSFER_ISOCHRONOUS]);
544
545 return EOK;
546}
547
548/** Initialize memory structures used by the OHCI hcd.
549 *
550 * @param[in] instance OHCI hc driver structure.
551 * @return Error code.
552 */
553int hc_init_memory(hc_t *instance)
554{
555 assert(instance);
556
557 memset(&instance->rh, 0, sizeof(instance->rh));
558 /* Init queues */
559 const int ret = hc_init_transfer_lists(instance);
560 if (ret != EOK) {
561 return ret;
562 }
563
564 /*Init HCCA */
565 instance->hcca = hcca_get();
566 if (instance->hcca == NULL)
567 return ENOMEM;
568 usb_log_debug2("OHCI HCCA initialized at %p.\n", instance->hcca);
569
570 for (unsigned i = 0; i < HCCA_INT_EP_COUNT; ++i) {
571 hcca_set_int_ep(instance->hcca, i,
572 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
573 }
574 usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").\n",
575 instance->lists[USB_TRANSFER_INTERRUPT].list_head,
576 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
577
578 return EOK;
579}
580
581/**
582 * @}
583 */
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