source: mainline/uspace/drv/bus/usb/ohci/hc.c@ db71e2a

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since db71e2a was db71e2a, checked in by Jan Vesely <jano.vesely@…>, 12 years ago

merge mainline changes.

usb hc macro changes from mainline were reverted, too many conflicts
  • Property mode set to 100644
File size: 16.4 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbohcihc
30 * @{
31 */
32/** @file
33 * @brief OHCI Host controller driver routines
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <adt/list.h>
39#include <libarch/ddi.h>
40
41#include <usb/debug.h>
42#include <usb/usb.h>
43
44#include "hc.h"
45#include "ohci_endpoint.h"
46
47#define OHCI_USED_INTERRUPTS \
48 (I_SO | I_WDH | I_UE | I_RHSC)
49
50static const irq_pio_range_t ohci_pio_ranges[] = {
51 {
52 .base = 0,
53 .size = sizeof(ohci_regs_t)
54 }
55};
56
57static const irq_cmd_t ohci_irq_commands[] = {
58 {
59 .cmd = CMD_PIO_READ_32,
60 .dstarg = 1,
61 .addr = NULL
62 },
63 {
64 .cmd = CMD_AND,
65 .srcarg = 1,
66 .dstarg = 2,
67 .value = 0
68 },
69 {
70 .cmd = CMD_PREDICATE,
71 .srcarg = 2,
72 .value = 2
73 },
74 {
75 .cmd = CMD_PIO_WRITE_A_32,
76 .srcarg = 1,
77 .addr = NULL
78 },
79 {
80 .cmd = CMD_ACCEPT
81 }
82};
83
84static void hc_gain_control(hc_t *instance);
85static void hc_start(hc_t *instance);
86static int hc_init_transfer_lists(hc_t *instance);
87static int hc_init_memory(hc_t *instance);
88static int interrupt_emulator(hc_t *instance);
89
90/** Get number of PIO ranges used in IRQ code.
91 * @return Number of ranges.
92 */
93size_t hc_irq_pio_range_count(void)
94{
95 return sizeof(ohci_pio_ranges) / sizeof(irq_pio_range_t);
96}
97
98/** Get number of commands used in IRQ code.
99 * @return Number of commands.
100 */
101size_t hc_irq_cmd_count(void)
102{
103 return sizeof(ohci_irq_commands) / sizeof(irq_cmd_t);
104}
105
106/** Generate IRQ code.
107 * @param[out] ranges PIO ranges buffer.
108 * @param[in] ranges_size Size of the ranges buffer (bytes).
109 * @param[out] cmds Commands buffer.
110 * @param[in] cmds_size Size of the commands buffer (bytes).
111 * @param[in] regs Physical address of device's registers.
112 * @param[in] reg_size Size of the register area (bytes).
113 *
114 * @return Error code.
115 */
116int
117hc_get_irq_code(irq_pio_range_t ranges[], size_t ranges_size, irq_cmd_t cmds[],
118 size_t cmds_size, uintptr_t regs, size_t reg_size)
119{
120 if ((ranges_size < sizeof(ohci_pio_ranges)) ||
121 (cmds_size < sizeof(ohci_irq_commands)) ||
122 (reg_size < sizeof(ohci_regs_t)))
123 return EOVERFLOW;
124
125 memcpy(ranges, ohci_pio_ranges, sizeof(ohci_pio_ranges));
126 ranges[0].base = regs;
127
128 memcpy(cmds, ohci_irq_commands, sizeof(ohci_irq_commands));
129 ohci_regs_t *registers = (ohci_regs_t *) regs;
130 cmds[0].addr = (void *) &registers->interrupt_status;
131 cmds[3].addr = (void *) &registers->interrupt_status;
132 OHCI_WR(cmds[1].value, OHCI_USED_INTERRUPTS);
133
134 return EOK;
135}
136
137/** Initialize OHCI hc driver structure
138 *
139 * @param[in] instance Memory place for the structure.
140 * @param[in] regs Address of the memory mapped I/O registers.
141 * @param[in] reg_size Size of the memory mapped area.
142 * @param[in] interrupts True if w interrupts should be used
143 * @return Error code
144 */
145int hc_init(hc_t *instance, uintptr_t regs, size_t reg_size, bool interrupts)
146{
147 assert(instance);
148
149#define CHECK_RET_RETURN(ret, message...) \
150if (ret != EOK) { \
151 usb_log_error(message); \
152 return ret; \
153} else (void)0
154
155 int ret =
156 pio_enable((void*)regs, reg_size, (void**)&instance->registers);
157 CHECK_RET_RETURN(ret,
158 "Failed to gain access to device registers: %s.\n", str_error(ret));
159
160 list_initialize(&instance->pending_batches);
161
162 ret = hc_init_memory(instance);
163 CHECK_RET_RETURN(ret, "Failed to create OHCI memory structures: %s.\n",
164 str_error(ret));
165#undef CHECK_RET_RETURN
166
167 fibril_mutex_initialize(&instance->guard);
168
169 hc_gain_control(instance);
170
171 if (!interrupts) {
172 instance->interrupt_emulator =
173 fibril_create((int(*)(void*))interrupt_emulator, instance);
174 fibril_add_ready(instance->interrupt_emulator);
175 }
176
177 ohci_rh_init(&instance->rh, instance->registers, "ohci rh");
178 hc_start(instance);
179
180 return EOK;
181}
182
183void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
184{
185 assert(instance);
186 assert(ep);
187
188 endpoint_list_t *list = &instance->lists[ep->transfer_type];
189 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
190 assert(list);
191 assert(ohci_ep);
192
193 /* Enqueue ep */
194 switch (ep->transfer_type) {
195 case USB_TRANSFER_CONTROL:
196 OHCI_CLR(instance->registers->control, C_CLE);
197 endpoint_list_add_ep(list, ohci_ep);
198 OHCI_WR(instance->registers->control_current, 0);
199 OHCI_SET(instance->registers->control, C_CLE);
200 break;
201 case USB_TRANSFER_BULK:
202 OHCI_CLR(instance->registers->control, C_BLE);
203 endpoint_list_add_ep(list, ohci_ep);
204 OHCI_WR(instance->registers->bulk_current, 0);
205 OHCI_SET(instance->registers->control, C_BLE);
206 break;
207 case USB_TRANSFER_ISOCHRONOUS:
208 case USB_TRANSFER_INTERRUPT:
209 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
210 endpoint_list_add_ep(list, ohci_ep);
211 OHCI_SET(instance->registers->control, C_PLE | C_IE);
212 break;
213 }
214}
215
216void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
217{
218 assert(instance);
219 assert(ep);
220
221 /* Dequeue ep */
222 endpoint_list_t *list = &instance->lists[ep->transfer_type];
223 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
224
225 assert(list);
226 assert(ohci_ep);
227 switch (ep->transfer_type) {
228 case USB_TRANSFER_CONTROL:
229 OHCI_CLR(instance->registers->control, C_CLE);
230 endpoint_list_remove_ep(list, ohci_ep);
231 OHCI_WR(instance->registers->control_current, 0);
232 OHCI_SET(instance->registers->control, C_CLE);
233 break;
234 case USB_TRANSFER_BULK:
235 OHCI_CLR(instance->registers->control, C_BLE);
236 endpoint_list_remove_ep(list, ohci_ep);
237 OHCI_WR(instance->registers->bulk_current, 0);
238 OHCI_SET(instance->registers->control, C_BLE);
239 break;
240 case USB_TRANSFER_ISOCHRONOUS:
241 case USB_TRANSFER_INTERRUPT:
242 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
243 endpoint_list_remove_ep(list, ohci_ep);
244 OHCI_SET(instance->registers->control, C_PLE | C_IE);
245 break;
246 default:
247 break;
248 }
249}
250
251/** Add USB transfer to the schedule.
252 *
253 * @param[in] instance OHCI hc driver structure.
254 * @param[in] batch Batch representing the transfer.
255 * @return Error code.
256 */
257int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
258{
259 assert(hcd);
260 hc_t *instance = hcd->private_data;
261 assert(instance);
262
263 /* Check for root hub communication */
264 if (batch->ep->address == ohci_rh_get_address(&instance->rh)) {
265 usb_log_debug("OHCI root hub request.\n");
266 return ohci_rh_schedule(&instance->rh, batch);
267 }
268 ohci_transfer_batch_t *ohci_batch = ohci_transfer_batch_get(batch);
269 if (!ohci_batch)
270 return ENOMEM;
271
272 fibril_mutex_lock(&instance->guard);
273 list_append(&ohci_batch->link, &instance->pending_batches);
274 ohci_transfer_batch_commit(ohci_batch);
275
276 /* Control and bulk schedules need a kick to start working */
277 switch (batch->ep->transfer_type)
278 {
279 case USB_TRANSFER_CONTROL:
280 OHCI_SET(instance->registers->command_status, CS_CLF);
281 break;
282 case USB_TRANSFER_BULK:
283 OHCI_SET(instance->registers->command_status, CS_BLF);
284 break;
285 default:
286 break;
287 }
288 fibril_mutex_unlock(&instance->guard);
289 return EOK;
290}
291
292/** Interrupt handling routine
293 *
294 * @param[in] instance OHCI hc driver structure.
295 * @param[in] status Value of the status register at the time of interrupt.
296 */
297void hc_interrupt(hc_t *instance, uint32_t status)
298{
299 status = OHCI_RD(status);
300 assert(instance);
301 if ((status & ~I_SF) == 0) /* ignore sof status */
302 return;
303 usb_log_debug2("OHCI(%p) interrupt: %x.\n", instance, status);
304 if (status & I_RHSC)
305 ohci_rh_interrupt(&instance->rh);
306
307 if (status & I_WDH) {
308 fibril_mutex_lock(&instance->guard);
309 usb_log_debug2("HCCA: %p-%#" PRIx32 " (%p).\n", instance->hcca,
310 OHCI_RD(instance->registers->hcca),
311 (void *) addr_to_phys(instance->hcca));
312 usb_log_debug2("Periodic current: %#" PRIx32 ".\n",
313 OHCI_RD(instance->registers->periodic_current));
314
315 link_t *current = list_first(&instance->pending_batches);
316 while (current && current != &instance->pending_batches.head) {
317 link_t *next = current->next;
318 ohci_transfer_batch_t *batch =
319 ohci_transfer_batch_from_link(current);
320
321 if (ohci_transfer_batch_is_complete(batch)) {
322 list_remove(current);
323 ohci_transfer_batch_finish_dispose(batch);
324 }
325
326 current = next;
327 }
328 fibril_mutex_unlock(&instance->guard);
329 }
330
331 if (status & I_UE) {
332 usb_log_fatal("Error like no other!\n");
333 hc_start(instance);
334 }
335
336}
337
338/** Check status register regularly
339 *
340 * @param[in] instance OHCI hc driver structure.
341 * @return Error code
342 */
343int interrupt_emulator(hc_t *instance)
344{
345 assert(instance);
346 usb_log_info("Started interrupt emulator.\n");
347 while (1) {
348 const uint32_t status = instance->registers->interrupt_status;
349 instance->registers->interrupt_status = status;
350 hc_interrupt(instance, status);
351 async_usleep(10000);
352 }
353 return EOK;
354}
355
356/** Turn off any (BIOS)driver that might be in control of the device.
357 *
358 * This function implements routines described in chapter 5.1.1.3 of the OHCI
359 * specification (page 40, pdf page 54).
360 *
361 * @param[in] instance OHCI hc driver structure.
362 */
363void hc_gain_control(hc_t *instance)
364{
365 assert(instance);
366
367 usb_log_debug("Requesting OHCI control.\n");
368 if (OHCI_RD(instance->registers->revision) & R_LEGACY_FLAG) {
369 /* Turn off legacy emulation, it should be enough to zero
370 * the lowest bit, but it caused problems. Thus clear all
371 * except GateA20 (causes restart on some hw).
372 * See page 145 of the specs for details.
373 */
374 volatile uint32_t *ohci_emulation_reg =
375 (uint32_t*)((char*)instance->registers + LEGACY_REGS_OFFSET);
376 usb_log_debug("OHCI legacy register %p: %x.\n",
377 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
378 /* Zero everything but A20State */
379 OHCI_CLR(*ohci_emulation_reg, ~0x100);
380 usb_log_debug(
381 "OHCI legacy register (should be 0 or 0x100) %p: %x.\n",
382 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
383 }
384
385 /* Interrupt routing enabled => smm driver is active */
386 if (OHCI_RD(instance->registers->control) & C_IR) {
387 usb_log_debug("SMM driver: request ownership change.\n");
388 OHCI_SET(instance->registers->command_status, CS_OCR);
389 /* Hope that SMM actually knows its stuff or we can hang here */
390 while (OHCI_RD(instance->registers->control & C_IR)) {
391 async_usleep(1000);
392 }
393 usb_log_info("SMM driver: Ownership taken.\n");
394 C_HCFS_SET(instance->registers->control, C_HCFS_RESET);
395 async_usleep(50000);
396 return;
397 }
398
399 const unsigned hc_status = C_HCFS_GET(instance->registers->control);
400 /* Interrupt routing disabled && status != USB_RESET => BIOS active */
401 if (hc_status != C_HCFS_RESET) {
402 usb_log_debug("BIOS driver found.\n");
403 if (hc_status == C_HCFS_OPERATIONAL) {
404 usb_log_info("BIOS driver: HC operational.\n");
405 return;
406 }
407 /* HC is suspended assert resume for 20ms */
408 C_HCFS_SET(instance->registers->control, C_HCFS_RESUME);
409 async_usleep(20000);
410 usb_log_info("BIOS driver: HC resumed.\n");
411 return;
412 }
413
414 /* HC is in reset (hw startup) => no other driver
415 * maintain reset for at least the time specified in USB spec (50 ms)*/
416 usb_log_debug("Host controller found in reset state.\n");
417 async_usleep(50000);
418}
419
420/** OHCI hw initialization routine.
421 *
422 * @param[in] instance OHCI hc driver structure.
423 */
424void hc_start(hc_t *instance)
425{
426 /* OHCI guide page 42 */
427 assert(instance);
428 usb_log_debug2("Started hc initialization routine.\n");
429
430 /* Save contents of fm_interval register */
431 const uint32_t fm_interval = OHCI_RD(instance->registers->fm_interval);
432 usb_log_debug2("Old value of HcFmInterval: %x.\n", fm_interval);
433
434 /* Reset hc */
435 usb_log_debug2("HC reset.\n");
436 size_t time = 0;
437 OHCI_WR(instance->registers->command_status, CS_HCR);
438 while (OHCI_RD(instance->registers->command_status) & CS_HCR) {
439 async_usleep(10);
440 time += 10;
441 }
442 usb_log_debug2("HC reset complete in %zu us.\n", time);
443
444 /* Restore fm_interval */
445 OHCI_WR(instance->registers->fm_interval, fm_interval);
446 assert((OHCI_RD(instance->registers->command_status) & CS_HCR) == 0);
447
448 /* hc is now in suspend state */
449 usb_log_debug2("HC should be in suspend state(%x).\n",
450 OHCI_RD(instance->registers->control));
451
452 /* Use HCCA */
453 OHCI_WR(instance->registers->hcca, addr_to_phys(instance->hcca));
454
455 /* Use queues */
456 OHCI_WR(instance->registers->bulk_head,
457 instance->lists[USB_TRANSFER_BULK].list_head_pa);
458 usb_log_debug2("Bulk HEAD set to: %p (%#" PRIx32 ").\n",
459 instance->lists[USB_TRANSFER_BULK].list_head,
460 instance->lists[USB_TRANSFER_BULK].list_head_pa);
461
462 OHCI_WR(instance->registers->control_head,
463 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
464 usb_log_debug2("Control HEAD set to: %p (%#" PRIx32 ").\n",
465 instance->lists[USB_TRANSFER_CONTROL].list_head,
466 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
467
468 /* Enable queues */
469 OHCI_SET(instance->registers->control, (C_PLE | C_IE | C_CLE | C_BLE));
470 usb_log_debug("Queues enabled(%x).\n",
471 OHCI_RD(instance->registers->control));
472
473 /* Enable interrupts */
474 OHCI_WR(instance->registers->interrupt_enable, OHCI_USED_INTERRUPTS);
475 usb_log_debug("Enabled interrupts: %x.\n",
476 OHCI_RD(instance->registers->interrupt_enable));
477 OHCI_WR(instance->registers->interrupt_enable, I_MI);
478
479 /* Set periodic start to 90% */
480 const uint32_t frame_length =
481 (fm_interval >> FMI_FI_SHIFT) & FMI_FI_MASK;
482 OHCI_WR(instance->registers->periodic_start,
483 ((frame_length / 10) * 9) & PS_MASK << PS_SHIFT);
484 usb_log_debug2("All periodic start set to: %x(%u - 90%% of %d).\n",
485 OHCI_RD(instance->registers->periodic_start),
486 OHCI_RD(instance->registers->periodic_start), frame_length);
487 C_HCFS_SET(instance->registers->control, C_HCFS_OPERATIONAL);
488 usb_log_debug("OHCI HC up and running (ctl_reg=0x%x).\n",
489 OHCI_RD(instance->registers->control));
490}
491
492/** Initialize schedule queues
493 *
494 * @param[in] instance OHCI hc driver structure
495 * @return Error code
496 */
497int hc_init_transfer_lists(hc_t *instance)
498{
499 assert(instance);
500#define SETUP_ENDPOINT_LIST(type) \
501do { \
502 const char *name = usb_str_transfer_type(type); \
503 int ret = endpoint_list_init(&instance->lists[type], name); \
504 if (ret != EOK) { \
505 usb_log_error("Failed to setup %s endpoint list: %s.\n", \
506 name, str_error(ret)); \
507 endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]);\
508 endpoint_list_fini(&instance->lists[USB_TRANSFER_INTERRUPT]); \
509 endpoint_list_fini(&instance->lists[USB_TRANSFER_CONTROL]); \
510 endpoint_list_fini(&instance->lists[USB_TRANSFER_BULK]); \
511 return ret; \
512 } \
513} while (0)
514
515 SETUP_ENDPOINT_LIST(USB_TRANSFER_ISOCHRONOUS);
516 SETUP_ENDPOINT_LIST(USB_TRANSFER_INTERRUPT);
517 SETUP_ENDPOINT_LIST(USB_TRANSFER_CONTROL);
518 SETUP_ENDPOINT_LIST(USB_TRANSFER_BULK);
519#undef SETUP_ENDPOINT_LIST
520 endpoint_list_set_next(&instance->lists[USB_TRANSFER_INTERRUPT],
521 &instance->lists[USB_TRANSFER_ISOCHRONOUS]);
522
523 return EOK;
524}
525
526/** Initialize memory structures used by the OHCI hcd.
527 *
528 * @param[in] instance OHCI hc driver structure.
529 * @return Error code.
530 */
531int hc_init_memory(hc_t *instance)
532{
533 assert(instance);
534
535 memset(&instance->rh, 0, sizeof(instance->rh));
536 /* Init queues */
537 const int ret = hc_init_transfer_lists(instance);
538 if (ret != EOK) {
539 return ret;
540 }
541
542 /*Init HCCA */
543 instance->hcca = hcca_get();
544 if (instance->hcca == NULL)
545 return ENOMEM;
546 usb_log_debug2("OHCI HCCA initialized at %p.\n", instance->hcca);
547
548 for (unsigned i = 0; i < HCCA_INT_EP_COUNT; ++i) {
549 hcca_set_int_ep(instance->hcca, i,
550 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
551 }
552 usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").\n",
553 instance->lists[USB_TRANSFER_INTERRUPT].list_head,
554 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
555
556 return EOK;
557}
558
559/**
560 * @}
561 */
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