source: mainline/uspace/drv/bus/usb/ohci/hc.c@ d5c1051

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since d5c1051 was 68e5406, checked in by Jiří Zárevúcky <zarevucky.jiri@…>, 8 years ago

Separate return value from error code in gen_irq_code*() and hcd_send_batch_sync().
  • Property mode set to 100644
File size: 16.9 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbohcihc
30 * @{
31 */
32/** @file
33 * @brief OHCI Host controller driver routines
34 */
35
36#include <assert.h>
37#include <async.h>
38#include <errno.h>
39#include <macros.h>
40#include <mem.h>
41#include <stdlib.h>
42#include <str_error.h>
43#include <stddef.h>
44#include <stdint.h>
45
46#include <usb/debug.h>
47#include <usb/usb.h>
48
49#include "ohci_endpoint.h"
50#include "ohci_batch.h"
51
52#include "hc.h"
53
54#define OHCI_USED_INTERRUPTS \
55 (I_SO | I_WDH | I_UE | I_RHSC)
56
57static const irq_pio_range_t ohci_pio_ranges[] = {
58 {
59 .base = 0,
60 .size = sizeof(ohci_regs_t)
61 }
62};
63
64static const irq_cmd_t ohci_irq_commands[] = {
65 {
66 .cmd = CMD_PIO_READ_32,
67 .dstarg = 1,
68 .addr = NULL
69 },
70 {
71 .cmd = CMD_AND,
72 .srcarg = 1,
73 .dstarg = 2,
74 .value = 0
75 },
76 {
77 .cmd = CMD_PREDICATE,
78 .srcarg = 2,
79 .value = 2
80 },
81 {
82 .cmd = CMD_PIO_WRITE_A_32,
83 .srcarg = 1,
84 .addr = NULL
85 },
86 {
87 .cmd = CMD_ACCEPT
88 }
89};
90
91static void hc_gain_control(hc_t *instance);
92static void hc_start(hc_t *instance);
93static int hc_init_transfer_lists(hc_t *instance);
94static int hc_init_memory(hc_t *instance);
95
96/** Generate IRQ code.
97 * @param[out] ranges PIO ranges buffer.
98 * @param[in] ranges_size Size of the ranges buffer (bytes).
99 * @param[out] cmds Commands buffer.
100 * @param[in] cmds_size Size of the commands buffer (bytes).
101 * @param[in] hw_res Device's resources.
102 *
103 * @return Error code.
104 */
105int ohci_hc_gen_irq_code(irq_code_t *code, const hw_res_list_parsed_t *hw_res, int *irq)
106{
107 assert(code);
108 assert(hw_res);
109
110 if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
111 return EINVAL;
112
113 const addr_range_t regs = hw_res->mem_ranges.ranges[0];
114
115 if (RNGSZ(regs) < sizeof(ohci_regs_t))
116 return EOVERFLOW;
117
118 code->ranges = malloc(sizeof(ohci_pio_ranges));
119 if (code->ranges == NULL)
120 return ENOMEM;
121
122 code->cmds = malloc(sizeof(ohci_irq_commands));
123 if (code->cmds == NULL) {
124 free(code->ranges);
125 return ENOMEM;
126 }
127
128 code->rangecount = ARRAY_SIZE(ohci_pio_ranges);
129 code->cmdcount = ARRAY_SIZE(ohci_irq_commands);
130
131 memcpy(code->ranges, ohci_pio_ranges, sizeof(ohci_pio_ranges));
132 code->ranges[0].base = RNGABS(regs);
133
134 memcpy(code->cmds, ohci_irq_commands, sizeof(ohci_irq_commands));
135 ohci_regs_t *registers = (ohci_regs_t *) RNGABSPTR(regs);
136 code->cmds[0].addr = (void *) &registers->interrupt_status;
137 code->cmds[3].addr = (void *) &registers->interrupt_status;
138 OHCI_WR(code->cmds[1].value, OHCI_USED_INTERRUPTS);
139
140 usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.\n",
141 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
142
143 *irq = hw_res->irqs.irqs[0];
144 return EOK;
145}
146
147/** Initialize OHCI hc driver structure
148 *
149 * @param[in] instance Memory place for the structure.
150 * @param[in] regs Device's resources
151 * @param[in] interrupts True if w interrupts should be used
152 * @return Error code
153 */
154int hc_init(hc_t *instance, const hw_res_list_parsed_t *hw_res, bool interrupts)
155{
156 assert(instance);
157 assert(hw_res);
158 if (hw_res->mem_ranges.count != 1 ||
159 hw_res->mem_ranges.ranges[0].size < sizeof(ohci_regs_t))
160 return EINVAL;
161
162 int ret = pio_enable_range(&hw_res->mem_ranges.ranges[0],
163 (void **) &instance->registers);
164 if (ret != EOK) {
165 usb_log_error("Failed to gain access to registers: %s.\n",
166 str_error(ret));
167 return ret;
168 }
169 usb_log_debug("Device registers at %" PRIx64 " (%zuB) accessible.\n",
170 hw_res->mem_ranges.ranges[0].address.absolute,
171 hw_res->mem_ranges.ranges[0].size);
172
173 list_initialize(&instance->pending_batches);
174 fibril_mutex_initialize(&instance->guard);
175 instance->hw_interrupts = interrupts;
176
177 ret = hc_init_memory(instance);
178 if (ret != EOK) {
179 usb_log_error("Failed to create OHCI memory structures: %s.\n",
180 str_error(ret));
181 // TODO: We should disable pio access here
182 return ret;
183 }
184
185 hc_gain_control(instance);
186
187 ohci_rh_init(&instance->rh, instance->registers, "ohci rh");
188 hc_start(instance);
189
190 return EOK;
191}
192
193/** Safely dispose host controller internal structures
194 *
195 * @param[in] instance Host controller structure to use.
196 */
197void hc_fini(hc_t *instance)
198{
199 assert(instance);
200 /* TODO: implement*/
201};
202
203void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
204{
205 assert(instance);
206 assert(ep);
207
208 endpoint_list_t *list = &instance->lists[ep->transfer_type];
209 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
210 assert(list);
211 assert(ohci_ep);
212
213 /* Enqueue ep */
214 switch (ep->transfer_type) {
215 case USB_TRANSFER_CONTROL:
216 OHCI_CLR(instance->registers->control, C_CLE);
217 endpoint_list_add_ep(list, ohci_ep);
218 OHCI_WR(instance->registers->control_current, 0);
219 OHCI_SET(instance->registers->control, C_CLE);
220 break;
221 case USB_TRANSFER_BULK:
222 OHCI_CLR(instance->registers->control, C_BLE);
223 endpoint_list_add_ep(list, ohci_ep);
224 OHCI_WR(instance->registers->bulk_current, 0);
225 OHCI_SET(instance->registers->control, C_BLE);
226 break;
227 case USB_TRANSFER_ISOCHRONOUS:
228 case USB_TRANSFER_INTERRUPT:
229 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
230 endpoint_list_add_ep(list, ohci_ep);
231 OHCI_SET(instance->registers->control, C_PLE | C_IE);
232 break;
233 }
234}
235
236void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
237{
238 assert(instance);
239 assert(ep);
240
241 /* Dequeue ep */
242 endpoint_list_t *list = &instance->lists[ep->transfer_type];
243 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
244
245 assert(list);
246 assert(ohci_ep);
247 switch (ep->transfer_type) {
248 case USB_TRANSFER_CONTROL:
249 OHCI_CLR(instance->registers->control, C_CLE);
250 endpoint_list_remove_ep(list, ohci_ep);
251 OHCI_WR(instance->registers->control_current, 0);
252 OHCI_SET(instance->registers->control, C_CLE);
253 break;
254 case USB_TRANSFER_BULK:
255 OHCI_CLR(instance->registers->control, C_BLE);
256 endpoint_list_remove_ep(list, ohci_ep);
257 OHCI_WR(instance->registers->bulk_current, 0);
258 OHCI_SET(instance->registers->control, C_BLE);
259 break;
260 case USB_TRANSFER_ISOCHRONOUS:
261 case USB_TRANSFER_INTERRUPT:
262 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
263 endpoint_list_remove_ep(list, ohci_ep);
264 OHCI_SET(instance->registers->control, C_PLE | C_IE);
265 break;
266 default:
267 break;
268 }
269}
270
271int ohci_hc_status(hcd_t *hcd, uint32_t *status)
272{
273 assert(hcd);
274 assert(status);
275 hc_t *instance = hcd_get_driver_data(hcd);
276 assert(instance);
277
278 if (instance->registers){
279 *status = OHCI_RD(instance->registers->interrupt_status);
280 OHCI_WR(instance->registers->interrupt_status, *status);
281 }
282 return EOK;
283}
284
285/** Add USB transfer to the schedule.
286 *
287 * @param[in] hcd HCD driver structure.
288 * @param[in] batch Batch representing the transfer.
289 * @return Error code.
290 */
291int ohci_hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
292{
293 assert(hcd);
294 hc_t *instance = hcd_get_driver_data(hcd);
295 assert(instance);
296
297 /* Check for root hub communication */
298 if (batch->ep->address == ohci_rh_get_address(&instance->rh)) {
299 usb_log_debug("OHCI root hub request.\n");
300 return ohci_rh_schedule(&instance->rh, batch);
301 }
302 ohci_transfer_batch_t *ohci_batch = ohci_transfer_batch_get(batch);
303 if (!ohci_batch)
304 return ENOMEM;
305
306 fibril_mutex_lock(&instance->guard);
307 list_append(&ohci_batch->link, &instance->pending_batches);
308 ohci_transfer_batch_commit(ohci_batch);
309
310 /* Control and bulk schedules need a kick to start working */
311 switch (batch->ep->transfer_type)
312 {
313 case USB_TRANSFER_CONTROL:
314 OHCI_SET(instance->registers->command_status, CS_CLF);
315 break;
316 case USB_TRANSFER_BULK:
317 OHCI_SET(instance->registers->command_status, CS_BLF);
318 break;
319 default:
320 break;
321 }
322 fibril_mutex_unlock(&instance->guard);
323 return EOK;
324}
325
326/** Interrupt handling routine
327 *
328 * @param[in] hcd HCD driver structure.
329 * @param[in] status Value of the status register at the time of interrupt.
330 */
331void ohci_hc_interrupt(hcd_t *hcd, uint32_t status)
332{
333 assert(hcd);
334 hc_t *instance = hcd_get_driver_data(hcd);
335 status = OHCI_RD(status);
336 assert(instance);
337 if ((status & ~I_SF) == 0) /* ignore sof status */
338 return;
339 usb_log_debug2("OHCI(%p) interrupt: %x.\n", instance, status);
340 if (status & I_RHSC)
341 ohci_rh_interrupt(&instance->rh);
342
343 if (status & I_WDH) {
344 fibril_mutex_lock(&instance->guard);
345 usb_log_debug2("HCCA: %p-%#" PRIx32 " (%p).\n", instance->hcca,
346 OHCI_RD(instance->registers->hcca),
347 (void *) addr_to_phys(instance->hcca));
348 usb_log_debug2("Periodic current: %#" PRIx32 ".\n",
349 OHCI_RD(instance->registers->periodic_current));
350
351 link_t *current = list_first(&instance->pending_batches);
352 while (current && current != &instance->pending_batches.head) {
353 link_t *next = current->next;
354 ohci_transfer_batch_t *batch =
355 ohci_transfer_batch_from_link(current);
356
357 if (ohci_transfer_batch_is_complete(batch)) {
358 list_remove(current);
359 ohci_transfer_batch_finish_dispose(batch);
360 }
361
362 current = next;
363 }
364 fibril_mutex_unlock(&instance->guard);
365 }
366
367 if (status & I_UE) {
368 usb_log_fatal("Error like no other!\n");
369 hc_start(instance);
370 }
371
372}
373
374/** Turn off any (BIOS)driver that might be in control of the device.
375 *
376 * This function implements routines described in chapter 5.1.1.3 of the OHCI
377 * specification (page 40, pdf page 54).
378 *
379 * @param[in] instance OHCI hc driver structure.
380 */
381void hc_gain_control(hc_t *instance)
382{
383 assert(instance);
384
385 usb_log_debug("Requesting OHCI control.\n");
386 if (OHCI_RD(instance->registers->revision) & R_LEGACY_FLAG) {
387 /* Turn off legacy emulation, it should be enough to zero
388 * the lowest bit, but it caused problems. Thus clear all
389 * except GateA20 (causes restart on some hw).
390 * See page 145 of the specs for details.
391 */
392 volatile uint32_t *ohci_emulation_reg =
393 (uint32_t*)((char*)instance->registers + LEGACY_REGS_OFFSET);
394 usb_log_debug("OHCI legacy register %p: %x.\n",
395 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
396 /* Zero everything but A20State */
397 // TODO: should we ack interrupts before doing this?
398 OHCI_CLR(*ohci_emulation_reg, ~0x100);
399 usb_log_debug(
400 "OHCI legacy register (should be 0 or 0x100) %p: %x.\n",
401 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
402 }
403
404 /* Interrupt routing enabled => smm driver is active */
405 if (OHCI_RD(instance->registers->control) & C_IR) {
406 usb_log_debug("SMM driver: request ownership change.\n");
407 // TODO: should we ack interrupts before doing this?
408 OHCI_SET(instance->registers->command_status, CS_OCR);
409 /* Hope that SMM actually knows its stuff or we can hang here */
410 while (OHCI_RD(instance->registers->control) & C_IR) {
411 async_usleep(1000);
412 }
413 usb_log_info("SMM driver: Ownership taken.\n");
414 C_HCFS_SET(instance->registers->control, C_HCFS_RESET);
415 async_usleep(50000);
416 return;
417 }
418
419 const unsigned hc_status = C_HCFS_GET(instance->registers->control);
420 /* Interrupt routing disabled && status != USB_RESET => BIOS active */
421 if (hc_status != C_HCFS_RESET) {
422 usb_log_debug("BIOS driver found.\n");
423 if (hc_status == C_HCFS_OPERATIONAL) {
424 usb_log_info("BIOS driver: HC operational.\n");
425 return;
426 }
427 /* HC is suspended assert resume for 20ms */
428 C_HCFS_SET(instance->registers->control, C_HCFS_RESUME);
429 async_usleep(20000);
430 usb_log_info("BIOS driver: HC resumed.\n");
431 return;
432 }
433
434 /* HC is in reset (hw startup) => no other driver
435 * maintain reset for at least the time specified in USB spec (50 ms)*/
436 usb_log_debug("Host controller found in reset state.\n");
437 async_usleep(50000);
438}
439
440/** OHCI hw initialization routine.
441 *
442 * @param[in] instance OHCI hc driver structure.
443 */
444void hc_start(hc_t *instance)
445{
446 /* OHCI guide page 42 */
447 assert(instance);
448 usb_log_debug2("Started hc initialization routine.\n");
449
450 /* Save contents of fm_interval register */
451 const uint32_t fm_interval = OHCI_RD(instance->registers->fm_interval);
452 usb_log_debug2("Old value of HcFmInterval: %x.\n", fm_interval);
453
454 /* Reset hc */
455 usb_log_debug2("HC reset.\n");
456 size_t time = 0;
457 OHCI_WR(instance->registers->command_status, CS_HCR);
458 while (OHCI_RD(instance->registers->command_status) & CS_HCR) {
459 async_usleep(10);
460 time += 10;
461 }
462 usb_log_debug2("HC reset complete in %zu us.\n", time);
463
464 /* Restore fm_interval */
465 OHCI_WR(instance->registers->fm_interval, fm_interval);
466 assert((OHCI_RD(instance->registers->command_status) & CS_HCR) == 0);
467
468 /* hc is now in suspend state */
469 usb_log_debug2("HC should be in suspend state(%x).\n",
470 OHCI_RD(instance->registers->control));
471
472 /* Use HCCA */
473 OHCI_WR(instance->registers->hcca, addr_to_phys(instance->hcca));
474
475 /* Use queues */
476 OHCI_WR(instance->registers->bulk_head,
477 instance->lists[USB_TRANSFER_BULK].list_head_pa);
478 usb_log_debug2("Bulk HEAD set to: %p (%#" PRIx32 ").\n",
479 instance->lists[USB_TRANSFER_BULK].list_head,
480 instance->lists[USB_TRANSFER_BULK].list_head_pa);
481
482 OHCI_WR(instance->registers->control_head,
483 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
484 usb_log_debug2("Control HEAD set to: %p (%#" PRIx32 ").\n",
485 instance->lists[USB_TRANSFER_CONTROL].list_head,
486 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
487
488 /* Enable queues */
489 OHCI_SET(instance->registers->control, (C_PLE | C_IE | C_CLE | C_BLE));
490 usb_log_debug("Queues enabled(%x).\n",
491 OHCI_RD(instance->registers->control));
492
493 /* Enable interrupts */
494 if (instance->hw_interrupts) {
495 OHCI_WR(instance->registers->interrupt_enable,
496 OHCI_USED_INTERRUPTS);
497 usb_log_debug("Enabled interrupts: %x.\n",
498 OHCI_RD(instance->registers->interrupt_enable));
499 OHCI_WR(instance->registers->interrupt_enable, I_MI);
500 }
501
502 /* Set periodic start to 90% */
503 const uint32_t frame_length =
504 (fm_interval >> FMI_FI_SHIFT) & FMI_FI_MASK;
505 OHCI_WR(instance->registers->periodic_start,
506 ((frame_length / 10) * 9) & PS_MASK << PS_SHIFT);
507 usb_log_debug2("All periodic start set to: %x(%u - 90%% of %d).\n",
508 OHCI_RD(instance->registers->periodic_start),
509 OHCI_RD(instance->registers->periodic_start), frame_length);
510 C_HCFS_SET(instance->registers->control, C_HCFS_OPERATIONAL);
511 usb_log_debug("OHCI HC up and running (ctl_reg=0x%x).\n",
512 OHCI_RD(instance->registers->control));
513}
514
515/** Initialize schedule queues
516 *
517 * @param[in] instance OHCI hc driver structure
518 * @return Error code
519 */
520int hc_init_transfer_lists(hc_t *instance)
521{
522 assert(instance);
523#define SETUP_ENDPOINT_LIST(type) \
524do { \
525 const char *name = usb_str_transfer_type(type); \
526 const int ret = endpoint_list_init(&instance->lists[type], name); \
527 if (ret != EOK) { \
528 usb_log_error("Failed to setup %s endpoint list: %s.\n", \
529 name, str_error(ret)); \
530 endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]);\
531 endpoint_list_fini(&instance->lists[USB_TRANSFER_INTERRUPT]); \
532 endpoint_list_fini(&instance->lists[USB_TRANSFER_CONTROL]); \
533 endpoint_list_fini(&instance->lists[USB_TRANSFER_BULK]); \
534 return ret; \
535 } \
536} while (0)
537
538 SETUP_ENDPOINT_LIST(USB_TRANSFER_ISOCHRONOUS);
539 SETUP_ENDPOINT_LIST(USB_TRANSFER_INTERRUPT);
540 SETUP_ENDPOINT_LIST(USB_TRANSFER_CONTROL);
541 SETUP_ENDPOINT_LIST(USB_TRANSFER_BULK);
542#undef SETUP_ENDPOINT_LIST
543 endpoint_list_set_next(&instance->lists[USB_TRANSFER_INTERRUPT],
544 &instance->lists[USB_TRANSFER_ISOCHRONOUS]);
545
546 return EOK;
547}
548
549/** Initialize memory structures used by the OHCI hcd.
550 *
551 * @param[in] instance OHCI hc driver structure.
552 * @return Error code.
553 */
554int hc_init_memory(hc_t *instance)
555{
556 assert(instance);
557
558 memset(&instance->rh, 0, sizeof(instance->rh));
559 /* Init queues */
560 const int ret = hc_init_transfer_lists(instance);
561 if (ret != EOK) {
562 return ret;
563 }
564
565 /*Init HCCA */
566 instance->hcca = hcca_get();
567 if (instance->hcca == NULL)
568 return ENOMEM;
569 usb_log_debug2("OHCI HCCA initialized at %p.\n", instance->hcca);
570
571 for (unsigned i = 0; i < HCCA_INT_EP_COUNT; ++i) {
572 hcca_set_int_ep(instance->hcca, i,
573 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
574 }
575 usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").\n",
576 instance->lists[USB_TRANSFER_INTERRUPT].list_head,
577 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
578
579 return EOK;
580}
581
582/**
583 * @}
584 */
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