source: mainline/uspace/drv/bus/usb/ohci/hc.c@ ba4a03a5

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ba4a03a5 was ba4a03a5, checked in by Jan Vesely <jano.vesely@…>, 12 years ago

usb host: Use all hw resources when generating irq code.
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File size: 16.4 KB
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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbohcihc
30 * @{
31 */
32/** @file
33 * @brief OHCI Host controller driver routines
34 */
35
36#include <assert.h>
37#include <async.h>
38#include <errno.h>
39#include <macros.h>
40#include <mem.h>
41#include <stdlib.h>
42#include <str_error.h>
43#include <sys/types.h>
44
45#include <usb/debug.h>
46#include <usb/usb.h>
47
48#include "ohci_endpoint.h"
49#include "ohci_batch.h"
50#include "utils/malloc32.h"
51
52#include "hc.h"
53
54#define OHCI_USED_INTERRUPTS \
55 (I_SO | I_WDH | I_UE | I_RHSC)
56
57static const irq_pio_range_t ohci_pio_ranges[] = {
58 {
59 .base = 0,
60 .size = sizeof(ohci_regs_t)
61 }
62};
63
64static const irq_cmd_t ohci_irq_commands[] = {
65 {
66 .cmd = CMD_PIO_READ_32,
67 .dstarg = 1,
68 .addr = NULL
69 },
70 {
71 .cmd = CMD_AND,
72 .srcarg = 1,
73 .dstarg = 2,
74 .value = 0
75 },
76 {
77 .cmd = CMD_PREDICATE,
78 .srcarg = 2,
79 .value = 2
80 },
81 {
82 .cmd = CMD_PIO_WRITE_A_32,
83 .srcarg = 1,
84 .addr = NULL
85 },
86 {
87 .cmd = CMD_ACCEPT
88 }
89};
90
91static void hc_gain_control(hc_t *instance);
92static void hc_start(hc_t *instance);
93static int hc_init_transfer_lists(hc_t *instance);
94static int hc_init_memory(hc_t *instance);
95static int interrupt_emulator(hc_t *instance);
96
97/** Generate IRQ code.
98 * @param[out] ranges PIO ranges buffer.
99 * @param[in] ranges_size Size of the ranges buffer (bytes).
100 * @param[out] cmds Commands buffer.
101 * @param[in] cmds_size Size of the commands buffer (bytes).
102 * @param[in] hw_res Device's resources.
103 *
104 * @return Error code.
105 */
106int hc_gen_irq_code(irq_code_t *code, const hw_res_list_parsed_t *hw_res)
107{
108 assert(code);
109 assert(hw_res);
110
111 if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
112 return EINVAL;
113
114 const addr_range_t regs = hw_res->mem_ranges.ranges[0];
115
116 if (RNGSZ(regs) < sizeof(ohci_regs_t))
117 return EOVERFLOW;
118
119 code->ranges = malloc(sizeof(ohci_pio_ranges));
120 if (code->ranges == NULL)
121 return ENOMEM;
122
123 code->cmds = malloc(sizeof(ohci_irq_commands));
124 if (code->cmds == NULL) {
125 free(code->ranges);
126 return ENOMEM;
127 }
128
129 code->rangecount = ARRAY_SIZE(ohci_pio_ranges);
130 code->cmdcount = ARRAY_SIZE(ohci_irq_commands);
131
132 memcpy(code->ranges, ohci_pio_ranges, sizeof(ohci_pio_ranges));
133 code->ranges[0].base = RNGABS(regs);
134
135 memcpy(code->cmds, ohci_irq_commands, sizeof(ohci_irq_commands));
136 ohci_regs_t *registers = (ohci_regs_t *) RNGABSPTR(regs);
137 code->cmds[0].addr = (void *) &registers->interrupt_status;
138 code->cmds[3].addr = (void *) &registers->interrupt_status;
139 OHCI_WR(code->cmds[1].value, OHCI_USED_INTERRUPTS);
140
141 usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.\n",
142 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
143
144 return hw_res->irqs.irqs[0];
145}
146
147/** Initialize OHCI hc driver structure
148 *
149 * @param[in] instance Memory place for the structure.
150 * @param[in] regs Device's I/O registers range.
151 * @param[in] interrupts True if w interrupts should be used
152 * @return Error code
153 */
154int hc_init(hc_t *instance, addr_range_t *regs, bool interrupts)
155{
156 assert(instance);
157
158 int ret = pio_enable_range(regs, (void **) &instance->registers);
159 if (ret != EOK) {
160 usb_log_error("Failed to gain access to device registers: %s.\n",
161 str_error(ret));
162 return ret;
163 }
164
165 list_initialize(&instance->pending_batches);
166 fibril_mutex_initialize(&instance->guard);
167
168 ret = hc_init_memory(instance);
169 if (ret != EOK) {
170 usb_log_error("Failed to create OHCI memory structures: %s.\n",
171 str_error(ret));
172 return ret;
173 }
174
175 hc_gain_control(instance);
176
177 if (!interrupts) {
178 instance->interrupt_emulator =
179 fibril_create((int(*)(void*))interrupt_emulator, instance);
180 fibril_add_ready(instance->interrupt_emulator);
181 }
182
183 ohci_rh_init(&instance->rh, instance->registers, "ohci rh");
184 hc_start(instance);
185
186 return EOK;
187}
188
189void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
190{
191 assert(instance);
192 assert(ep);
193
194 endpoint_list_t *list = &instance->lists[ep->transfer_type];
195 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
196 assert(list);
197 assert(ohci_ep);
198
199 /* Enqueue ep */
200 switch (ep->transfer_type) {
201 case USB_TRANSFER_CONTROL:
202 OHCI_CLR(instance->registers->control, C_CLE);
203 endpoint_list_add_ep(list, ohci_ep);
204 OHCI_WR(instance->registers->control_current, 0);
205 OHCI_SET(instance->registers->control, C_CLE);
206 break;
207 case USB_TRANSFER_BULK:
208 OHCI_CLR(instance->registers->control, C_BLE);
209 endpoint_list_add_ep(list, ohci_ep);
210 OHCI_WR(instance->registers->bulk_current, 0);
211 OHCI_SET(instance->registers->control, C_BLE);
212 break;
213 case USB_TRANSFER_ISOCHRONOUS:
214 case USB_TRANSFER_INTERRUPT:
215 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
216 endpoint_list_add_ep(list, ohci_ep);
217 OHCI_SET(instance->registers->control, C_PLE | C_IE);
218 break;
219 }
220}
221
222void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
223{
224 assert(instance);
225 assert(ep);
226
227 /* Dequeue ep */
228 endpoint_list_t *list = &instance->lists[ep->transfer_type];
229 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
230
231 assert(list);
232 assert(ohci_ep);
233 switch (ep->transfer_type) {
234 case USB_TRANSFER_CONTROL:
235 OHCI_CLR(instance->registers->control, C_CLE);
236 endpoint_list_remove_ep(list, ohci_ep);
237 OHCI_WR(instance->registers->control_current, 0);
238 OHCI_SET(instance->registers->control, C_CLE);
239 break;
240 case USB_TRANSFER_BULK:
241 OHCI_CLR(instance->registers->control, C_BLE);
242 endpoint_list_remove_ep(list, ohci_ep);
243 OHCI_WR(instance->registers->bulk_current, 0);
244 OHCI_SET(instance->registers->control, C_BLE);
245 break;
246 case USB_TRANSFER_ISOCHRONOUS:
247 case USB_TRANSFER_INTERRUPT:
248 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
249 endpoint_list_remove_ep(list, ohci_ep);
250 OHCI_SET(instance->registers->control, C_PLE | C_IE);
251 break;
252 default:
253 break;
254 }
255}
256
257/** Add USB transfer to the schedule.
258 *
259 * @param[in] instance OHCI hc driver structure.
260 * @param[in] batch Batch representing the transfer.
261 * @return Error code.
262 */
263int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
264{
265 assert(hcd);
266 hc_t *instance = hcd->driver.data;
267 assert(instance);
268
269 /* Check for root hub communication */
270 if (batch->ep->address == ohci_rh_get_address(&instance->rh)) {
271 usb_log_debug("OHCI root hub request.\n");
272 return ohci_rh_schedule(&instance->rh, batch);
273 }
274 ohci_transfer_batch_t *ohci_batch = ohci_transfer_batch_get(batch);
275 if (!ohci_batch)
276 return ENOMEM;
277
278 fibril_mutex_lock(&instance->guard);
279 list_append(&ohci_batch->link, &instance->pending_batches);
280 ohci_transfer_batch_commit(ohci_batch);
281
282 /* Control and bulk schedules need a kick to start working */
283 switch (batch->ep->transfer_type)
284 {
285 case USB_TRANSFER_CONTROL:
286 OHCI_SET(instance->registers->command_status, CS_CLF);
287 break;
288 case USB_TRANSFER_BULK:
289 OHCI_SET(instance->registers->command_status, CS_BLF);
290 break;
291 default:
292 break;
293 }
294 fibril_mutex_unlock(&instance->guard);
295 return EOK;
296}
297
298/** Interrupt handling routine
299 *
300 * @param[in] instance OHCI hc driver structure.
301 * @param[in] status Value of the status register at the time of interrupt.
302 */
303void hc_interrupt(hc_t *instance, uint32_t status)
304{
305 status = OHCI_RD(status);
306 assert(instance);
307 if ((status & ~I_SF) == 0) /* ignore sof status */
308 return;
309 usb_log_debug2("OHCI(%p) interrupt: %x.\n", instance, status);
310 if (status & I_RHSC)
311 ohci_rh_interrupt(&instance->rh);
312
313 if (status & I_WDH) {
314 fibril_mutex_lock(&instance->guard);
315 usb_log_debug2("HCCA: %p-%#" PRIx32 " (%p).\n", instance->hcca,
316 OHCI_RD(instance->registers->hcca),
317 (void *) addr_to_phys(instance->hcca));
318 usb_log_debug2("Periodic current: %#" PRIx32 ".\n",
319 OHCI_RD(instance->registers->periodic_current));
320
321 link_t *current = list_first(&instance->pending_batches);
322 while (current && current != &instance->pending_batches.head) {
323 link_t *next = current->next;
324 ohci_transfer_batch_t *batch =
325 ohci_transfer_batch_from_link(current);
326
327 if (ohci_transfer_batch_is_complete(batch)) {
328 list_remove(current);
329 ohci_transfer_batch_finish_dispose(batch);
330 }
331
332 current = next;
333 }
334 fibril_mutex_unlock(&instance->guard);
335 }
336
337 if (status & I_UE) {
338 usb_log_fatal("Error like no other!\n");
339 hc_start(instance);
340 }
341
342}
343
344/** Check status register regularly
345 *
346 * @param[in] instance OHCI hc driver structure.
347 * @return Error code
348 */
349int interrupt_emulator(hc_t *instance)
350{
351 assert(instance);
352 usb_log_info("Started interrupt emulator.\n");
353 while (1) {
354 const uint32_t status = instance->registers->interrupt_status;
355 instance->registers->interrupt_status = status;
356 hc_interrupt(instance, status);
357 async_usleep(10000);
358 }
359 return EOK;
360}
361
362/** Turn off any (BIOS)driver that might be in control of the device.
363 *
364 * This function implements routines described in chapter 5.1.1.3 of the OHCI
365 * specification (page 40, pdf page 54).
366 *
367 * @param[in] instance OHCI hc driver structure.
368 */
369void hc_gain_control(hc_t *instance)
370{
371 assert(instance);
372
373 usb_log_debug("Requesting OHCI control.\n");
374 if (OHCI_RD(instance->registers->revision) & R_LEGACY_FLAG) {
375 /* Turn off legacy emulation, it should be enough to zero
376 * the lowest bit, but it caused problems. Thus clear all
377 * except GateA20 (causes restart on some hw).
378 * See page 145 of the specs for details.
379 */
380 volatile uint32_t *ohci_emulation_reg =
381 (uint32_t*)((char*)instance->registers + LEGACY_REGS_OFFSET);
382 usb_log_debug("OHCI legacy register %p: %x.\n",
383 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
384 /* Zero everything but A20State */
385 OHCI_CLR(*ohci_emulation_reg, ~0x100);
386 usb_log_debug(
387 "OHCI legacy register (should be 0 or 0x100) %p: %x.\n",
388 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
389 }
390
391 /* Interrupt routing enabled => smm driver is active */
392 if (OHCI_RD(instance->registers->control) & C_IR) {
393 usb_log_debug("SMM driver: request ownership change.\n");
394 OHCI_SET(instance->registers->command_status, CS_OCR);
395 /* Hope that SMM actually knows its stuff or we can hang here */
396 while (OHCI_RD(instance->registers->control) & C_IR) {
397 async_usleep(1000);
398 }
399 usb_log_info("SMM driver: Ownership taken.\n");
400 C_HCFS_SET(instance->registers->control, C_HCFS_RESET);
401 async_usleep(50000);
402 return;
403 }
404
405 const unsigned hc_status = C_HCFS_GET(instance->registers->control);
406 /* Interrupt routing disabled && status != USB_RESET => BIOS active */
407 if (hc_status != C_HCFS_RESET) {
408 usb_log_debug("BIOS driver found.\n");
409 if (hc_status == C_HCFS_OPERATIONAL) {
410 usb_log_info("BIOS driver: HC operational.\n");
411 return;
412 }
413 /* HC is suspended assert resume for 20ms */
414 C_HCFS_SET(instance->registers->control, C_HCFS_RESUME);
415 async_usleep(20000);
416 usb_log_info("BIOS driver: HC resumed.\n");
417 return;
418 }
419
420 /* HC is in reset (hw startup) => no other driver
421 * maintain reset for at least the time specified in USB spec (50 ms)*/
422 usb_log_debug("Host controller found in reset state.\n");
423 async_usleep(50000);
424}
425
426/** OHCI hw initialization routine.
427 *
428 * @param[in] instance OHCI hc driver structure.
429 */
430void hc_start(hc_t *instance)
431{
432 /* OHCI guide page 42 */
433 assert(instance);
434 usb_log_debug2("Started hc initialization routine.\n");
435
436 /* Save contents of fm_interval register */
437 const uint32_t fm_interval = OHCI_RD(instance->registers->fm_interval);
438 usb_log_debug2("Old value of HcFmInterval: %x.\n", fm_interval);
439
440 /* Reset hc */
441 usb_log_debug2("HC reset.\n");
442 size_t time = 0;
443 OHCI_WR(instance->registers->command_status, CS_HCR);
444 while (OHCI_RD(instance->registers->command_status) & CS_HCR) {
445 async_usleep(10);
446 time += 10;
447 }
448 usb_log_debug2("HC reset complete in %zu us.\n", time);
449
450 /* Restore fm_interval */
451 OHCI_WR(instance->registers->fm_interval, fm_interval);
452 assert((OHCI_RD(instance->registers->command_status) & CS_HCR) == 0);
453
454 /* hc is now in suspend state */
455 usb_log_debug2("HC should be in suspend state(%x).\n",
456 OHCI_RD(instance->registers->control));
457
458 /* Use HCCA */
459 OHCI_WR(instance->registers->hcca, addr_to_phys(instance->hcca));
460
461 /* Use queues */
462 OHCI_WR(instance->registers->bulk_head,
463 instance->lists[USB_TRANSFER_BULK].list_head_pa);
464 usb_log_debug2("Bulk HEAD set to: %p (%#" PRIx32 ").\n",
465 instance->lists[USB_TRANSFER_BULK].list_head,
466 instance->lists[USB_TRANSFER_BULK].list_head_pa);
467
468 OHCI_WR(instance->registers->control_head,
469 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
470 usb_log_debug2("Control HEAD set to: %p (%#" PRIx32 ").\n",
471 instance->lists[USB_TRANSFER_CONTROL].list_head,
472 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
473
474 /* Enable queues */
475 OHCI_SET(instance->registers->control, (C_PLE | C_IE | C_CLE | C_BLE));
476 usb_log_debug("Queues enabled(%x).\n",
477 OHCI_RD(instance->registers->control));
478
479 /* Enable interrupts */
480 OHCI_WR(instance->registers->interrupt_enable, OHCI_USED_INTERRUPTS);
481 usb_log_debug("Enabled interrupts: %x.\n",
482 OHCI_RD(instance->registers->interrupt_enable));
483 OHCI_WR(instance->registers->interrupt_enable, I_MI);
484
485 /* Set periodic start to 90% */
486 const uint32_t frame_length =
487 (fm_interval >> FMI_FI_SHIFT) & FMI_FI_MASK;
488 OHCI_WR(instance->registers->periodic_start,
489 ((frame_length / 10) * 9) & PS_MASK << PS_SHIFT);
490 usb_log_debug2("All periodic start set to: %x(%u - 90%% of %d).\n",
491 OHCI_RD(instance->registers->periodic_start),
492 OHCI_RD(instance->registers->periodic_start), frame_length);
493 C_HCFS_SET(instance->registers->control, C_HCFS_OPERATIONAL);
494 usb_log_debug("OHCI HC up and running (ctl_reg=0x%x).\n",
495 OHCI_RD(instance->registers->control));
496}
497
498/** Initialize schedule queues
499 *
500 * @param[in] instance OHCI hc driver structure
501 * @return Error code
502 */
503int hc_init_transfer_lists(hc_t *instance)
504{
505 assert(instance);
506#define SETUP_ENDPOINT_LIST(type) \
507do { \
508 const char *name = usb_str_transfer_type(type); \
509 const int ret = endpoint_list_init(&instance->lists[type], name); \
510 if (ret != EOK) { \
511 usb_log_error("Failed to setup %s endpoint list: %s.\n", \
512 name, str_error(ret)); \
513 endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]);\
514 endpoint_list_fini(&instance->lists[USB_TRANSFER_INTERRUPT]); \
515 endpoint_list_fini(&instance->lists[USB_TRANSFER_CONTROL]); \
516 endpoint_list_fini(&instance->lists[USB_TRANSFER_BULK]); \
517 return ret; \
518 } \
519} while (0)
520
521 SETUP_ENDPOINT_LIST(USB_TRANSFER_ISOCHRONOUS);
522 SETUP_ENDPOINT_LIST(USB_TRANSFER_INTERRUPT);
523 SETUP_ENDPOINT_LIST(USB_TRANSFER_CONTROL);
524 SETUP_ENDPOINT_LIST(USB_TRANSFER_BULK);
525#undef SETUP_ENDPOINT_LIST
526 endpoint_list_set_next(&instance->lists[USB_TRANSFER_INTERRUPT],
527 &instance->lists[USB_TRANSFER_ISOCHRONOUS]);
528
529 return EOK;
530}
531
532/** Initialize memory structures used by the OHCI hcd.
533 *
534 * @param[in] instance OHCI hc driver structure.
535 * @return Error code.
536 */
537int hc_init_memory(hc_t *instance)
538{
539 assert(instance);
540
541 memset(&instance->rh, 0, sizeof(instance->rh));
542 /* Init queues */
543 const int ret = hc_init_transfer_lists(instance);
544 if (ret != EOK) {
545 return ret;
546 }
547
548 /*Init HCCA */
549 instance->hcca = hcca_get();
550 if (instance->hcca == NULL)
551 return ENOMEM;
552 usb_log_debug2("OHCI HCCA initialized at %p.\n", instance->hcca);
553
554 for (unsigned i = 0; i < HCCA_INT_EP_COUNT; ++i) {
555 hcca_set_int_ep(instance->hcca, i,
556 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
557 }
558 usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").\n",
559 instance->lists[USB_TRANSFER_INTERRUPT].list_head,
560 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
561
562 return EOK;
563}
564
565/**
566 * @}
567 */
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