source: mainline/uspace/drv/bus/usb/ohci/hc.c@ 7c3fb9b

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 7c3fb9b was 7c3fb9b, checked in by Jiri Svoboda <jiri@…>, 7 years ago

Fix block comment formatting (ccheck).
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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * Copyright (c) 2018 Ondrej Hlavaty
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/** @addtogroup drvusbohcihc
31 * @{
32 */
33/** @file
34 * @brief OHCI Host controller driver routines
35 */
36
37#include <assert.h>
38#include <async.h>
39#include <errno.h>
40#include <macros.h>
41#include <mem.h>
42#include <stdlib.h>
43#include <str_error.h>
44#include <stddef.h>
45#include <stdint.h>
46
47#include <usb/debug.h>
48#include <usb/host/utility.h>
49#include <usb/usb.h>
50
51#include "ohci_bus.h"
52#include "ohci_batch.h"
53
54#include "hc.h"
55
56#define OHCI_USED_INTERRUPTS \
57 (I_SO | I_WDH | I_UE | I_RHSC)
58
59static const irq_pio_range_t ohci_pio_ranges[] = {
60 {
61 .base = 0,
62 .size = sizeof(ohci_regs_t)
63 }
64};
65
66static const irq_cmd_t ohci_irq_commands[] = {
67 {
68 .cmd = CMD_PIO_READ_32,
69 .dstarg = 1,
70 .addr = NULL
71 },
72 {
73 .cmd = CMD_AND,
74 .srcarg = 1,
75 .dstarg = 2,
76 .value = 0
77 },
78 {
79 .cmd = CMD_PREDICATE,
80 .srcarg = 2,
81 .value = 2
82 },
83 {
84 .cmd = CMD_PIO_WRITE_A_32,
85 .srcarg = 1,
86 .addr = NULL
87 },
88 {
89 .cmd = CMD_ACCEPT
90 }
91};
92
93static errno_t hc_init_transfer_lists(hc_t *instance);
94static errno_t hc_init_memory(hc_t *instance);
95
96/** Generate IRQ code.
97 * @param[out] ranges PIO ranges buffer.
98 * @param[in] ranges_size Size of the ranges buffer (bytes).
99 * @param[out] cmds Commands buffer.
100 * @param[in] cmds_size Size of the commands buffer (bytes).
101 * @param[in] hw_res Device's resources.
102 *
103 * @return Error code.
104 */
105errno_t hc_gen_irq_code(irq_code_t *code, hc_device_t *hcd, const hw_res_list_parsed_t *hw_res, int *irq)
106{
107 assert(code);
108 assert(hw_res);
109
110 if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
111 return EINVAL;
112
113 const addr_range_t regs = hw_res->mem_ranges.ranges[0];
114
115 if (RNGSZ(regs) < sizeof(ohci_regs_t))
116 return EOVERFLOW;
117
118 code->ranges = malloc(sizeof(ohci_pio_ranges));
119 if (code->ranges == NULL)
120 return ENOMEM;
121
122 code->cmds = malloc(sizeof(ohci_irq_commands));
123 if (code->cmds == NULL) {
124 free(code->ranges);
125 return ENOMEM;
126 }
127
128 code->rangecount = ARRAY_SIZE(ohci_pio_ranges);
129 code->cmdcount = ARRAY_SIZE(ohci_irq_commands);
130
131 memcpy(code->ranges, ohci_pio_ranges, sizeof(ohci_pio_ranges));
132 code->ranges[0].base = RNGABS(regs);
133
134 memcpy(code->cmds, ohci_irq_commands, sizeof(ohci_irq_commands));
135 ohci_regs_t *registers = (ohci_regs_t *) RNGABSPTR(regs);
136 code->cmds[0].addr = (void *) &registers->interrupt_status;
137 code->cmds[3].addr = (void *) &registers->interrupt_status;
138 OHCI_WR(code->cmds[1].value, OHCI_USED_INTERRUPTS);
139
140 usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.",
141 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
142
143 *irq = hw_res->irqs.irqs[0];
144 return EOK;
145}
146
147/** Initialize OHCI hc driver structure
148 *
149 * @param[in] instance Memory place for the structure.
150 * @param[in] regs Device's resources
151 * @param[in] interrupts True if w interrupts should be used
152 * @return Error code
153 */
154errno_t hc_add(hc_device_t *hcd, const hw_res_list_parsed_t *hw_res)
155{
156 hc_t *instance = hcd_to_hc(hcd);
157 assert(hw_res);
158 if (hw_res->mem_ranges.count != 1 ||
159 hw_res->mem_ranges.ranges[0].size < sizeof(ohci_regs_t))
160 return EINVAL;
161
162 errno_t ret = pio_enable_range(&hw_res->mem_ranges.ranges[0],
163 (void **) &instance->registers);
164 if (ret != EOK) {
165 usb_log_error("Failed to gain access to registers: %s.",
166 str_error(ret));
167 return ret;
168 }
169 usb_log_debug("Device registers at %" PRIx64 " (%zuB) accessible.",
170 hw_res->mem_ranges.ranges[0].address.absolute,
171 hw_res->mem_ranges.ranges[0].size);
172
173 list_initialize(&instance->pending_endpoints);
174 fibril_mutex_initialize(&instance->guard);
175
176 ret = hc_init_memory(instance);
177 if (ret != EOK) {
178 usb_log_error("Failed to create OHCI memory structures: %s.",
179 str_error(ret));
180 // TODO: We should disable pio access here
181 return ret;
182 }
183
184 return EOK;
185}
186
187/** Safely dispose host controller internal structures
188 *
189 * @param[in] instance Host controller structure to use.
190 */
191int hc_gone(hc_device_t *instance)
192{
193 assert(instance);
194 /* TODO: implement*/
195 return ENOTSUP;
196}
197
198void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
199{
200 assert(instance);
201 assert(ep);
202
203 endpoint_list_t *list = &instance->lists[ep->transfer_type];
204 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
205 assert(list);
206 assert(ohci_ep);
207
208 /* Enqueue ep */
209 switch (ep->transfer_type) {
210 case USB_TRANSFER_CONTROL:
211 OHCI_CLR(instance->registers->control, C_CLE);
212 endpoint_list_add_ep(list, ohci_ep);
213 OHCI_WR(instance->registers->control_current, 0);
214 OHCI_SET(instance->registers->control, C_CLE);
215 break;
216 case USB_TRANSFER_BULK:
217 OHCI_CLR(instance->registers->control, C_BLE);
218 endpoint_list_add_ep(list, ohci_ep);
219 OHCI_WR(instance->registers->bulk_current, 0);
220 OHCI_SET(instance->registers->control, C_BLE);
221 break;
222 case USB_TRANSFER_ISOCHRONOUS:
223 case USB_TRANSFER_INTERRUPT:
224 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
225 endpoint_list_add_ep(list, ohci_ep);
226 OHCI_SET(instance->registers->control, C_PLE | C_IE);
227 break;
228 }
229}
230
231void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
232{
233 assert(instance);
234 assert(ep);
235
236 /* Dequeue ep */
237 endpoint_list_t *list = &instance->lists[ep->transfer_type];
238 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
239
240 assert(list);
241 assert(ohci_ep);
242 switch (ep->transfer_type) {
243 case USB_TRANSFER_CONTROL:
244 OHCI_CLR(instance->registers->control, C_CLE);
245 endpoint_list_remove_ep(list, ohci_ep);
246 OHCI_WR(instance->registers->control_current, 0);
247 OHCI_SET(instance->registers->control, C_CLE);
248 break;
249 case USB_TRANSFER_BULK:
250 OHCI_CLR(instance->registers->control, C_BLE);
251 endpoint_list_remove_ep(list, ohci_ep);
252 OHCI_WR(instance->registers->bulk_current, 0);
253 OHCI_SET(instance->registers->control, C_BLE);
254 break;
255 case USB_TRANSFER_ISOCHRONOUS:
256 case USB_TRANSFER_INTERRUPT:
257 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
258 endpoint_list_remove_ep(list, ohci_ep);
259 OHCI_SET(instance->registers->control, C_PLE | C_IE);
260 break;
261 default:
262 break;
263 }
264}
265
266errno_t ohci_hc_status(bus_t *bus_base, uint32_t *status)
267{
268 assert(bus_base);
269 assert(status);
270
271 ohci_bus_t *bus = (ohci_bus_t *) bus_base;
272 hc_t *hc = bus->hc;
273 assert(hc);
274
275 if (hc->registers) {
276 *status = OHCI_RD(hc->registers->interrupt_status);
277 OHCI_WR(hc->registers->interrupt_status, *status);
278 }
279 return EOK;
280}
281
282/** Add USB transfer to the schedule.
283 *
284 * @param[in] hcd HCD driver structure.
285 * @param[in] batch Batch representing the transfer.
286 * @return Error code.
287 */
288errno_t ohci_hc_schedule(usb_transfer_batch_t *batch)
289{
290 assert(batch);
291
292 ohci_bus_t *bus = (ohci_bus_t *) endpoint_get_bus(batch->ep);
293 hc_t *hc = bus->hc;
294 assert(hc);
295
296 /* Check for root hub communication */
297 if (batch->target.address == ohci_rh_get_address(&hc->rh)) {
298 usb_log_debug("OHCI root hub request.");
299 return ohci_rh_schedule(&hc->rh, batch);
300 }
301
302 endpoint_t *ep = batch->ep;
303 ohci_endpoint_t *const ohci_ep = ohci_endpoint_get(ep);
304 ohci_transfer_batch_t *ohci_batch = ohci_transfer_batch_get(batch);
305 int err;
306
307 if ((err = ohci_transfer_batch_prepare(ohci_batch)))
308 return err;
309
310 fibril_mutex_lock(&hc->guard);
311 if ((err = endpoint_activate_locked(ep, batch))) {
312 fibril_mutex_unlock(&hc->guard);
313 return err;
314 }
315
316 ohci_transfer_batch_commit(ohci_batch);
317 list_append(&ohci_ep->pending_link, &hc->pending_endpoints);
318 fibril_mutex_unlock(&hc->guard);
319
320 /* Control and bulk schedules need a kick to start working */
321 switch (batch->ep->transfer_type) {
322 case USB_TRANSFER_CONTROL:
323 OHCI_SET(hc->registers->command_status, CS_CLF);
324 break;
325 case USB_TRANSFER_BULK:
326 OHCI_SET(hc->registers->command_status, CS_BLF);
327 break;
328 default:
329 break;
330 }
331
332 return EOK;
333}
334
335/** Interrupt handling routine
336 *
337 * @param[in] hcd HCD driver structure.
338 * @param[in] status Value of the status register at the time of interrupt.
339 */
340void ohci_hc_interrupt(bus_t *bus_base, uint32_t status)
341{
342 assert(bus_base);
343
344 ohci_bus_t *bus = (ohci_bus_t *) bus_base;
345 hc_t *hc = bus->hc;
346 assert(hc);
347
348 status = OHCI_RD(status);
349 assert(hc);
350 if ((status & ~I_SF) == 0) /* ignore sof status */
351 return;
352 usb_log_debug2("OHCI(%p) interrupt: %x.", hc, status);
353 if (status & I_RHSC)
354 ohci_rh_interrupt(&hc->rh);
355
356 if (status & I_WDH) {
357 fibril_mutex_lock(&hc->guard);
358 usb_log_debug2("HCCA: %p-%#" PRIx32 " (%p).", hc->hcca,
359 OHCI_RD(hc->registers->hcca),
360 (void *) addr_to_phys(hc->hcca));
361 usb_log_debug2("Periodic current: %#" PRIx32 ".",
362 OHCI_RD(hc->registers->periodic_current));
363
364 list_foreach_safe(hc->pending_endpoints, current, next) {
365 ohci_endpoint_t *ep =
366 list_get_instance(current, ohci_endpoint_t, pending_link);
367
368 ohci_transfer_batch_t *batch =
369 ohci_transfer_batch_get(ep->base.active_batch);
370 assert(batch);
371
372 if (ohci_transfer_batch_check_completed(batch)) {
373 endpoint_deactivate_locked(&ep->base);
374 list_remove(current);
375 hc_reset_toggles(&batch->base, &ohci_ep_toggle_reset);
376 usb_transfer_batch_finish(&batch->base);
377 }
378 }
379 fibril_mutex_unlock(&hc->guard);
380 }
381
382 if (status & I_UE) {
383 usb_log_fatal("Error like no other!");
384 hc_start(&hc->base);
385 }
386
387}
388
389/** Turn off any (BIOS)driver that might be in control of the device.
390 *
391 * This function implements routines described in chapter 5.1.1.3 of the OHCI
392 * specification (page 40, pdf page 54).
393 *
394 * @param[in] instance OHCI hc driver structure.
395 */
396int hc_gain_control(hc_device_t *hcd)
397{
398 hc_t *instance = hcd_to_hc(hcd);
399
400 usb_log_debug("Requesting OHCI control.");
401 if (OHCI_RD(instance->registers->revision) & R_LEGACY_FLAG) {
402 /*
403 * Turn off legacy emulation, it should be enough to zero
404 * the lowest bit, but it caused problems. Thus clear all
405 * except GateA20 (causes restart on some hw).
406 * See page 145 of the specs for details.
407 */
408 volatile uint32_t *ohci_emulation_reg =
409 (uint32_t *)((char *)instance->registers + LEGACY_REGS_OFFSET);
410 usb_log_debug("OHCI legacy register %p: %x.",
411 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
412 /* Zero everything but A20State */
413 // TODO: should we ack interrupts before doing this?
414 OHCI_CLR(*ohci_emulation_reg, ~0x100);
415 usb_log_debug(
416 "OHCI legacy register (should be 0 or 0x100) %p: %x.",
417 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
418 }
419
420 /* Interrupt routing enabled => smm driver is active */
421 if (OHCI_RD(instance->registers->control) & C_IR) {
422 usb_log_debug("SMM driver: request ownership change.");
423 // TODO: should we ack interrupts before doing this?
424 OHCI_SET(instance->registers->command_status, CS_OCR);
425 /* Hope that SMM actually knows its stuff or we can hang here */
426 while (OHCI_RD(instance->registers->control) & C_IR) {
427 async_usleep(1000);
428 }
429 usb_log_info("SMM driver: Ownership taken.");
430 C_HCFS_SET(instance->registers->control, C_HCFS_RESET);
431 async_usleep(50000);
432 return EOK;
433 }
434
435 const unsigned hc_status = C_HCFS_GET(instance->registers->control);
436 /* Interrupt routing disabled && status != USB_RESET => BIOS active */
437 if (hc_status != C_HCFS_RESET) {
438 usb_log_debug("BIOS driver found.");
439 if (hc_status == C_HCFS_OPERATIONAL) {
440 usb_log_info("BIOS driver: HC operational.");
441 return EOK;
442 }
443 /* HC is suspended assert resume for 20ms */
444 C_HCFS_SET(instance->registers->control, C_HCFS_RESUME);
445 async_usleep(20000);
446 usb_log_info("BIOS driver: HC resumed.");
447 return EOK;
448 }
449
450 /*
451 * HC is in reset (hw startup) => no other driver
452 * maintain reset for at least the time specified in USB spec (50 ms)
453 */
454 usb_log_debug("Host controller found in reset state.");
455 async_usleep(50000);
456 return EOK;
457}
458
459/** OHCI hw initialization routine.
460 *
461 * @param[in] instance OHCI hc driver structure.
462 */
463int hc_start(hc_device_t *hcd)
464{
465 hc_t *instance = hcd_to_hc(hcd);
466 ohci_rh_init(&instance->rh, instance->registers, &instance->guard, "ohci rh");
467
468 /* OHCI guide page 42 */
469 assert(instance);
470 usb_log_debug2("Started hc initialization routine.");
471
472 /* Save contents of fm_interval register */
473 const uint32_t fm_interval = OHCI_RD(instance->registers->fm_interval);
474 usb_log_debug2("Old value of HcFmInterval: %x.", fm_interval);
475
476 /* Reset hc */
477 usb_log_debug2("HC reset.");
478 size_t time = 0;
479 OHCI_WR(instance->registers->command_status, CS_HCR);
480 while (OHCI_RD(instance->registers->command_status) & CS_HCR) {
481 async_usleep(10);
482 time += 10;
483 }
484 usb_log_debug2("HC reset complete in %zu us.", time);
485
486 /* Restore fm_interval */
487 OHCI_WR(instance->registers->fm_interval, fm_interval);
488 assert((OHCI_RD(instance->registers->command_status) & CS_HCR) == 0);
489
490 /* hc is now in suspend state */
491 usb_log_debug2("HC should be in suspend state(%x).",
492 OHCI_RD(instance->registers->control));
493
494 /* Use HCCA */
495 OHCI_WR(instance->registers->hcca, addr_to_phys(instance->hcca));
496
497 /* Use queues */
498 OHCI_WR(instance->registers->bulk_head,
499 instance->lists[USB_TRANSFER_BULK].list_head_pa);
500 usb_log_debug2("Bulk HEAD set to: %p (%#" PRIx32 ").",
501 instance->lists[USB_TRANSFER_BULK].list_head,
502 instance->lists[USB_TRANSFER_BULK].list_head_pa);
503
504 OHCI_WR(instance->registers->control_head,
505 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
506 usb_log_debug2("Control HEAD set to: %p (%#" PRIx32 ").",
507 instance->lists[USB_TRANSFER_CONTROL].list_head,
508 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
509
510 /* Enable queues */
511 OHCI_SET(instance->registers->control, (C_PLE | C_IE | C_CLE | C_BLE));
512 usb_log_debug("Queues enabled(%x).",
513 OHCI_RD(instance->registers->control));
514
515 /* Enable interrupts */
516 if (CAP_HANDLE_VALID(instance->base.irq_handle)) {
517 OHCI_WR(instance->registers->interrupt_enable,
518 OHCI_USED_INTERRUPTS);
519 usb_log_debug("Enabled interrupts: %x.",
520 OHCI_RD(instance->registers->interrupt_enable));
521 OHCI_WR(instance->registers->interrupt_enable, I_MI);
522 }
523
524 /* Set periodic start to 90% */
525 const uint32_t frame_length =
526 (fm_interval >> FMI_FI_SHIFT) & FMI_FI_MASK;
527 OHCI_WR(instance->registers->periodic_start,
528 ((frame_length / 10) * 9) & PS_MASK << PS_SHIFT);
529 usb_log_debug2("All periodic start set to: %x(%u - 90%% of %d).",
530 OHCI_RD(instance->registers->periodic_start),
531 OHCI_RD(instance->registers->periodic_start), frame_length);
532 C_HCFS_SET(instance->registers->control, C_HCFS_OPERATIONAL);
533 usb_log_debug("OHCI HC up and running (ctl_reg=0x%x).",
534 OHCI_RD(instance->registers->control));
535
536 return EOK;
537}
538
539/**
540 * Setup roothub as a virtual hub.
541 */
542int hc_setup_roothub(hc_device_t *hcd)
543{
544 return hc_setup_virtual_root_hub(hcd, USB_SPEED_FULL);
545}
546
547/** Initialize schedule queues
548 *
549 * @param[in] instance OHCI hc driver structure
550 * @return Error code
551 */
552errno_t hc_init_transfer_lists(hc_t *instance)
553{
554 assert(instance);
555#define SETUP_ENDPOINT_LIST(type) \
556do { \
557 const char *name = usb_str_transfer_type(type); \
558 const errno_t ret = endpoint_list_init(&instance->lists[type], name); \
559 if (ret != EOK) { \
560 usb_log_error("Failed to setup %s endpoint list: %s.", \
561 name, str_error(ret)); \
562 endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]);\
563 endpoint_list_fini(&instance->lists[USB_TRANSFER_INTERRUPT]); \
564 endpoint_list_fini(&instance->lists[USB_TRANSFER_CONTROL]); \
565 endpoint_list_fini(&instance->lists[USB_TRANSFER_BULK]); \
566 return ret; \
567 } \
568} while (0)
569
570 SETUP_ENDPOINT_LIST(USB_TRANSFER_ISOCHRONOUS);
571 SETUP_ENDPOINT_LIST(USB_TRANSFER_INTERRUPT);
572 SETUP_ENDPOINT_LIST(USB_TRANSFER_CONTROL);
573 SETUP_ENDPOINT_LIST(USB_TRANSFER_BULK);
574#undef SETUP_ENDPOINT_LIST
575 endpoint_list_set_next(&instance->lists[USB_TRANSFER_INTERRUPT],
576 &instance->lists[USB_TRANSFER_ISOCHRONOUS]);
577
578 return EOK;
579}
580
581/** Initialize memory structures used by the OHCI hcd.
582 *
583 * @param[in] instance OHCI hc driver structure.
584 * @return Error code.
585 */
586errno_t hc_init_memory(hc_t *instance)
587{
588 assert(instance);
589
590 memset(&instance->rh, 0, sizeof(instance->rh));
591 /* Init queues */
592 errno_t ret = hc_init_transfer_lists(instance);
593 if (ret != EOK) {
594 return ret;
595 }
596
597 /*Init HCCA */
598 instance->hcca = hcca_get();
599 if (instance->hcca == NULL)
600 return ENOMEM;
601 usb_log_debug2("OHCI HCCA initialized at %p.", instance->hcca);
602
603 for (unsigned i = 0; i < HCCA_INT_EP_COUNT; ++i) {
604 hcca_set_int_ep(instance->hcca, i,
605 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
606 }
607 usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").",
608 instance->lists[USB_TRANSFER_INTERRUPT].list_head,
609 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
610
611 if ((ret = ohci_bus_init(&instance->bus, instance))) {
612 usb_log_error("HC(%p): Failed to setup bus : %s",
613 instance, str_error(ret));
614 return ret;
615 }
616
617 hc_device_setup(&instance->base, (bus_t *) &instance->bus);
618
619 return EOK;
620}
621
622/**
623 * @}
624 */
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