source: mainline/uspace/drv/bus/usb/ohci/hc.c@ 772a172

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 772a172 was 772a172, checked in by Jan Vesely <jano.vesely@…>, 12 years ago

ohci,uhci: Switch to library provided irq setup routine.
  • Property mode set to 100644
File size: 16.0 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbohcihc
30 * @{
31 */
32/** @file
33 * @brief OHCI Host controller driver routines
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <adt/list.h>
39#include <libarch/ddi.h>
40
41#include <usb/debug.h>
42#include <usb/usb.h>
43
44#include "macros.h"
45#include "hc.h"
46#include "ohci_endpoint.h"
47
48#define OHCI_USED_INTERRUPTS \
49 (I_SO | I_WDH | I_UE | I_RHSC)
50
51static const irq_pio_range_t ohci_pio_ranges[] = {
52 {
53 .base = 0,
54 .size = sizeof(ohci_regs_t)
55 }
56};
57
58static const irq_cmd_t ohci_irq_commands[] = {
59 {
60 .cmd = CMD_PIO_READ_32,
61 .dstarg = 1,
62 .addr = NULL
63 },
64 {
65 .cmd = CMD_AND,
66 .srcarg = 1,
67 .dstarg = 2,
68 .value = 0
69 },
70 {
71 .cmd = CMD_PREDICATE,
72 .srcarg = 2,
73 .value = 2
74 },
75 {
76 .cmd = CMD_PIO_WRITE_A_32,
77 .srcarg = 1,
78 .addr = NULL
79 },
80 {
81 .cmd = CMD_ACCEPT
82 }
83};
84
85static void hc_gain_control(hc_t *instance);
86static void hc_start(hc_t *instance);
87static int hc_init_transfer_lists(hc_t *instance);
88static int hc_init_memory(hc_t *instance);
89static int interrupt_emulator(hc_t *instance);
90
91/** Generate IRQ code.
92 * @param[out] ranges PIO ranges buffer.
93 * @param[in] ranges_size Size of the ranges buffer (bytes).
94 * @param[out] cmds Commands buffer.
95 * @param[in] cmds_size Size of the commands buffer (bytes).
96 * @param[in] regs Device's register range.
97 *
98 * @return Error code.
99 */
100int hc_gen_irq_code(irq_code_t *code, addr_range_t *regs)
101{
102 assert(code);
103 if (RNGSZ(*regs) < sizeof(ohci_regs_t))
104 return EOVERFLOW;
105
106 code->ranges = malloc(sizeof(ohci_pio_ranges));
107 if (code->ranges == NULL)
108 return ENOMEM;
109
110 code->cmds = malloc(sizeof(ohci_irq_commands));
111 if (code->cmds == NULL) {
112 free(code->ranges);
113 return ENOMEM;
114 }
115
116 code->rangecount = ARRAY_SIZE(ohci_pio_ranges);
117 code->cmdcount = ARRAY_SIZE(ohci_irq_commands);
118
119 memcpy(code->ranges, ohci_pio_ranges, sizeof(ohci_pio_ranges));
120 code->ranges[0].base = RNGABS(*regs);
121
122 memcpy(code->cmds, ohci_irq_commands, sizeof(ohci_irq_commands));
123 ohci_regs_t *registers = (ohci_regs_t *) RNGABSPTR(*regs);
124 code->cmds[0].addr = (void *) &registers->interrupt_status;
125 code->cmds[3].addr = (void *) &registers->interrupt_status;
126 OHCI_WR(code->cmds[1].value, OHCI_USED_INTERRUPTS);
127
128 return EOK;
129}
130
131/** Initialize OHCI hc driver structure
132 *
133 * @param[in] instance Memory place for the structure.
134 * @param[in] regs Device's I/O registers range.
135 * @param[in] interrupts True if w interrupts should be used
136 * @return Error code
137 */
138int hc_init(hc_t *instance, addr_range_t *regs, bool interrupts)
139{
140 assert(instance);
141
142 int ret = pio_enable_range(regs, (void **) &instance->registers);
143 if (ret != EOK) {
144 usb_log_error("Failed to gain access to device registers: %s.\n",
145 str_error(ret));
146 return ret;
147 }
148
149 list_initialize(&instance->pending_batches);
150 fibril_mutex_initialize(&instance->guard);
151
152 ret = hc_init_memory(instance);
153 if (ret != EOK) {
154 usb_log_error("Failed to create OHCI memory structures: %s.\n",
155 str_error(ret));
156 return ret;
157 }
158
159 hc_gain_control(instance);
160
161 if (!interrupts) {
162 instance->interrupt_emulator =
163 fibril_create((int(*)(void*))interrupt_emulator, instance);
164 fibril_add_ready(instance->interrupt_emulator);
165 }
166
167 ohci_rh_init(&instance->rh, instance->registers, "ohci rh");
168 hc_start(instance);
169
170 return EOK;
171}
172
173void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
174{
175 assert(instance);
176 assert(ep);
177
178 endpoint_list_t *list = &instance->lists[ep->transfer_type];
179 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
180 assert(list);
181 assert(ohci_ep);
182
183 /* Enqueue ep */
184 switch (ep->transfer_type) {
185 case USB_TRANSFER_CONTROL:
186 OHCI_CLR(instance->registers->control, C_CLE);
187 endpoint_list_add_ep(list, ohci_ep);
188 OHCI_WR(instance->registers->control_current, 0);
189 OHCI_SET(instance->registers->control, C_CLE);
190 break;
191 case USB_TRANSFER_BULK:
192 OHCI_CLR(instance->registers->control, C_BLE);
193 endpoint_list_add_ep(list, ohci_ep);
194 OHCI_WR(instance->registers->bulk_current, 0);
195 OHCI_SET(instance->registers->control, C_BLE);
196 break;
197 case USB_TRANSFER_ISOCHRONOUS:
198 case USB_TRANSFER_INTERRUPT:
199 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
200 endpoint_list_add_ep(list, ohci_ep);
201 OHCI_SET(instance->registers->control, C_PLE | C_IE);
202 break;
203 }
204}
205
206void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
207{
208 assert(instance);
209 assert(ep);
210
211 /* Dequeue ep */
212 endpoint_list_t *list = &instance->lists[ep->transfer_type];
213 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
214
215 assert(list);
216 assert(ohci_ep);
217 switch (ep->transfer_type) {
218 case USB_TRANSFER_CONTROL:
219 OHCI_CLR(instance->registers->control, C_CLE);
220 endpoint_list_remove_ep(list, ohci_ep);
221 OHCI_WR(instance->registers->control_current, 0);
222 OHCI_SET(instance->registers->control, C_CLE);
223 break;
224 case USB_TRANSFER_BULK:
225 OHCI_CLR(instance->registers->control, C_BLE);
226 endpoint_list_remove_ep(list, ohci_ep);
227 OHCI_WR(instance->registers->bulk_current, 0);
228 OHCI_SET(instance->registers->control, C_BLE);
229 break;
230 case USB_TRANSFER_ISOCHRONOUS:
231 case USB_TRANSFER_INTERRUPT:
232 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
233 endpoint_list_remove_ep(list, ohci_ep);
234 OHCI_SET(instance->registers->control, C_PLE | C_IE);
235 break;
236 default:
237 break;
238 }
239}
240
241/** Add USB transfer to the schedule.
242 *
243 * @param[in] instance OHCI hc driver structure.
244 * @param[in] batch Batch representing the transfer.
245 * @return Error code.
246 */
247int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
248{
249 assert(hcd);
250 hc_t *instance = hcd->driver.data;
251 assert(instance);
252
253 /* Check for root hub communication */
254 if (batch->ep->address == ohci_rh_get_address(&instance->rh)) {
255 usb_log_debug("OHCI root hub request.\n");
256 return ohci_rh_schedule(&instance->rh, batch);
257 }
258 ohci_transfer_batch_t *ohci_batch = ohci_transfer_batch_get(batch);
259 if (!ohci_batch)
260 return ENOMEM;
261
262 fibril_mutex_lock(&instance->guard);
263 list_append(&ohci_batch->link, &instance->pending_batches);
264 ohci_transfer_batch_commit(ohci_batch);
265
266 /* Control and bulk schedules need a kick to start working */
267 switch (batch->ep->transfer_type)
268 {
269 case USB_TRANSFER_CONTROL:
270 OHCI_SET(instance->registers->command_status, CS_CLF);
271 break;
272 case USB_TRANSFER_BULK:
273 OHCI_SET(instance->registers->command_status, CS_BLF);
274 break;
275 default:
276 break;
277 }
278 fibril_mutex_unlock(&instance->guard);
279 return EOK;
280}
281
282/** Interrupt handling routine
283 *
284 * @param[in] instance OHCI hc driver structure.
285 * @param[in] status Value of the status register at the time of interrupt.
286 */
287void hc_interrupt(hc_t *instance, uint32_t status)
288{
289 status = OHCI_RD(status);
290 assert(instance);
291 if ((status & ~I_SF) == 0) /* ignore sof status */
292 return;
293 usb_log_debug2("OHCI(%p) interrupt: %x.\n", instance, status);
294 if (status & I_RHSC)
295 ohci_rh_interrupt(&instance->rh);
296
297 if (status & I_WDH) {
298 fibril_mutex_lock(&instance->guard);
299 usb_log_debug2("HCCA: %p-%#" PRIx32 " (%p).\n", instance->hcca,
300 OHCI_RD(instance->registers->hcca),
301 (void *) addr_to_phys(instance->hcca));
302 usb_log_debug2("Periodic current: %#" PRIx32 ".\n",
303 OHCI_RD(instance->registers->periodic_current));
304
305 link_t *current = list_first(&instance->pending_batches);
306 while (current && current != &instance->pending_batches.head) {
307 link_t *next = current->next;
308 ohci_transfer_batch_t *batch =
309 ohci_transfer_batch_from_link(current);
310
311 if (ohci_transfer_batch_is_complete(batch)) {
312 list_remove(current);
313 ohci_transfer_batch_finish_dispose(batch);
314 }
315
316 current = next;
317 }
318 fibril_mutex_unlock(&instance->guard);
319 }
320
321 if (status & I_UE) {
322 usb_log_fatal("Error like no other!\n");
323 hc_start(instance);
324 }
325
326}
327
328/** Check status register regularly
329 *
330 * @param[in] instance OHCI hc driver structure.
331 * @return Error code
332 */
333int interrupt_emulator(hc_t *instance)
334{
335 assert(instance);
336 usb_log_info("Started interrupt emulator.\n");
337 while (1) {
338 const uint32_t status = instance->registers->interrupt_status;
339 instance->registers->interrupt_status = status;
340 hc_interrupt(instance, status);
341 async_usleep(10000);
342 }
343 return EOK;
344}
345
346/** Turn off any (BIOS)driver that might be in control of the device.
347 *
348 * This function implements routines described in chapter 5.1.1.3 of the OHCI
349 * specification (page 40, pdf page 54).
350 *
351 * @param[in] instance OHCI hc driver structure.
352 */
353void hc_gain_control(hc_t *instance)
354{
355 assert(instance);
356
357 usb_log_debug("Requesting OHCI control.\n");
358 if (OHCI_RD(instance->registers->revision) & R_LEGACY_FLAG) {
359 /* Turn off legacy emulation, it should be enough to zero
360 * the lowest bit, but it caused problems. Thus clear all
361 * except GateA20 (causes restart on some hw).
362 * See page 145 of the specs for details.
363 */
364 volatile uint32_t *ohci_emulation_reg =
365 (uint32_t*)((char*)instance->registers + LEGACY_REGS_OFFSET);
366 usb_log_debug("OHCI legacy register %p: %x.\n",
367 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
368 /* Zero everything but A20State */
369 OHCI_CLR(*ohci_emulation_reg, ~0x100);
370 usb_log_debug(
371 "OHCI legacy register (should be 0 or 0x100) %p: %x.\n",
372 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
373 }
374
375 /* Interrupt routing enabled => smm driver is active */
376 if (OHCI_RD(instance->registers->control) & C_IR) {
377 usb_log_debug("SMM driver: request ownership change.\n");
378 OHCI_SET(instance->registers->command_status, CS_OCR);
379 /* Hope that SMM actually knows its stuff or we can hang here */
380 while (OHCI_RD(instance->registers->control & C_IR)) {
381 async_usleep(1000);
382 }
383 usb_log_info("SMM driver: Ownership taken.\n");
384 C_HCFS_SET(instance->registers->control, C_HCFS_RESET);
385 async_usleep(50000);
386 return;
387 }
388
389 const unsigned hc_status = C_HCFS_GET(instance->registers->control);
390 /* Interrupt routing disabled && status != USB_RESET => BIOS active */
391 if (hc_status != C_HCFS_RESET) {
392 usb_log_debug("BIOS driver found.\n");
393 if (hc_status == C_HCFS_OPERATIONAL) {
394 usb_log_info("BIOS driver: HC operational.\n");
395 return;
396 }
397 /* HC is suspended assert resume for 20ms */
398 C_HCFS_SET(instance->registers->control, C_HCFS_RESUME);
399 async_usleep(20000);
400 usb_log_info("BIOS driver: HC resumed.\n");
401 return;
402 }
403
404 /* HC is in reset (hw startup) => no other driver
405 * maintain reset for at least the time specified in USB spec (50 ms)*/
406 usb_log_debug("Host controller found in reset state.\n");
407 async_usleep(50000);
408}
409
410/** OHCI hw initialization routine.
411 *
412 * @param[in] instance OHCI hc driver structure.
413 */
414void hc_start(hc_t *instance)
415{
416 /* OHCI guide page 42 */
417 assert(instance);
418 usb_log_debug2("Started hc initialization routine.\n");
419
420 /* Save contents of fm_interval register */
421 const uint32_t fm_interval = OHCI_RD(instance->registers->fm_interval);
422 usb_log_debug2("Old value of HcFmInterval: %x.\n", fm_interval);
423
424 /* Reset hc */
425 usb_log_debug2("HC reset.\n");
426 size_t time = 0;
427 OHCI_WR(instance->registers->command_status, CS_HCR);
428 while (OHCI_RD(instance->registers->command_status) & CS_HCR) {
429 async_usleep(10);
430 time += 10;
431 }
432 usb_log_debug2("HC reset complete in %zu us.\n", time);
433
434 /* Restore fm_interval */
435 OHCI_WR(instance->registers->fm_interval, fm_interval);
436 assert((OHCI_RD(instance->registers->command_status) & CS_HCR) == 0);
437
438 /* hc is now in suspend state */
439 usb_log_debug2("HC should be in suspend state(%x).\n",
440 OHCI_RD(instance->registers->control));
441
442 /* Use HCCA */
443 OHCI_WR(instance->registers->hcca, addr_to_phys(instance->hcca));
444
445 /* Use queues */
446 OHCI_WR(instance->registers->bulk_head,
447 instance->lists[USB_TRANSFER_BULK].list_head_pa);
448 usb_log_debug2("Bulk HEAD set to: %p (%#" PRIx32 ").\n",
449 instance->lists[USB_TRANSFER_BULK].list_head,
450 instance->lists[USB_TRANSFER_BULK].list_head_pa);
451
452 OHCI_WR(instance->registers->control_head,
453 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
454 usb_log_debug2("Control HEAD set to: %p (%#" PRIx32 ").\n",
455 instance->lists[USB_TRANSFER_CONTROL].list_head,
456 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
457
458 /* Enable queues */
459 OHCI_SET(instance->registers->control, (C_PLE | C_IE | C_CLE | C_BLE));
460 usb_log_debug("Queues enabled(%x).\n",
461 OHCI_RD(instance->registers->control));
462
463 /* Enable interrupts */
464 OHCI_WR(instance->registers->interrupt_enable, OHCI_USED_INTERRUPTS);
465 usb_log_debug("Enabled interrupts: %x.\n",
466 OHCI_RD(instance->registers->interrupt_enable));
467 OHCI_WR(instance->registers->interrupt_enable, I_MI);
468
469 /* Set periodic start to 90% */
470 const uint32_t frame_length =
471 (fm_interval >> FMI_FI_SHIFT) & FMI_FI_MASK;
472 OHCI_WR(instance->registers->periodic_start,
473 ((frame_length / 10) * 9) & PS_MASK << PS_SHIFT);
474 usb_log_debug2("All periodic start set to: %x(%u - 90%% of %d).\n",
475 OHCI_RD(instance->registers->periodic_start),
476 OHCI_RD(instance->registers->periodic_start), frame_length);
477 C_HCFS_SET(instance->registers->control, C_HCFS_OPERATIONAL);
478 usb_log_debug("OHCI HC up and running (ctl_reg=0x%x).\n",
479 OHCI_RD(instance->registers->control));
480}
481
482/** Initialize schedule queues
483 *
484 * @param[in] instance OHCI hc driver structure
485 * @return Error code
486 */
487int hc_init_transfer_lists(hc_t *instance)
488{
489 assert(instance);
490#define SETUP_ENDPOINT_LIST(type) \
491do { \
492 const char *name = usb_str_transfer_type(type); \
493 const int ret = endpoint_list_init(&instance->lists[type], name); \
494 if (ret != EOK) { \
495 usb_log_error("Failed to setup %s endpoint list: %s.\n", \
496 name, str_error(ret)); \
497 endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]);\
498 endpoint_list_fini(&instance->lists[USB_TRANSFER_INTERRUPT]); \
499 endpoint_list_fini(&instance->lists[USB_TRANSFER_CONTROL]); \
500 endpoint_list_fini(&instance->lists[USB_TRANSFER_BULK]); \
501 return ret; \
502 } \
503} while (0)
504
505 SETUP_ENDPOINT_LIST(USB_TRANSFER_ISOCHRONOUS);
506 SETUP_ENDPOINT_LIST(USB_TRANSFER_INTERRUPT);
507 SETUP_ENDPOINT_LIST(USB_TRANSFER_CONTROL);
508 SETUP_ENDPOINT_LIST(USB_TRANSFER_BULK);
509#undef SETUP_ENDPOINT_LIST
510 endpoint_list_set_next(&instance->lists[USB_TRANSFER_INTERRUPT],
511 &instance->lists[USB_TRANSFER_ISOCHRONOUS]);
512
513 return EOK;
514}
515
516/** Initialize memory structures used by the OHCI hcd.
517 *
518 * @param[in] instance OHCI hc driver structure.
519 * @return Error code.
520 */
521int hc_init_memory(hc_t *instance)
522{
523 assert(instance);
524
525 memset(&instance->rh, 0, sizeof(instance->rh));
526 /* Init queues */
527 const int ret = hc_init_transfer_lists(instance);
528 if (ret != EOK) {
529 return ret;
530 }
531
532 /*Init HCCA */
533 instance->hcca = hcca_get();
534 if (instance->hcca == NULL)
535 return ENOMEM;
536 usb_log_debug2("OHCI HCCA initialized at %p.\n", instance->hcca);
537
538 for (unsigned i = 0; i < HCCA_INT_EP_COUNT; ++i) {
539 hcca_set_int_ep(instance->hcca, i,
540 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
541 }
542 usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").\n",
543 instance->lists[USB_TRANSFER_INTERRUPT].list_head,
544 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
545
546 return EOK;
547}
548
549/**
550 * @}
551 */
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