source: mainline/uspace/drv/bus/usb/ohci/hc.c@ 6297465

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 6297465 was f5bfd98, checked in by Jan Vesely <jano.vesely@…>, 12 years ago

ohci: Fix incorrect parentheses
  • Property mode set to 100644
File size: 16.1 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbohcihc
30 * @{
31 */
32/** @file
33 * @brief OHCI Host controller driver routines
34 */
35
36#include <assert.h>
37#include <async.h>
38#include <errno.h>
39#include <macros.h>
40#include <mem.h>
41#include <stdlib.h>
42#include <str_error.h>
43#include <sys/types.h>
44
45#include <usb/debug.h>
46#include <usb/usb.h>
47
48#include "ohci_endpoint.h"
49#include "ohci_batch.h"
50#include "utils/malloc32.h"
51
52#include "hc.h"
53
54#define OHCI_USED_INTERRUPTS \
55 (I_SO | I_WDH | I_UE | I_RHSC)
56
57static const irq_pio_range_t ohci_pio_ranges[] = {
58 {
59 .base = 0,
60 .size = sizeof(ohci_regs_t)
61 }
62};
63
64static const irq_cmd_t ohci_irq_commands[] = {
65 {
66 .cmd = CMD_PIO_READ_32,
67 .dstarg = 1,
68 .addr = NULL
69 },
70 {
71 .cmd = CMD_AND,
72 .srcarg = 1,
73 .dstarg = 2,
74 .value = 0
75 },
76 {
77 .cmd = CMD_PREDICATE,
78 .srcarg = 2,
79 .value = 2
80 },
81 {
82 .cmd = CMD_PIO_WRITE_A_32,
83 .srcarg = 1,
84 .addr = NULL
85 },
86 {
87 .cmd = CMD_ACCEPT
88 }
89};
90
91static void hc_gain_control(hc_t *instance);
92static void hc_start(hc_t *instance);
93static int hc_init_transfer_lists(hc_t *instance);
94static int hc_init_memory(hc_t *instance);
95static int interrupt_emulator(hc_t *instance);
96
97/** Generate IRQ code.
98 * @param[out] ranges PIO ranges buffer.
99 * @param[in] ranges_size Size of the ranges buffer (bytes).
100 * @param[out] cmds Commands buffer.
101 * @param[in] cmds_size Size of the commands buffer (bytes).
102 * @param[in] regs Device's register range.
103 *
104 * @return Error code.
105 */
106int hc_gen_irq_code(irq_code_t *code, addr_range_t *regs)
107{
108 assert(code);
109 if (RNGSZ(*regs) < sizeof(ohci_regs_t))
110 return EOVERFLOW;
111
112 code->ranges = malloc(sizeof(ohci_pio_ranges));
113 if (code->ranges == NULL)
114 return ENOMEM;
115
116 code->cmds = malloc(sizeof(ohci_irq_commands));
117 if (code->cmds == NULL) {
118 free(code->ranges);
119 return ENOMEM;
120 }
121
122 code->rangecount = ARRAY_SIZE(ohci_pio_ranges);
123 code->cmdcount = ARRAY_SIZE(ohci_irq_commands);
124
125 memcpy(code->ranges, ohci_pio_ranges, sizeof(ohci_pio_ranges));
126 code->ranges[0].base = RNGABS(*regs);
127
128 memcpy(code->cmds, ohci_irq_commands, sizeof(ohci_irq_commands));
129 ohci_regs_t *registers = (ohci_regs_t *) RNGABSPTR(*regs);
130 code->cmds[0].addr = (void *) &registers->interrupt_status;
131 code->cmds[3].addr = (void *) &registers->interrupt_status;
132 OHCI_WR(code->cmds[1].value, OHCI_USED_INTERRUPTS);
133
134 return EOK;
135}
136
137/** Initialize OHCI hc driver structure
138 *
139 * @param[in] instance Memory place for the structure.
140 * @param[in] regs Device's I/O registers range.
141 * @param[in] interrupts True if w interrupts should be used
142 * @return Error code
143 */
144int hc_init(hc_t *instance, addr_range_t *regs, bool interrupts)
145{
146 assert(instance);
147
148 int ret = pio_enable_range(regs, (void **) &instance->registers);
149 if (ret != EOK) {
150 usb_log_error("Failed to gain access to device registers: %s.\n",
151 str_error(ret));
152 return ret;
153 }
154
155 list_initialize(&instance->pending_batches);
156 fibril_mutex_initialize(&instance->guard);
157
158 ret = hc_init_memory(instance);
159 if (ret != EOK) {
160 usb_log_error("Failed to create OHCI memory structures: %s.\n",
161 str_error(ret));
162 return ret;
163 }
164
165 hc_gain_control(instance);
166
167 if (!interrupts) {
168 instance->interrupt_emulator =
169 fibril_create((int(*)(void*))interrupt_emulator, instance);
170 fibril_add_ready(instance->interrupt_emulator);
171 }
172
173 ohci_rh_init(&instance->rh, instance->registers, "ohci rh");
174 hc_start(instance);
175
176 return EOK;
177}
178
179void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
180{
181 assert(instance);
182 assert(ep);
183
184 endpoint_list_t *list = &instance->lists[ep->transfer_type];
185 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
186 assert(list);
187 assert(ohci_ep);
188
189 /* Enqueue ep */
190 switch (ep->transfer_type) {
191 case USB_TRANSFER_CONTROL:
192 OHCI_CLR(instance->registers->control, C_CLE);
193 endpoint_list_add_ep(list, ohci_ep);
194 OHCI_WR(instance->registers->control_current, 0);
195 OHCI_SET(instance->registers->control, C_CLE);
196 break;
197 case USB_TRANSFER_BULK:
198 OHCI_CLR(instance->registers->control, C_BLE);
199 endpoint_list_add_ep(list, ohci_ep);
200 OHCI_WR(instance->registers->bulk_current, 0);
201 OHCI_SET(instance->registers->control, C_BLE);
202 break;
203 case USB_TRANSFER_ISOCHRONOUS:
204 case USB_TRANSFER_INTERRUPT:
205 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
206 endpoint_list_add_ep(list, ohci_ep);
207 OHCI_SET(instance->registers->control, C_PLE | C_IE);
208 break;
209 }
210}
211
212void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
213{
214 assert(instance);
215 assert(ep);
216
217 /* Dequeue ep */
218 endpoint_list_t *list = &instance->lists[ep->transfer_type];
219 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
220
221 assert(list);
222 assert(ohci_ep);
223 switch (ep->transfer_type) {
224 case USB_TRANSFER_CONTROL:
225 OHCI_CLR(instance->registers->control, C_CLE);
226 endpoint_list_remove_ep(list, ohci_ep);
227 OHCI_WR(instance->registers->control_current, 0);
228 OHCI_SET(instance->registers->control, C_CLE);
229 break;
230 case USB_TRANSFER_BULK:
231 OHCI_CLR(instance->registers->control, C_BLE);
232 endpoint_list_remove_ep(list, ohci_ep);
233 OHCI_WR(instance->registers->bulk_current, 0);
234 OHCI_SET(instance->registers->control, C_BLE);
235 break;
236 case USB_TRANSFER_ISOCHRONOUS:
237 case USB_TRANSFER_INTERRUPT:
238 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
239 endpoint_list_remove_ep(list, ohci_ep);
240 OHCI_SET(instance->registers->control, C_PLE | C_IE);
241 break;
242 default:
243 break;
244 }
245}
246
247/** Add USB transfer to the schedule.
248 *
249 * @param[in] instance OHCI hc driver structure.
250 * @param[in] batch Batch representing the transfer.
251 * @return Error code.
252 */
253int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
254{
255 assert(hcd);
256 hc_t *instance = hcd->driver.data;
257 assert(instance);
258
259 /* Check for root hub communication */
260 if (batch->ep->address == ohci_rh_get_address(&instance->rh)) {
261 usb_log_debug("OHCI root hub request.\n");
262 return ohci_rh_schedule(&instance->rh, batch);
263 }
264 ohci_transfer_batch_t *ohci_batch = ohci_transfer_batch_get(batch);
265 if (!ohci_batch)
266 return ENOMEM;
267
268 fibril_mutex_lock(&instance->guard);
269 list_append(&ohci_batch->link, &instance->pending_batches);
270 ohci_transfer_batch_commit(ohci_batch);
271
272 /* Control and bulk schedules need a kick to start working */
273 switch (batch->ep->transfer_type)
274 {
275 case USB_TRANSFER_CONTROL:
276 OHCI_SET(instance->registers->command_status, CS_CLF);
277 break;
278 case USB_TRANSFER_BULK:
279 OHCI_SET(instance->registers->command_status, CS_BLF);
280 break;
281 default:
282 break;
283 }
284 fibril_mutex_unlock(&instance->guard);
285 return EOK;
286}
287
288/** Interrupt handling routine
289 *
290 * @param[in] instance OHCI hc driver structure.
291 * @param[in] status Value of the status register at the time of interrupt.
292 */
293void hc_interrupt(hc_t *instance, uint32_t status)
294{
295 status = OHCI_RD(status);
296 assert(instance);
297 if ((status & ~I_SF) == 0) /* ignore sof status */
298 return;
299 usb_log_debug2("OHCI(%p) interrupt: %x.\n", instance, status);
300 if (status & I_RHSC)
301 ohci_rh_interrupt(&instance->rh);
302
303 if (status & I_WDH) {
304 fibril_mutex_lock(&instance->guard);
305 usb_log_debug2("HCCA: %p-%#" PRIx32 " (%p).\n", instance->hcca,
306 OHCI_RD(instance->registers->hcca),
307 (void *) addr_to_phys(instance->hcca));
308 usb_log_debug2("Periodic current: %#" PRIx32 ".\n",
309 OHCI_RD(instance->registers->periodic_current));
310
311 link_t *current = list_first(&instance->pending_batches);
312 while (current && current != &instance->pending_batches.head) {
313 link_t *next = current->next;
314 ohci_transfer_batch_t *batch =
315 ohci_transfer_batch_from_link(current);
316
317 if (ohci_transfer_batch_is_complete(batch)) {
318 list_remove(current);
319 ohci_transfer_batch_finish_dispose(batch);
320 }
321
322 current = next;
323 }
324 fibril_mutex_unlock(&instance->guard);
325 }
326
327 if (status & I_UE) {
328 usb_log_fatal("Error like no other!\n");
329 hc_start(instance);
330 }
331
332}
333
334/** Check status register regularly
335 *
336 * @param[in] instance OHCI hc driver structure.
337 * @return Error code
338 */
339int interrupt_emulator(hc_t *instance)
340{
341 assert(instance);
342 usb_log_info("Started interrupt emulator.\n");
343 while (1) {
344 const uint32_t status = instance->registers->interrupt_status;
345 instance->registers->interrupt_status = status;
346 hc_interrupt(instance, status);
347 async_usleep(10000);
348 }
349 return EOK;
350}
351
352/** Turn off any (BIOS)driver that might be in control of the device.
353 *
354 * This function implements routines described in chapter 5.1.1.3 of the OHCI
355 * specification (page 40, pdf page 54).
356 *
357 * @param[in] instance OHCI hc driver structure.
358 */
359void hc_gain_control(hc_t *instance)
360{
361 assert(instance);
362
363 usb_log_debug("Requesting OHCI control.\n");
364 if (OHCI_RD(instance->registers->revision) & R_LEGACY_FLAG) {
365 /* Turn off legacy emulation, it should be enough to zero
366 * the lowest bit, but it caused problems. Thus clear all
367 * except GateA20 (causes restart on some hw).
368 * See page 145 of the specs for details.
369 */
370 volatile uint32_t *ohci_emulation_reg =
371 (uint32_t*)((char*)instance->registers + LEGACY_REGS_OFFSET);
372 usb_log_debug("OHCI legacy register %p: %x.\n",
373 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
374 /* Zero everything but A20State */
375 OHCI_CLR(*ohci_emulation_reg, ~0x100);
376 usb_log_debug(
377 "OHCI legacy register (should be 0 or 0x100) %p: %x.\n",
378 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
379 }
380
381 /* Interrupt routing enabled => smm driver is active */
382 if (OHCI_RD(instance->registers->control) & C_IR) {
383 usb_log_debug("SMM driver: request ownership change.\n");
384 OHCI_SET(instance->registers->command_status, CS_OCR);
385 /* Hope that SMM actually knows its stuff or we can hang here */
386 while (OHCI_RD(instance->registers->control) & C_IR) {
387 async_usleep(1000);
388 }
389 usb_log_info("SMM driver: Ownership taken.\n");
390 C_HCFS_SET(instance->registers->control, C_HCFS_RESET);
391 async_usleep(50000);
392 return;
393 }
394
395 const unsigned hc_status = C_HCFS_GET(instance->registers->control);
396 /* Interrupt routing disabled && status != USB_RESET => BIOS active */
397 if (hc_status != C_HCFS_RESET) {
398 usb_log_debug("BIOS driver found.\n");
399 if (hc_status == C_HCFS_OPERATIONAL) {
400 usb_log_info("BIOS driver: HC operational.\n");
401 return;
402 }
403 /* HC is suspended assert resume for 20ms */
404 C_HCFS_SET(instance->registers->control, C_HCFS_RESUME);
405 async_usleep(20000);
406 usb_log_info("BIOS driver: HC resumed.\n");
407 return;
408 }
409
410 /* HC is in reset (hw startup) => no other driver
411 * maintain reset for at least the time specified in USB spec (50 ms)*/
412 usb_log_debug("Host controller found in reset state.\n");
413 async_usleep(50000);
414}
415
416/** OHCI hw initialization routine.
417 *
418 * @param[in] instance OHCI hc driver structure.
419 */
420void hc_start(hc_t *instance)
421{
422 /* OHCI guide page 42 */
423 assert(instance);
424 usb_log_debug2("Started hc initialization routine.\n");
425
426 /* Save contents of fm_interval register */
427 const uint32_t fm_interval = OHCI_RD(instance->registers->fm_interval);
428 usb_log_debug2("Old value of HcFmInterval: %x.\n", fm_interval);
429
430 /* Reset hc */
431 usb_log_debug2("HC reset.\n");
432 size_t time = 0;
433 OHCI_WR(instance->registers->command_status, CS_HCR);
434 while (OHCI_RD(instance->registers->command_status) & CS_HCR) {
435 async_usleep(10);
436 time += 10;
437 }
438 usb_log_debug2("HC reset complete in %zu us.\n", time);
439
440 /* Restore fm_interval */
441 OHCI_WR(instance->registers->fm_interval, fm_interval);
442 assert((OHCI_RD(instance->registers->command_status) & CS_HCR) == 0);
443
444 /* hc is now in suspend state */
445 usb_log_debug2("HC should be in suspend state(%x).\n",
446 OHCI_RD(instance->registers->control));
447
448 /* Use HCCA */
449 OHCI_WR(instance->registers->hcca, addr_to_phys(instance->hcca));
450
451 /* Use queues */
452 OHCI_WR(instance->registers->bulk_head,
453 instance->lists[USB_TRANSFER_BULK].list_head_pa);
454 usb_log_debug2("Bulk HEAD set to: %p (%#" PRIx32 ").\n",
455 instance->lists[USB_TRANSFER_BULK].list_head,
456 instance->lists[USB_TRANSFER_BULK].list_head_pa);
457
458 OHCI_WR(instance->registers->control_head,
459 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
460 usb_log_debug2("Control HEAD set to: %p (%#" PRIx32 ").\n",
461 instance->lists[USB_TRANSFER_CONTROL].list_head,
462 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
463
464 /* Enable queues */
465 OHCI_SET(instance->registers->control, (C_PLE | C_IE | C_CLE | C_BLE));
466 usb_log_debug("Queues enabled(%x).\n",
467 OHCI_RD(instance->registers->control));
468
469 /* Enable interrupts */
470 OHCI_WR(instance->registers->interrupt_enable, OHCI_USED_INTERRUPTS);
471 usb_log_debug("Enabled interrupts: %x.\n",
472 OHCI_RD(instance->registers->interrupt_enable));
473 OHCI_WR(instance->registers->interrupt_enable, I_MI);
474
475 /* Set periodic start to 90% */
476 const uint32_t frame_length =
477 (fm_interval >> FMI_FI_SHIFT) & FMI_FI_MASK;
478 OHCI_WR(instance->registers->periodic_start,
479 ((frame_length / 10) * 9) & PS_MASK << PS_SHIFT);
480 usb_log_debug2("All periodic start set to: %x(%u - 90%% of %d).\n",
481 OHCI_RD(instance->registers->periodic_start),
482 OHCI_RD(instance->registers->periodic_start), frame_length);
483 C_HCFS_SET(instance->registers->control, C_HCFS_OPERATIONAL);
484 usb_log_debug("OHCI HC up and running (ctl_reg=0x%x).\n",
485 OHCI_RD(instance->registers->control));
486}
487
488/** Initialize schedule queues
489 *
490 * @param[in] instance OHCI hc driver structure
491 * @return Error code
492 */
493int hc_init_transfer_lists(hc_t *instance)
494{
495 assert(instance);
496#define SETUP_ENDPOINT_LIST(type) \
497do { \
498 const char *name = usb_str_transfer_type(type); \
499 const int ret = endpoint_list_init(&instance->lists[type], name); \
500 if (ret != EOK) { \
501 usb_log_error("Failed to setup %s endpoint list: %s.\n", \
502 name, str_error(ret)); \
503 endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]);\
504 endpoint_list_fini(&instance->lists[USB_TRANSFER_INTERRUPT]); \
505 endpoint_list_fini(&instance->lists[USB_TRANSFER_CONTROL]); \
506 endpoint_list_fini(&instance->lists[USB_TRANSFER_BULK]); \
507 return ret; \
508 } \
509} while (0)
510
511 SETUP_ENDPOINT_LIST(USB_TRANSFER_ISOCHRONOUS);
512 SETUP_ENDPOINT_LIST(USB_TRANSFER_INTERRUPT);
513 SETUP_ENDPOINT_LIST(USB_TRANSFER_CONTROL);
514 SETUP_ENDPOINT_LIST(USB_TRANSFER_BULK);
515#undef SETUP_ENDPOINT_LIST
516 endpoint_list_set_next(&instance->lists[USB_TRANSFER_INTERRUPT],
517 &instance->lists[USB_TRANSFER_ISOCHRONOUS]);
518
519 return EOK;
520}
521
522/** Initialize memory structures used by the OHCI hcd.
523 *
524 * @param[in] instance OHCI hc driver structure.
525 * @return Error code.
526 */
527int hc_init_memory(hc_t *instance)
528{
529 assert(instance);
530
531 memset(&instance->rh, 0, sizeof(instance->rh));
532 /* Init queues */
533 const int ret = hc_init_transfer_lists(instance);
534 if (ret != EOK) {
535 return ret;
536 }
537
538 /*Init HCCA */
539 instance->hcca = hcca_get();
540 if (instance->hcca == NULL)
541 return ENOMEM;
542 usb_log_debug2("OHCI HCCA initialized at %p.\n", instance->hcca);
543
544 for (unsigned i = 0; i < HCCA_INT_EP_COUNT; ++i) {
545 hcca_set_int_ep(instance->hcca, i,
546 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
547 }
548 usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").\n",
549 instance->lists[USB_TRANSFER_INTERRUPT].list_head,
550 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
551
552 return EOK;
553}
554
555/**
556 * @}
557 */
Note: See TracBrowser for help on using the repository browser.