source: mainline/uspace/drv/bus/usb/ohci/hc.c@ 41abf3c

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 41abf3c was d60115a, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago

ohci: implement transfer abort on endpoint unregister
  • Property mode set to 100644
File size: 17.5 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbohcihc
30 * @{
31 */
32/** @file
33 * @brief OHCI Host controller driver routines
34 */
35
36#include <assert.h>
37#include <async.h>
38#include <errno.h>
39#include <macros.h>
40#include <mem.h>
41#include <stdlib.h>
42#include <str_error.h>
43#include <stddef.h>
44#include <stdint.h>
45
46#include <usb/debug.h>
47#include <usb/usb.h>
48
49#include "ohci_bus.h"
50#include "ohci_batch.h"
51
52#include "hc.h"
53
54#define OHCI_USED_INTERRUPTS \
55 (I_SO | I_WDH | I_UE | I_RHSC)
56
57static const irq_pio_range_t ohci_pio_ranges[] = {
58 {
59 .base = 0,
60 .size = sizeof(ohci_regs_t)
61 }
62};
63
64static const irq_cmd_t ohci_irq_commands[] = {
65 {
66 .cmd = CMD_PIO_READ_32,
67 .dstarg = 1,
68 .addr = NULL
69 },
70 {
71 .cmd = CMD_AND,
72 .srcarg = 1,
73 .dstarg = 2,
74 .value = 0
75 },
76 {
77 .cmd = CMD_PREDICATE,
78 .srcarg = 2,
79 .value = 2
80 },
81 {
82 .cmd = CMD_PIO_WRITE_A_32,
83 .srcarg = 1,
84 .addr = NULL
85 },
86 {
87 .cmd = CMD_ACCEPT
88 }
89};
90
91static int hc_init_transfer_lists(hc_t *instance);
92static int hc_init_memory(hc_t *instance);
93
94/** Generate IRQ code.
95 * @param[out] ranges PIO ranges buffer.
96 * @param[in] ranges_size Size of the ranges buffer (bytes).
97 * @param[out] cmds Commands buffer.
98 * @param[in] cmds_size Size of the commands buffer (bytes).
99 * @param[in] hw_res Device's resources.
100 *
101 * @return Error code.
102 */
103int hc_gen_irq_code(irq_code_t *code, hc_device_t *hcd, const hw_res_list_parsed_t *hw_res)
104{
105 assert(code);
106 assert(hw_res);
107
108 if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
109 return EINVAL;
110
111 const addr_range_t regs = hw_res->mem_ranges.ranges[0];
112
113 if (RNGSZ(regs) < sizeof(ohci_regs_t))
114 return EOVERFLOW;
115
116 code->ranges = malloc(sizeof(ohci_pio_ranges));
117 if (code->ranges == NULL)
118 return ENOMEM;
119
120 code->cmds = malloc(sizeof(ohci_irq_commands));
121 if (code->cmds == NULL) {
122 free(code->ranges);
123 return ENOMEM;
124 }
125
126 code->rangecount = ARRAY_SIZE(ohci_pio_ranges);
127 code->cmdcount = ARRAY_SIZE(ohci_irq_commands);
128
129 memcpy(code->ranges, ohci_pio_ranges, sizeof(ohci_pio_ranges));
130 code->ranges[0].base = RNGABS(regs);
131
132 memcpy(code->cmds, ohci_irq_commands, sizeof(ohci_irq_commands));
133 ohci_regs_t *registers = (ohci_regs_t *) RNGABSPTR(regs);
134 code->cmds[0].addr = (void *) &registers->interrupt_status;
135 code->cmds[3].addr = (void *) &registers->interrupt_status;
136 OHCI_WR(code->cmds[1].value, OHCI_USED_INTERRUPTS);
137
138 usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.",
139 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
140
141 return hw_res->irqs.irqs[0];
142}
143
144/** Initialize OHCI hc driver structure
145 *
146 * @param[in] instance Memory place for the structure.
147 * @param[in] regs Device's resources
148 * @param[in] interrupts True if w interrupts should be used
149 * @return Error code
150 */
151int hc_add(hc_device_t *hcd, const hw_res_list_parsed_t *hw_res)
152{
153 hc_t *instance = hcd_to_hc(hcd);
154 assert(hw_res);
155 if (hw_res->mem_ranges.count != 1 ||
156 hw_res->mem_ranges.ranges[0].size < sizeof(ohci_regs_t))
157 return EINVAL;
158
159 int ret = pio_enable_range(&hw_res->mem_ranges.ranges[0],
160 (void **) &instance->registers);
161 if (ret != EOK) {
162 usb_log_error("Failed to gain access to registers: %s.",
163 str_error(ret));
164 return ret;
165 }
166 usb_log_debug("Device registers at %" PRIx64 " (%zuB) accessible.",
167 hw_res->mem_ranges.ranges[0].address.absolute,
168 hw_res->mem_ranges.ranges[0].size);
169
170 list_initialize(&instance->pending_endpoints);
171 fibril_mutex_initialize(&instance->guard);
172
173 ret = hc_init_memory(instance);
174 if (ret != EOK) {
175 usb_log_error("Failed to create OHCI memory structures: %s.",
176 str_error(ret));
177 // TODO: We should disable pio access here
178 return ret;
179 }
180
181 return EOK;
182}
183
184/** Safely dispose host controller internal structures
185 *
186 * @param[in] instance Host controller structure to use.
187 */
188int hc_gone(hc_device_t *instance)
189{
190 assert(instance);
191 /* TODO: implement*/
192 return ENOTSUP;
193}
194
195void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
196{
197 assert(instance);
198 assert(ep);
199
200 endpoint_list_t *list = &instance->lists[ep->transfer_type];
201 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
202 assert(list);
203 assert(ohci_ep);
204
205 /* Enqueue ep */
206 switch (ep->transfer_type) {
207 case USB_TRANSFER_CONTROL:
208 OHCI_CLR(instance->registers->control, C_CLE);
209 endpoint_list_add_ep(list, ohci_ep);
210 OHCI_WR(instance->registers->control_current, 0);
211 OHCI_SET(instance->registers->control, C_CLE);
212 break;
213 case USB_TRANSFER_BULK:
214 OHCI_CLR(instance->registers->control, C_BLE);
215 endpoint_list_add_ep(list, ohci_ep);
216 OHCI_WR(instance->registers->bulk_current, 0);
217 OHCI_SET(instance->registers->control, C_BLE);
218 break;
219 case USB_TRANSFER_ISOCHRONOUS:
220 case USB_TRANSFER_INTERRUPT:
221 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
222 endpoint_list_add_ep(list, ohci_ep);
223 OHCI_SET(instance->registers->control, C_PLE | C_IE);
224 break;
225 }
226}
227
228void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
229{
230 assert(instance);
231 assert(ep);
232
233 /* Dequeue ep */
234 endpoint_list_t *list = &instance->lists[ep->transfer_type];
235 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
236
237 assert(list);
238 assert(ohci_ep);
239 switch (ep->transfer_type) {
240 case USB_TRANSFER_CONTROL:
241 OHCI_CLR(instance->registers->control, C_CLE);
242 endpoint_list_remove_ep(list, ohci_ep);
243 OHCI_WR(instance->registers->control_current, 0);
244 OHCI_SET(instance->registers->control, C_CLE);
245 break;
246 case USB_TRANSFER_BULK:
247 OHCI_CLR(instance->registers->control, C_BLE);
248 endpoint_list_remove_ep(list, ohci_ep);
249 OHCI_WR(instance->registers->bulk_current, 0);
250 OHCI_SET(instance->registers->control, C_BLE);
251 break;
252 case USB_TRANSFER_ISOCHRONOUS:
253 case USB_TRANSFER_INTERRUPT:
254 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
255 endpoint_list_remove_ep(list, ohci_ep);
256 OHCI_SET(instance->registers->control, C_PLE | C_IE);
257 break;
258 default:
259 break;
260 }
261}
262
263int ohci_hc_status(bus_t *bus_base, uint32_t *status)
264{
265 assert(bus_base);
266 assert(status);
267
268 ohci_bus_t *bus = (ohci_bus_t *) bus_base;
269 hc_t *hc = bus->hc;
270 assert(hc);
271
272 if (hc->registers){
273 *status = OHCI_RD(hc->registers->interrupt_status);
274 OHCI_WR(hc->registers->interrupt_status, *status);
275 }
276 return EOK;
277}
278
279/** Add USB transfer to the schedule.
280 *
281 * @param[in] hcd HCD driver structure.
282 * @param[in] batch Batch representing the transfer.
283 * @return Error code.
284 */
285int ohci_hc_schedule(usb_transfer_batch_t *batch)
286{
287 assert(batch);
288
289 ohci_bus_t *bus = (ohci_bus_t *) endpoint_get_bus(batch->ep);
290 hc_t *hc = bus->hc;
291 assert(hc);
292
293 /* Check for root hub communication */
294 if (batch->target.address == ohci_rh_get_address(&hc->rh)) {
295 usb_log_debug("OHCI root hub request.");
296 return ohci_rh_schedule(&hc->rh, batch);
297 }
298 ohci_transfer_batch_t *ohci_batch = ohci_transfer_batch_get(batch);
299 if (!ohci_batch)
300 return ENOMEM;
301
302 const int err = ohci_transfer_batch_prepare(ohci_batch);
303 if (err)
304 return err;
305
306 endpoint_t *ep = batch->ep;
307 ohci_endpoint_t * const ohci_ep = ohci_endpoint_get(ep);
308
309 /* creating local reference */
310 endpoint_add_ref(ep);
311
312 fibril_mutex_lock(&ep->guard);
313 endpoint_activate_locked(ep, batch);
314 ohci_transfer_batch_commit(ohci_batch);
315 fibril_mutex_unlock(&ep->guard);
316
317 /* Control and bulk schedules need a kick to start working */
318 switch (batch->ep->transfer_type)
319 {
320 case USB_TRANSFER_CONTROL:
321 OHCI_SET(hc->registers->command_status, CS_CLF);
322 break;
323 case USB_TRANSFER_BULK:
324 OHCI_SET(hc->registers->command_status, CS_BLF);
325 break;
326 default:
327 break;
328 }
329
330 fibril_mutex_lock(&hc->guard);
331 list_append(&ohci_ep->pending_link, &hc->pending_endpoints);
332 fibril_mutex_unlock(&hc->guard);
333
334 return EOK;
335}
336
337/** Interrupt handling routine
338 *
339 * @param[in] hcd HCD driver structure.
340 * @param[in] status Value of the status register at the time of interrupt.
341 */
342void ohci_hc_interrupt(bus_t *bus_base, uint32_t status)
343{
344 assert(bus_base);
345
346 ohci_bus_t *bus = (ohci_bus_t *) bus_base;
347 hc_t *hc = bus->hc;
348 assert(hc);
349
350 status = OHCI_RD(status);
351 assert(hc);
352 if ((status & ~I_SF) == 0) /* ignore sof status */
353 return;
354 usb_log_debug2("OHCI(%p) interrupt: %x.", hc, status);
355 if (status & I_RHSC)
356 ohci_rh_interrupt(&hc->rh);
357
358 if (status & I_WDH) {
359 fibril_mutex_lock(&hc->guard);
360 usb_log_debug2("HCCA: %p-%#" PRIx32 " (%p).", hc->hcca,
361 OHCI_RD(hc->registers->hcca),
362 (void *) addr_to_phys(hc->hcca));
363 usb_log_debug2("Periodic current: %#" PRIx32 ".",
364 OHCI_RD(hc->registers->periodic_current));
365
366 list_foreach_safe(hc->pending_endpoints, current, next) {
367 ohci_endpoint_t *ep
368 = list_get_instance(current, ohci_endpoint_t, pending_link);
369
370 fibril_mutex_lock(&ep->base.guard);
371 ohci_transfer_batch_t *batch
372 = ohci_transfer_batch_get(ep->base.active_batch);
373 assert(batch);
374
375 if (ohci_transfer_batch_check_completed(batch)) {
376 endpoint_deactivate_locked(&ep->base);
377 list_remove(current);
378 endpoint_del_ref(&ep->base);
379 usb_transfer_batch_finish(&batch->base);
380 }
381 fibril_mutex_unlock(&ep->base.guard);
382 }
383 fibril_mutex_unlock(&hc->guard);
384 }
385
386 if (status & I_UE) {
387 usb_log_fatal("Error like no other!");
388 hc_start(&hc->base);
389 }
390
391}
392
393/** Turn off any (BIOS)driver that might be in control of the device.
394 *
395 * This function implements routines described in chapter 5.1.1.3 of the OHCI
396 * specification (page 40, pdf page 54).
397 *
398 * @param[in] instance OHCI hc driver structure.
399 */
400int hc_gain_control(hc_device_t *hcd)
401{
402 hc_t *instance = hcd_to_hc(hcd);
403
404 usb_log_debug("Requesting OHCI control.");
405 if (OHCI_RD(instance->registers->revision) & R_LEGACY_FLAG) {
406 /* Turn off legacy emulation, it should be enough to zero
407 * the lowest bit, but it caused problems. Thus clear all
408 * except GateA20 (causes restart on some hw).
409 * See page 145 of the specs for details.
410 */
411 volatile uint32_t *ohci_emulation_reg =
412 (uint32_t*)((char*)instance->registers + LEGACY_REGS_OFFSET);
413 usb_log_debug("OHCI legacy register %p: %x.",
414 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
415 /* Zero everything but A20State */
416 // TODO: should we ack interrupts before doing this?
417 OHCI_CLR(*ohci_emulation_reg, ~0x100);
418 usb_log_debug(
419 "OHCI legacy register (should be 0 or 0x100) %p: %x.",
420 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
421 }
422
423 /* Interrupt routing enabled => smm driver is active */
424 if (OHCI_RD(instance->registers->control) & C_IR) {
425 usb_log_debug("SMM driver: request ownership change.");
426 // TODO: should we ack interrupts before doing this?
427 OHCI_SET(instance->registers->command_status, CS_OCR);
428 /* Hope that SMM actually knows its stuff or we can hang here */
429 while (OHCI_RD(instance->registers->control) & C_IR) {
430 async_usleep(1000);
431 }
432 usb_log_info("SMM driver: Ownership taken.");
433 C_HCFS_SET(instance->registers->control, C_HCFS_RESET);
434 async_usleep(50000);
435 return EOK;
436 }
437
438 const unsigned hc_status = C_HCFS_GET(instance->registers->control);
439 /* Interrupt routing disabled && status != USB_RESET => BIOS active */
440 if (hc_status != C_HCFS_RESET) {
441 usb_log_debug("BIOS driver found.");
442 if (hc_status == C_HCFS_OPERATIONAL) {
443 usb_log_info("BIOS driver: HC operational.");
444 return EOK;
445 }
446 /* HC is suspended assert resume for 20ms */
447 C_HCFS_SET(instance->registers->control, C_HCFS_RESUME);
448 async_usleep(20000);
449 usb_log_info("BIOS driver: HC resumed.");
450 return EOK;
451 }
452
453 /* HC is in reset (hw startup) => no other driver
454 * maintain reset for at least the time specified in USB spec (50 ms)*/
455 usb_log_debug("Host controller found in reset state.");
456 async_usleep(50000);
457 return EOK;
458}
459
460/** OHCI hw initialization routine.
461 *
462 * @param[in] instance OHCI hc driver structure.
463 */
464int hc_start(hc_device_t *hcd)
465{
466 hc_t *instance = hcd_to_hc(hcd);
467 ohci_rh_init(&instance->rh, instance->registers, "ohci rh");
468
469 /* OHCI guide page 42 */
470 assert(instance);
471 usb_log_debug2("Started hc initialization routine.");
472
473 /* Save contents of fm_interval register */
474 const uint32_t fm_interval = OHCI_RD(instance->registers->fm_interval);
475 usb_log_debug2("Old value of HcFmInterval: %x.", fm_interval);
476
477 /* Reset hc */
478 usb_log_debug2("HC reset.");
479 size_t time = 0;
480 OHCI_WR(instance->registers->command_status, CS_HCR);
481 while (OHCI_RD(instance->registers->command_status) & CS_HCR) {
482 async_usleep(10);
483 time += 10;
484 }
485 usb_log_debug2("HC reset complete in %zu us.", time);
486
487 /* Restore fm_interval */
488 OHCI_WR(instance->registers->fm_interval, fm_interval);
489 assert((OHCI_RD(instance->registers->command_status) & CS_HCR) == 0);
490
491 /* hc is now in suspend state */
492 usb_log_debug2("HC should be in suspend state(%x).",
493 OHCI_RD(instance->registers->control));
494
495 /* Use HCCA */
496 OHCI_WR(instance->registers->hcca, addr_to_phys(instance->hcca));
497
498 /* Use queues */
499 OHCI_WR(instance->registers->bulk_head,
500 instance->lists[USB_TRANSFER_BULK].list_head_pa);
501 usb_log_debug2("Bulk HEAD set to: %p (%#" PRIx32 ").",
502 instance->lists[USB_TRANSFER_BULK].list_head,
503 instance->lists[USB_TRANSFER_BULK].list_head_pa);
504
505 OHCI_WR(instance->registers->control_head,
506 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
507 usb_log_debug2("Control HEAD set to: %p (%#" PRIx32 ").",
508 instance->lists[USB_TRANSFER_CONTROL].list_head,
509 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
510
511 /* Enable queues */
512 OHCI_SET(instance->registers->control, (C_PLE | C_IE | C_CLE | C_BLE));
513 usb_log_debug("Queues enabled(%x).",
514 OHCI_RD(instance->registers->control));
515
516 /* Enable interrupts */
517 if (instance->base.irq_cap >= 0) {
518 OHCI_WR(instance->registers->interrupt_enable,
519 OHCI_USED_INTERRUPTS);
520 usb_log_debug("Enabled interrupts: %x.",
521 OHCI_RD(instance->registers->interrupt_enable));
522 OHCI_WR(instance->registers->interrupt_enable, I_MI);
523 }
524
525 /* Set periodic start to 90% */
526 const uint32_t frame_length =
527 (fm_interval >> FMI_FI_SHIFT) & FMI_FI_MASK;
528 OHCI_WR(instance->registers->periodic_start,
529 ((frame_length / 10) * 9) & PS_MASK << PS_SHIFT);
530 usb_log_debug2("All periodic start set to: %x(%u - 90%% of %d).",
531 OHCI_RD(instance->registers->periodic_start),
532 OHCI_RD(instance->registers->periodic_start), frame_length);
533 C_HCFS_SET(instance->registers->control, C_HCFS_OPERATIONAL);
534 usb_log_debug("OHCI HC up and running (ctl_reg=0x%x).",
535 OHCI_RD(instance->registers->control));
536
537 return EOK;
538}
539
540/** Initialize schedule queues
541 *
542 * @param[in] instance OHCI hc driver structure
543 * @return Error code
544 */
545int hc_init_transfer_lists(hc_t *instance)
546{
547 assert(instance);
548#define SETUP_ENDPOINT_LIST(type) \
549do { \
550 const char *name = usb_str_transfer_type(type); \
551 const int ret = endpoint_list_init(&instance->lists[type], name); \
552 if (ret != EOK) { \
553 usb_log_error("Failed to setup %s endpoint list: %s.", \
554 name, str_error(ret)); \
555 endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]);\
556 endpoint_list_fini(&instance->lists[USB_TRANSFER_INTERRUPT]); \
557 endpoint_list_fini(&instance->lists[USB_TRANSFER_CONTROL]); \
558 endpoint_list_fini(&instance->lists[USB_TRANSFER_BULK]); \
559 return ret; \
560 } \
561} while (0)
562
563 SETUP_ENDPOINT_LIST(USB_TRANSFER_ISOCHRONOUS);
564 SETUP_ENDPOINT_LIST(USB_TRANSFER_INTERRUPT);
565 SETUP_ENDPOINT_LIST(USB_TRANSFER_CONTROL);
566 SETUP_ENDPOINT_LIST(USB_TRANSFER_BULK);
567#undef SETUP_ENDPOINT_LIST
568 endpoint_list_set_next(&instance->lists[USB_TRANSFER_INTERRUPT],
569 &instance->lists[USB_TRANSFER_ISOCHRONOUS]);
570
571 return EOK;
572}
573
574/** Initialize memory structures used by the OHCI hcd.
575 *
576 * @param[in] instance OHCI hc driver structure.
577 * @return Error code.
578 */
579int hc_init_memory(hc_t *instance)
580{
581 assert(instance);
582
583 memset(&instance->rh, 0, sizeof(instance->rh));
584 /* Init queues */
585 int ret = hc_init_transfer_lists(instance);
586 if (ret != EOK) {
587 return ret;
588 }
589
590 /*Init HCCA */
591 instance->hcca = hcca_get();
592 if (instance->hcca == NULL)
593 return ENOMEM;
594 usb_log_debug2("OHCI HCCA initialized at %p.", instance->hcca);
595
596 for (unsigned i = 0; i < HCCA_INT_EP_COUNT; ++i) {
597 hcca_set_int_ep(instance->hcca, i,
598 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
599 }
600 usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").",
601 instance->lists[USB_TRANSFER_INTERRUPT].list_head,
602 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
603
604 if ((ret = ohci_bus_init(&instance->bus, instance))) {
605 usb_log_error("HC(%p): Failed to setup bus : %s",
606 instance, str_error(ret));
607 return ret;
608 }
609
610 hc_device_setup(&instance->base, (bus_t *) &instance->bus);
611
612 return EOK;
613}
614
615/**
616 * @}
617 */
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