source: mainline/uspace/drv/bus/usb/ohci/hc.c@ 3121b5f

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 3121b5f was 6340a6ff, checked in by Jan Vesely <jano.vesely@…>, 12 years ago

ohci: some more macro removal
  • Property mode set to 100644
File size: 16.3 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbohcihc
30 * @{
31 */
32/** @file
33 * @brief OHCI Host controller driver routines
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <adt/list.h>
39#include <libarch/ddi.h>
40
41#include <usb/debug.h>
42#include <usb/usb.h>
43
44#include "hc.h"
45#include "ohci_endpoint.h"
46
47#define OHCI_USED_INTERRUPTS \
48 (I_SO | I_WDH | I_UE | I_RHSC)
49
50static const irq_pio_range_t ohci_pio_ranges[] = {
51 {
52 .base = 0,
53 .size = sizeof(ohci_regs_t)
54 }
55};
56
57static const irq_cmd_t ohci_irq_commands[] = {
58 {
59 .cmd = CMD_PIO_READ_32,
60 .dstarg = 1,
61 .addr = NULL
62 },
63 {
64 .cmd = CMD_AND,
65 .srcarg = 1,
66 .dstarg = 2,
67 .value = 0
68 },
69 {
70 .cmd = CMD_PREDICATE,
71 .srcarg = 2,
72 .value = 2
73 },
74 {
75 .cmd = CMD_PIO_WRITE_A_32,
76 .srcarg = 1,
77 .addr = NULL
78 },
79 {
80 .cmd = CMD_ACCEPT
81 }
82};
83
84static void hc_gain_control(hc_t *instance);
85static void hc_start(hc_t *instance);
86static int hc_init_transfer_lists(hc_t *instance);
87static int hc_init_memory(hc_t *instance);
88static int interrupt_emulator(hc_t *instance);
89
90/** Get number of PIO ranges used in IRQ code.
91 * @return Number of ranges.
92 */
93size_t hc_irq_pio_range_count(void)
94{
95 return sizeof(ohci_pio_ranges) / sizeof(irq_pio_range_t);
96}
97
98/** Get number of commands used in IRQ code.
99 * @return Number of commands.
100 */
101size_t hc_irq_cmd_count(void)
102{
103 return sizeof(ohci_irq_commands) / sizeof(irq_cmd_t);
104}
105
106/** Generate IRQ code.
107 * @param[out] ranges PIO ranges buffer.
108 * @param[in] ranges_size Size of the ranges buffer (bytes).
109 * @param[out] cmds Commands buffer.
110 * @param[in] cmds_size Size of the commands buffer (bytes).
111 * @param[in] regs Physical address of device's registers.
112 * @param[in] reg_size Size of the register area (bytes).
113 *
114 * @return Error code.
115 */
116int
117hc_get_irq_code(irq_pio_range_t ranges[], size_t ranges_size, irq_cmd_t cmds[],
118 size_t cmds_size, uintptr_t regs, size_t reg_size)
119{
120 if ((ranges_size < sizeof(ohci_pio_ranges)) ||
121 (cmds_size < sizeof(ohci_irq_commands)) ||
122 (reg_size < sizeof(ohci_regs_t)))
123 return EOVERFLOW;
124
125 memcpy(ranges, ohci_pio_ranges, sizeof(ohci_pio_ranges));
126 ranges[0].base = regs;
127
128 memcpy(cmds, ohci_irq_commands, sizeof(ohci_irq_commands));
129 ohci_regs_t *registers = (ohci_regs_t *) regs;
130 cmds[0].addr = (void *) &registers->interrupt_status;
131 cmds[3].addr = (void *) &registers->interrupt_status;
132 OHCI_WR(cmds[1].value, OHCI_USED_INTERRUPTS);
133
134 return EOK;
135}
136
137/** Initialize OHCI hc driver structure
138 *
139 * @param[in] instance Memory place for the structure.
140 * @param[in] regs Address of the memory mapped I/O registers.
141 * @param[in] reg_size Size of the memory mapped area.
142 * @param[in] interrupts True if w interrupts should be used
143 * @return Error code
144 */
145int hc_init(hc_t *instance, uintptr_t regs, size_t reg_size, bool interrupts)
146{
147 assert(instance);
148
149 int ret =
150 pio_enable((void*)regs, reg_size, (void**)&instance->registers);
151 if (ret != EOK) {
152 usb_log_error("Failed to enable access to device regss: %s.\n",
153 str_error(ret));
154 return ret;
155 }
156
157 list_initialize(&instance->pending_batches);
158 fibril_mutex_initialize(&instance->guard);
159
160 ret = hc_init_memory(instance);
161 if (ret != EOK) {
162 usb_log_error("Failed to create OHCI memory structures: %s.\n",
163 str_error(ret));
164 return ret;
165 }
166
167 hc_gain_control(instance);
168
169 if (!interrupts) {
170 instance->interrupt_emulator =
171 fibril_create((int(*)(void*))interrupt_emulator, instance);
172 fibril_add_ready(instance->interrupt_emulator);
173 }
174
175 ohci_rh_init(&instance->rh, instance->registers, "ohci rh");
176 hc_start(instance);
177
178 return EOK;
179}
180
181void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
182{
183 assert(instance);
184 assert(ep);
185
186 endpoint_list_t *list = &instance->lists[ep->transfer_type];
187 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
188 assert(list);
189 assert(ohci_ep);
190
191 /* Enqueue ep */
192 switch (ep->transfer_type) {
193 case USB_TRANSFER_CONTROL:
194 OHCI_CLR(instance->registers->control, C_CLE);
195 endpoint_list_add_ep(list, ohci_ep);
196 OHCI_WR(instance->registers->control_current, 0);
197 OHCI_SET(instance->registers->control, C_CLE);
198 break;
199 case USB_TRANSFER_BULK:
200 OHCI_CLR(instance->registers->control, C_BLE);
201 endpoint_list_add_ep(list, ohci_ep);
202 OHCI_WR(instance->registers->bulk_current, 0);
203 OHCI_SET(instance->registers->control, C_BLE);
204 break;
205 case USB_TRANSFER_ISOCHRONOUS:
206 case USB_TRANSFER_INTERRUPT:
207 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
208 endpoint_list_add_ep(list, ohci_ep);
209 OHCI_SET(instance->registers->control, C_PLE | C_IE);
210 break;
211 }
212}
213
214void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
215{
216 assert(instance);
217 assert(ep);
218
219 /* Dequeue ep */
220 endpoint_list_t *list = &instance->lists[ep->transfer_type];
221 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
222
223 assert(list);
224 assert(ohci_ep);
225 switch (ep->transfer_type) {
226 case USB_TRANSFER_CONTROL:
227 OHCI_CLR(instance->registers->control, C_CLE);
228 endpoint_list_remove_ep(list, ohci_ep);
229 OHCI_WR(instance->registers->control_current, 0);
230 OHCI_SET(instance->registers->control, C_CLE);
231 break;
232 case USB_TRANSFER_BULK:
233 OHCI_CLR(instance->registers->control, C_BLE);
234 endpoint_list_remove_ep(list, ohci_ep);
235 OHCI_WR(instance->registers->bulk_current, 0);
236 OHCI_SET(instance->registers->control, C_BLE);
237 break;
238 case USB_TRANSFER_ISOCHRONOUS:
239 case USB_TRANSFER_INTERRUPT:
240 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
241 endpoint_list_remove_ep(list, ohci_ep);
242 OHCI_SET(instance->registers->control, C_PLE | C_IE);
243 break;
244 default:
245 break;
246 }
247}
248
249/** Add USB transfer to the schedule.
250 *
251 * @param[in] instance OHCI hc driver structure.
252 * @param[in] batch Batch representing the transfer.
253 * @return Error code.
254 */
255int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
256{
257 assert(hcd);
258 hc_t *instance = hcd->private_data;
259 assert(instance);
260
261 /* Check for root hub communication */
262 if (batch->ep->address == ohci_rh_get_address(&instance->rh)) {
263 usb_log_debug("OHCI root hub request.\n");
264 return ohci_rh_schedule(&instance->rh, batch);
265 }
266 ohci_transfer_batch_t *ohci_batch = ohci_transfer_batch_get(batch);
267 if (!ohci_batch)
268 return ENOMEM;
269
270 fibril_mutex_lock(&instance->guard);
271 list_append(&ohci_batch->link, &instance->pending_batches);
272 ohci_transfer_batch_commit(ohci_batch);
273
274 /* Control and bulk schedules need a kick to start working */
275 switch (batch->ep->transfer_type)
276 {
277 case USB_TRANSFER_CONTROL:
278 OHCI_SET(instance->registers->command_status, CS_CLF);
279 break;
280 case USB_TRANSFER_BULK:
281 OHCI_SET(instance->registers->command_status, CS_BLF);
282 break;
283 default:
284 break;
285 }
286 fibril_mutex_unlock(&instance->guard);
287 return EOK;
288}
289
290/** Interrupt handling routine
291 *
292 * @param[in] instance OHCI hc driver structure.
293 * @param[in] status Value of the status register at the time of interrupt.
294 */
295void hc_interrupt(hc_t *instance, uint32_t status)
296{
297 status = OHCI_RD(status);
298 assert(instance);
299 if ((status & ~I_SF) == 0) /* ignore sof status */
300 return;
301 usb_log_debug2("OHCI(%p) interrupt: %x.\n", instance, status);
302 if (status & I_RHSC)
303 ohci_rh_interrupt(&instance->rh);
304
305 if (status & I_WDH) {
306 fibril_mutex_lock(&instance->guard);
307 usb_log_debug2("HCCA: %p-%#" PRIx32 " (%p).\n", instance->hcca,
308 OHCI_RD(instance->registers->hcca),
309 (void *) addr_to_phys(instance->hcca));
310 usb_log_debug2("Periodic current: %#" PRIx32 ".\n",
311 OHCI_RD(instance->registers->periodic_current));
312
313 link_t *current = list_first(&instance->pending_batches);
314 while (current && current != &instance->pending_batches.head) {
315 link_t *next = current->next;
316 ohci_transfer_batch_t *batch =
317 ohci_transfer_batch_from_link(current);
318
319 if (ohci_transfer_batch_is_complete(batch)) {
320 list_remove(current);
321 ohci_transfer_batch_finish_dispose(batch);
322 }
323
324 current = next;
325 }
326 fibril_mutex_unlock(&instance->guard);
327 }
328
329 if (status & I_UE) {
330 usb_log_fatal("Error like no other!\n");
331 hc_start(instance);
332 }
333
334}
335
336/** Check status register regularly
337 *
338 * @param[in] instance OHCI hc driver structure.
339 * @return Error code
340 */
341int interrupt_emulator(hc_t *instance)
342{
343 assert(instance);
344 usb_log_info("Started interrupt emulator.\n");
345 while (1) {
346 const uint32_t status = instance->registers->interrupt_status;
347 instance->registers->interrupt_status = status;
348 hc_interrupt(instance, status);
349 async_usleep(10000);
350 }
351 return EOK;
352}
353
354/** Turn off any (BIOS)driver that might be in control of the device.
355 *
356 * This function implements routines described in chapter 5.1.1.3 of the OHCI
357 * specification (page 40, pdf page 54).
358 *
359 * @param[in] instance OHCI hc driver structure.
360 */
361void hc_gain_control(hc_t *instance)
362{
363 assert(instance);
364
365 usb_log_debug("Requesting OHCI control.\n");
366 if (OHCI_RD(instance->registers->revision) & R_LEGACY_FLAG) {
367 /* Turn off legacy emulation, it should be enough to zero
368 * the lowest bit, but it caused problems. Thus clear all
369 * except GateA20 (causes restart on some hw).
370 * See page 145 of the specs for details.
371 */
372 volatile uint32_t *ohci_emulation_reg =
373 (uint32_t*)((char*)instance->registers + LEGACY_REGS_OFFSET);
374 usb_log_debug("OHCI legacy register %p: %x.\n",
375 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
376 /* Zero everything but A20State */
377 OHCI_CLR(*ohci_emulation_reg, ~0x100);
378 usb_log_debug(
379 "OHCI legacy register (should be 0 or 0x100) %p: %x.\n",
380 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
381 }
382
383 /* Interrupt routing enabled => smm driver is active */
384 if (OHCI_RD(instance->registers->control) & C_IR) {
385 usb_log_debug("SMM driver: request ownership change.\n");
386 OHCI_SET(instance->registers->command_status, CS_OCR);
387 /* Hope that SMM actually knows its stuff or we can hang here */
388 while (OHCI_RD(instance->registers->control & C_IR)) {
389 async_usleep(1000);
390 }
391 usb_log_info("SMM driver: Ownership taken.\n");
392 C_HCFS_SET(instance->registers->control, C_HCFS_RESET);
393 async_usleep(50000);
394 return;
395 }
396
397 const unsigned hc_status = C_HCFS_GET(instance->registers->control);
398 /* Interrupt routing disabled && status != USB_RESET => BIOS active */
399 if (hc_status != C_HCFS_RESET) {
400 usb_log_debug("BIOS driver found.\n");
401 if (hc_status == C_HCFS_OPERATIONAL) {
402 usb_log_info("BIOS driver: HC operational.\n");
403 return;
404 }
405 /* HC is suspended assert resume for 20ms */
406 C_HCFS_SET(instance->registers->control, C_HCFS_RESUME);
407 async_usleep(20000);
408 usb_log_info("BIOS driver: HC resumed.\n");
409 return;
410 }
411
412 /* HC is in reset (hw startup) => no other driver
413 * maintain reset for at least the time specified in USB spec (50 ms)*/
414 usb_log_debug("Host controller found in reset state.\n");
415 async_usleep(50000);
416}
417
418/** OHCI hw initialization routine.
419 *
420 * @param[in] instance OHCI hc driver structure.
421 */
422void hc_start(hc_t *instance)
423{
424 /* OHCI guide page 42 */
425 assert(instance);
426 usb_log_debug2("Started hc initialization routine.\n");
427
428 /* Save contents of fm_interval register */
429 const uint32_t fm_interval = OHCI_RD(instance->registers->fm_interval);
430 usb_log_debug2("Old value of HcFmInterval: %x.\n", fm_interval);
431
432 /* Reset hc */
433 usb_log_debug2("HC reset.\n");
434 size_t time = 0;
435 OHCI_WR(instance->registers->command_status, CS_HCR);
436 while (OHCI_RD(instance->registers->command_status) & CS_HCR) {
437 async_usleep(10);
438 time += 10;
439 }
440 usb_log_debug2("HC reset complete in %zu us.\n", time);
441
442 /* Restore fm_interval */
443 OHCI_WR(instance->registers->fm_interval, fm_interval);
444 assert((OHCI_RD(instance->registers->command_status) & CS_HCR) == 0);
445
446 /* hc is now in suspend state */
447 usb_log_debug2("HC should be in suspend state(%x).\n",
448 OHCI_RD(instance->registers->control));
449
450 /* Use HCCA */
451 OHCI_WR(instance->registers->hcca, addr_to_phys(instance->hcca));
452
453 /* Use queues */
454 OHCI_WR(instance->registers->bulk_head,
455 instance->lists[USB_TRANSFER_BULK].list_head_pa);
456 usb_log_debug2("Bulk HEAD set to: %p (%#" PRIx32 ").\n",
457 instance->lists[USB_TRANSFER_BULK].list_head,
458 instance->lists[USB_TRANSFER_BULK].list_head_pa);
459
460 OHCI_WR(instance->registers->control_head,
461 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
462 usb_log_debug2("Control HEAD set to: %p (%#" PRIx32 ").\n",
463 instance->lists[USB_TRANSFER_CONTROL].list_head,
464 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
465
466 /* Enable queues */
467 OHCI_SET(instance->registers->control, (C_PLE | C_IE | C_CLE | C_BLE));
468 usb_log_debug("Queues enabled(%x).\n",
469 OHCI_RD(instance->registers->control));
470
471 /* Enable interrupts */
472 OHCI_WR(instance->registers->interrupt_enable, OHCI_USED_INTERRUPTS);
473 usb_log_debug("Enabled interrupts: %x.\n",
474 OHCI_RD(instance->registers->interrupt_enable));
475 OHCI_WR(instance->registers->interrupt_enable, I_MI);
476
477 /* Set periodic start to 90% */
478 const uint32_t frame_length =
479 (fm_interval >> FMI_FI_SHIFT) & FMI_FI_MASK;
480 OHCI_WR(instance->registers->periodic_start,
481 ((frame_length / 10) * 9) & PS_MASK << PS_SHIFT);
482 usb_log_debug2("All periodic start set to: %x(%u - 90%% of %d).\n",
483 OHCI_RD(instance->registers->periodic_start),
484 OHCI_RD(instance->registers->periodic_start), frame_length);
485 C_HCFS_SET(instance->registers->control, C_HCFS_OPERATIONAL);
486 usb_log_debug("OHCI HC up and running (ctl_reg=0x%x).\n",
487 OHCI_RD(instance->registers->control));
488}
489
490/** Initialize schedule queues
491 *
492 * @param[in] instance OHCI hc driver structure
493 * @return Error code
494 */
495int hc_init_transfer_lists(hc_t *instance)
496{
497 assert(instance);
498#define SETUP_ENDPOINT_LIST(type) \
499do { \
500 const char *name = usb_str_transfer_type(type); \
501 const int ret = endpoint_list_init(&instance->lists[type], name); \
502 if (ret != EOK) { \
503 usb_log_error("Failed to setup %s endpoint list: %s.\n", \
504 name, str_error(ret)); \
505 endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]);\
506 endpoint_list_fini(&instance->lists[USB_TRANSFER_INTERRUPT]); \
507 endpoint_list_fini(&instance->lists[USB_TRANSFER_CONTROL]); \
508 endpoint_list_fini(&instance->lists[USB_TRANSFER_BULK]); \
509 return ret; \
510 } \
511} while (0)
512
513 SETUP_ENDPOINT_LIST(USB_TRANSFER_ISOCHRONOUS);
514 SETUP_ENDPOINT_LIST(USB_TRANSFER_INTERRUPT);
515 SETUP_ENDPOINT_LIST(USB_TRANSFER_CONTROL);
516 SETUP_ENDPOINT_LIST(USB_TRANSFER_BULK);
517#undef SETUP_ENDPOINT_LIST
518 endpoint_list_set_next(&instance->lists[USB_TRANSFER_INTERRUPT],
519 &instance->lists[USB_TRANSFER_ISOCHRONOUS]);
520
521 return EOK;
522}
523
524/** Initialize memory structures used by the OHCI hcd.
525 *
526 * @param[in] instance OHCI hc driver structure.
527 * @return Error code.
528 */
529int hc_init_memory(hc_t *instance)
530{
531 assert(instance);
532
533 memset(&instance->rh, 0, sizeof(instance->rh));
534 /* Init queues */
535 const int ret = hc_init_transfer_lists(instance);
536 if (ret != EOK) {
537 return ret;
538 }
539
540 /*Init HCCA */
541 instance->hcca = hcca_get();
542 if (instance->hcca == NULL)
543 return ENOMEM;
544 usb_log_debug2("OHCI HCCA initialized at %p.\n", instance->hcca);
545
546 for (unsigned i = 0; i < HCCA_INT_EP_COUNT; ++i) {
547 hcca_set_int_ep(instance->hcca, i,
548 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
549 }
550 usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").\n",
551 instance->lists[USB_TRANSFER_INTERRUPT].list_head,
552 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
553
554 return EOK;
555}
556
557/**
558 * @}
559 */
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