source: mainline/uspace/drv/bus/usb/ohci/hc.c@ 2dbfe44

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 2dbfe44 was 2dbfe44, checked in by Jan Vesely <jano.vesely@…>, 10 years ago

ohci: Switch to libusb malloc32 function
  • Property mode set to 100644
File size: 16.9 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbohcihc
30 * @{
31 */
32/** @file
33 * @brief OHCI Host controller driver routines
34 */
35
36#include <assert.h>
37#include <async.h>
38#include <errno.h>
39#include <macros.h>
40#include <mem.h>
41#include <stdlib.h>
42#include <str_error.h>
43#include <sys/types.h>
44
45#include <usb/debug.h>
46#include <usb/usb.h>
47
48#include "ohci_endpoint.h"
49#include "ohci_batch.h"
50
51#include "hc.h"
52
53#define OHCI_USED_INTERRUPTS \
54 (I_SO | I_WDH | I_UE | I_RHSC)
55
56static const irq_pio_range_t ohci_pio_ranges[] = {
57 {
58 .base = 0,
59 .size = sizeof(ohci_regs_t)
60 }
61};
62
63static const irq_cmd_t ohci_irq_commands[] = {
64 {
65 .cmd = CMD_PIO_READ_32,
66 .dstarg = 1,
67 .addr = NULL
68 },
69 {
70 .cmd = CMD_AND,
71 .srcarg = 1,
72 .dstarg = 2,
73 .value = 0
74 },
75 {
76 .cmd = CMD_PREDICATE,
77 .srcarg = 2,
78 .value = 2
79 },
80 {
81 .cmd = CMD_PIO_WRITE_A_32,
82 .srcarg = 1,
83 .addr = NULL
84 },
85 {
86 .cmd = CMD_ACCEPT
87 }
88};
89
90static void hc_gain_control(hc_t *instance);
91static void hc_start(hc_t *instance);
92static int hc_init_transfer_lists(hc_t *instance);
93static int hc_init_memory(hc_t *instance);
94
95/** Generate IRQ code.
96 * @param[out] ranges PIO ranges buffer.
97 * @param[in] ranges_size Size of the ranges buffer (bytes).
98 * @param[out] cmds Commands buffer.
99 * @param[in] cmds_size Size of the commands buffer (bytes).
100 * @param[in] hw_res Device's resources.
101 *
102 * @return Error code.
103 */
104int ohci_hc_gen_irq_code(irq_code_t *code, const hw_res_list_parsed_t *hw_res)
105{
106 assert(code);
107 assert(hw_res);
108
109 if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
110 return EINVAL;
111
112 const addr_range_t regs = hw_res->mem_ranges.ranges[0];
113
114 if (RNGSZ(regs) < sizeof(ohci_regs_t))
115 return EOVERFLOW;
116
117 code->ranges = malloc(sizeof(ohci_pio_ranges));
118 if (code->ranges == NULL)
119 return ENOMEM;
120
121 code->cmds = malloc(sizeof(ohci_irq_commands));
122 if (code->cmds == NULL) {
123 free(code->ranges);
124 return ENOMEM;
125 }
126
127 code->rangecount = ARRAY_SIZE(ohci_pio_ranges);
128 code->cmdcount = ARRAY_SIZE(ohci_irq_commands);
129
130 memcpy(code->ranges, ohci_pio_ranges, sizeof(ohci_pio_ranges));
131 code->ranges[0].base = RNGABS(regs);
132
133 memcpy(code->cmds, ohci_irq_commands, sizeof(ohci_irq_commands));
134 ohci_regs_t *registers = (ohci_regs_t *) RNGABSPTR(regs);
135 code->cmds[0].addr = (void *) &registers->interrupt_status;
136 code->cmds[3].addr = (void *) &registers->interrupt_status;
137 OHCI_WR(code->cmds[1].value, OHCI_USED_INTERRUPTS);
138
139 usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.\n",
140 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
141
142 return hw_res->irqs.irqs[0];
143}
144
145/** Initialize OHCI hc driver structure
146 *
147 * @param[in] instance Memory place for the structure.
148 * @param[in] regs Device's resources
149 * @param[in] interrupts True if w interrupts should be used
150 * @return Error code
151 */
152int hc_init(hc_t *instance, const hw_res_list_parsed_t *hw_res, bool interrupts)
153{
154 assert(instance);
155 assert(hw_res);
156 if (hw_res->mem_ranges.count != 1 ||
157 hw_res->mem_ranges.ranges[0].size < sizeof(ohci_regs_t))
158 return EINVAL;
159
160 int ret = pio_enable_range(&hw_res->mem_ranges.ranges[0],
161 (void **) &instance->registers);
162 if (ret != EOK) {
163 usb_log_error("Failed to gain access to registers: %s.\n",
164 str_error(ret));
165 return ret;
166 }
167 usb_log_debug("Device registers at %" PRIx64 " (%zuB) accessible.\n",
168 hw_res->mem_ranges.ranges[0].address.absolute,
169 hw_res->mem_ranges.ranges[0].size);
170
171 list_initialize(&instance->pending_batches);
172 fibril_mutex_initialize(&instance->guard);
173 instance->hw_interrupts = interrupts;
174
175 ret = hc_init_memory(instance);
176 if (ret != EOK) {
177 usb_log_error("Failed to create OHCI memory structures: %s.\n",
178 str_error(ret));
179 //TODO: We should disable pio access here
180 return ret;
181 }
182
183 hc_gain_control(instance);
184
185 ohci_rh_init(&instance->rh, instance->registers, "ohci rh");
186 hc_start(instance);
187
188 return EOK;
189}
190
191/** Safely dispose host controller internal structures
192 *
193 * @param[in] instance Host controller structure to use.
194 */
195void hc_fini(hc_t *instance)
196{
197 assert(instance);
198 /* TODO: implement*/
199};
200
201void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
202{
203 assert(instance);
204 assert(ep);
205
206 endpoint_list_t *list = &instance->lists[ep->transfer_type];
207 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
208 assert(list);
209 assert(ohci_ep);
210
211 /* Enqueue ep */
212 switch (ep->transfer_type) {
213 case USB_TRANSFER_CONTROL:
214 OHCI_CLR(instance->registers->control, C_CLE);
215 endpoint_list_add_ep(list, ohci_ep);
216 OHCI_WR(instance->registers->control_current, 0);
217 OHCI_SET(instance->registers->control, C_CLE);
218 break;
219 case USB_TRANSFER_BULK:
220 OHCI_CLR(instance->registers->control, C_BLE);
221 endpoint_list_add_ep(list, ohci_ep);
222 OHCI_WR(instance->registers->bulk_current, 0);
223 OHCI_SET(instance->registers->control, C_BLE);
224 break;
225 case USB_TRANSFER_ISOCHRONOUS:
226 case USB_TRANSFER_INTERRUPT:
227 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
228 endpoint_list_add_ep(list, ohci_ep);
229 OHCI_SET(instance->registers->control, C_PLE | C_IE);
230 break;
231 }
232}
233
234void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
235{
236 assert(instance);
237 assert(ep);
238
239 /* Dequeue ep */
240 endpoint_list_t *list = &instance->lists[ep->transfer_type];
241 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
242
243 assert(list);
244 assert(ohci_ep);
245 switch (ep->transfer_type) {
246 case USB_TRANSFER_CONTROL:
247 OHCI_CLR(instance->registers->control, C_CLE);
248 endpoint_list_remove_ep(list, ohci_ep);
249 OHCI_WR(instance->registers->control_current, 0);
250 OHCI_SET(instance->registers->control, C_CLE);
251 break;
252 case USB_TRANSFER_BULK:
253 OHCI_CLR(instance->registers->control, C_BLE);
254 endpoint_list_remove_ep(list, ohci_ep);
255 OHCI_WR(instance->registers->bulk_current, 0);
256 OHCI_SET(instance->registers->control, C_BLE);
257 break;
258 case USB_TRANSFER_ISOCHRONOUS:
259 case USB_TRANSFER_INTERRUPT:
260 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
261 endpoint_list_remove_ep(list, ohci_ep);
262 OHCI_SET(instance->registers->control, C_PLE | C_IE);
263 break;
264 default:
265 break;
266 }
267}
268
269int ohci_hc_status(hcd_t *hcd, uint32_t *status)
270{
271 assert(hcd);
272 assert(status);
273 hc_t *instance = hcd->driver.data;
274 assert(instance);
275
276 if (instance->registers){
277 *status = OHCI_RD(instance->registers->interrupt_status);
278 OHCI_WR(instance->registers->interrupt_status, *status);
279 }
280 return EOK;
281}
282
283/** Add USB transfer to the schedule.
284 *
285 * @param[in] hcd HCD driver structure.
286 * @param[in] batch Batch representing the transfer.
287 * @return Error code.
288 */
289int ohci_hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
290{
291 assert(hcd);
292 hc_t *instance = hcd->driver.data;
293 assert(instance);
294
295 /* Check for root hub communication */
296 if (batch->ep->address == ohci_rh_get_address(&instance->rh)) {
297 usb_log_debug("OHCI root hub request.\n");
298 return ohci_rh_schedule(&instance->rh, batch);
299 }
300 ohci_transfer_batch_t *ohci_batch = ohci_transfer_batch_get(batch);
301 if (!ohci_batch)
302 return ENOMEM;
303
304 fibril_mutex_lock(&instance->guard);
305 list_append(&ohci_batch->link, &instance->pending_batches);
306 ohci_transfer_batch_commit(ohci_batch);
307
308 /* Control and bulk schedules need a kick to start working */
309 switch (batch->ep->transfer_type)
310 {
311 case USB_TRANSFER_CONTROL:
312 OHCI_SET(instance->registers->command_status, CS_CLF);
313 break;
314 case USB_TRANSFER_BULK:
315 OHCI_SET(instance->registers->command_status, CS_BLF);
316 break;
317 default:
318 break;
319 }
320 fibril_mutex_unlock(&instance->guard);
321 return EOK;
322}
323
324/** Interrupt handling routine
325 *
326 * @param[in] hcd HCD driver structure.
327 * @param[in] status Value of the status register at the time of interrupt.
328 */
329void ohci_hc_interrupt(hcd_t *hcd, uint32_t status)
330{
331 assert(hcd);
332 hc_t *instance = hcd->driver.data;
333 status = OHCI_RD(status);
334 assert(instance);
335 if ((status & ~I_SF) == 0) /* ignore sof status */
336 return;
337 usb_log_debug2("OHCI(%p) interrupt: %x.\n", instance, status);
338 if (status & I_RHSC)
339 ohci_rh_interrupt(&instance->rh);
340
341 if (status & I_WDH) {
342 fibril_mutex_lock(&instance->guard);
343 usb_log_debug2("HCCA: %p-%#" PRIx32 " (%p).\n", instance->hcca,
344 OHCI_RD(instance->registers->hcca),
345 (void *) addr_to_phys(instance->hcca));
346 usb_log_debug2("Periodic current: %#" PRIx32 ".\n",
347 OHCI_RD(instance->registers->periodic_current));
348
349 link_t *current = list_first(&instance->pending_batches);
350 while (current && current != &instance->pending_batches.head) {
351 link_t *next = current->next;
352 ohci_transfer_batch_t *batch =
353 ohci_transfer_batch_from_link(current);
354
355 if (ohci_transfer_batch_is_complete(batch)) {
356 list_remove(current);
357 ohci_transfer_batch_finish_dispose(batch);
358 }
359
360 current = next;
361 }
362 fibril_mutex_unlock(&instance->guard);
363 }
364
365 if (status & I_UE) {
366 usb_log_fatal("Error like no other!\n");
367 hc_start(instance);
368 }
369
370}
371
372/** Turn off any (BIOS)driver that might be in control of the device.
373 *
374 * This function implements routines described in chapter 5.1.1.3 of the OHCI
375 * specification (page 40, pdf page 54).
376 *
377 * @param[in] instance OHCI hc driver structure.
378 */
379void hc_gain_control(hc_t *instance)
380{
381 assert(instance);
382
383 usb_log_debug("Requesting OHCI control.\n");
384 if (OHCI_RD(instance->registers->revision) & R_LEGACY_FLAG) {
385 /* Turn off legacy emulation, it should be enough to zero
386 * the lowest bit, but it caused problems. Thus clear all
387 * except GateA20 (causes restart on some hw).
388 * See page 145 of the specs for details.
389 */
390 volatile uint32_t *ohci_emulation_reg =
391 (uint32_t*)((char*)instance->registers + LEGACY_REGS_OFFSET);
392 usb_log_debug("OHCI legacy register %p: %x.\n",
393 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
394 /* Zero everything but A20State */
395 //TODO: should we ack interrupts before doing this?
396 OHCI_CLR(*ohci_emulation_reg, ~0x100);
397 usb_log_debug(
398 "OHCI legacy register (should be 0 or 0x100) %p: %x.\n",
399 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
400 }
401
402 /* Interrupt routing enabled => smm driver is active */
403 if (OHCI_RD(instance->registers->control) & C_IR) {
404 usb_log_debug("SMM driver: request ownership change.\n");
405 //TODO: should we ack interrupts before doing this?
406 OHCI_SET(instance->registers->command_status, CS_OCR);
407 /* Hope that SMM actually knows its stuff or we can hang here */
408 while (OHCI_RD(instance->registers->control) & C_IR) {
409 async_usleep(1000);
410 }
411 usb_log_info("SMM driver: Ownership taken.\n");
412 C_HCFS_SET(instance->registers->control, C_HCFS_RESET);
413 async_usleep(50000);
414 return;
415 }
416
417 const unsigned hc_status = C_HCFS_GET(instance->registers->control);
418 /* Interrupt routing disabled && status != USB_RESET => BIOS active */
419 if (hc_status != C_HCFS_RESET) {
420 usb_log_debug("BIOS driver found.\n");
421 if (hc_status == C_HCFS_OPERATIONAL) {
422 usb_log_info("BIOS driver: HC operational.\n");
423 return;
424 }
425 /* HC is suspended assert resume for 20ms */
426 C_HCFS_SET(instance->registers->control, C_HCFS_RESUME);
427 async_usleep(20000);
428 usb_log_info("BIOS driver: HC resumed.\n");
429 return;
430 }
431
432 /* HC is in reset (hw startup) => no other driver
433 * maintain reset for at least the time specified in USB spec (50 ms)*/
434 usb_log_debug("Host controller found in reset state.\n");
435 async_usleep(50000);
436}
437
438/** OHCI hw initialization routine.
439 *
440 * @param[in] instance OHCI hc driver structure.
441 */
442void hc_start(hc_t *instance)
443{
444 /* OHCI guide page 42 */
445 assert(instance);
446 usb_log_debug2("Started hc initialization routine.\n");
447
448 /* Save contents of fm_interval register */
449 const uint32_t fm_interval = OHCI_RD(instance->registers->fm_interval);
450 usb_log_debug2("Old value of HcFmInterval: %x.\n", fm_interval);
451
452 /* Reset hc */
453 usb_log_debug2("HC reset.\n");
454 size_t time = 0;
455 OHCI_WR(instance->registers->command_status, CS_HCR);
456 while (OHCI_RD(instance->registers->command_status) & CS_HCR) {
457 async_usleep(10);
458 time += 10;
459 }
460 usb_log_debug2("HC reset complete in %zu us.\n", time);
461
462 /* Restore fm_interval */
463 OHCI_WR(instance->registers->fm_interval, fm_interval);
464 assert((OHCI_RD(instance->registers->command_status) & CS_HCR) == 0);
465
466 /* hc is now in suspend state */
467 usb_log_debug2("HC should be in suspend state(%x).\n",
468 OHCI_RD(instance->registers->control));
469
470 /* Use HCCA */
471 OHCI_WR(instance->registers->hcca, addr_to_phys(instance->hcca));
472
473 /* Use queues */
474 OHCI_WR(instance->registers->bulk_head,
475 instance->lists[USB_TRANSFER_BULK].list_head_pa);
476 usb_log_debug2("Bulk HEAD set to: %p (%#" PRIx32 ").\n",
477 instance->lists[USB_TRANSFER_BULK].list_head,
478 instance->lists[USB_TRANSFER_BULK].list_head_pa);
479
480 OHCI_WR(instance->registers->control_head,
481 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
482 usb_log_debug2("Control HEAD set to: %p (%#" PRIx32 ").\n",
483 instance->lists[USB_TRANSFER_CONTROL].list_head,
484 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
485
486 /* Enable queues */
487 OHCI_SET(instance->registers->control, (C_PLE | C_IE | C_CLE | C_BLE));
488 usb_log_debug("Queues enabled(%x).\n",
489 OHCI_RD(instance->registers->control));
490
491 /* Enable interrupts */
492 if (instance->hw_interrupts) {
493 OHCI_WR(instance->registers->interrupt_enable,
494 OHCI_USED_INTERRUPTS);
495 usb_log_debug("Enabled interrupts: %x.\n",
496 OHCI_RD(instance->registers->interrupt_enable));
497 OHCI_WR(instance->registers->interrupt_enable, I_MI);
498 }
499
500 /* Set periodic start to 90% */
501 const uint32_t frame_length =
502 (fm_interval >> FMI_FI_SHIFT) & FMI_FI_MASK;
503 OHCI_WR(instance->registers->periodic_start,
504 ((frame_length / 10) * 9) & PS_MASK << PS_SHIFT);
505 usb_log_debug2("All periodic start set to: %x(%u - 90%% of %d).\n",
506 OHCI_RD(instance->registers->periodic_start),
507 OHCI_RD(instance->registers->periodic_start), frame_length);
508 C_HCFS_SET(instance->registers->control, C_HCFS_OPERATIONAL);
509 usb_log_debug("OHCI HC up and running (ctl_reg=0x%x).\n",
510 OHCI_RD(instance->registers->control));
511}
512
513/** Initialize schedule queues
514 *
515 * @param[in] instance OHCI hc driver structure
516 * @return Error code
517 */
518int hc_init_transfer_lists(hc_t *instance)
519{
520 assert(instance);
521#define SETUP_ENDPOINT_LIST(type) \
522do { \
523 const char *name = usb_str_transfer_type(type); \
524 const int ret = endpoint_list_init(&instance->lists[type], name); \
525 if (ret != EOK) { \
526 usb_log_error("Failed to setup %s endpoint list: %s.\n", \
527 name, str_error(ret)); \
528 endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]);\
529 endpoint_list_fini(&instance->lists[USB_TRANSFER_INTERRUPT]); \
530 endpoint_list_fini(&instance->lists[USB_TRANSFER_CONTROL]); \
531 endpoint_list_fini(&instance->lists[USB_TRANSFER_BULK]); \
532 return ret; \
533 } \
534} while (0)
535
536 SETUP_ENDPOINT_LIST(USB_TRANSFER_ISOCHRONOUS);
537 SETUP_ENDPOINT_LIST(USB_TRANSFER_INTERRUPT);
538 SETUP_ENDPOINT_LIST(USB_TRANSFER_CONTROL);
539 SETUP_ENDPOINT_LIST(USB_TRANSFER_BULK);
540#undef SETUP_ENDPOINT_LIST
541 endpoint_list_set_next(&instance->lists[USB_TRANSFER_INTERRUPT],
542 &instance->lists[USB_TRANSFER_ISOCHRONOUS]);
543
544 return EOK;
545}
546
547/** Initialize memory structures used by the OHCI hcd.
548 *
549 * @param[in] instance OHCI hc driver structure.
550 * @return Error code.
551 */
552int hc_init_memory(hc_t *instance)
553{
554 assert(instance);
555
556 memset(&instance->rh, 0, sizeof(instance->rh));
557 /* Init queues */
558 const int ret = hc_init_transfer_lists(instance);
559 if (ret != EOK) {
560 return ret;
561 }
562
563 /*Init HCCA */
564 instance->hcca = hcca_get();
565 if (instance->hcca == NULL)
566 return ENOMEM;
567 usb_log_debug2("OHCI HCCA initialized at %p.\n", instance->hcca);
568
569 for (unsigned i = 0; i < HCCA_INT_EP_COUNT; ++i) {
570 hcca_set_int_ep(instance->hcca, i,
571 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
572 }
573 usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").\n",
574 instance->lists[USB_TRANSFER_INTERRUPT].list_head,
575 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
576
577 return EOK;
578}
579
580/**
581 * @}
582 */
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