source: mainline/uspace/drv/bus/usb/ohci/hc.c@ 0eb2a0f

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 0eb2a0f was f51587f5, checked in by Jan Vesely <jano.vesely@…>, 13 years ago

ohci: Move generic hcd initialization out of device hc init.
  • Property mode set to 100644
File size: 16.4 KB
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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbohcihc
30 * @{
31 */
32/** @file
33 * @brief OHCI Host controller driver routines
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <adt/list.h>
39#include <libarch/ddi.h>
40
41#include <usb/debug.h>
42#include <usb/usb.h>
43#include <usb/ddfiface.h>
44
45#include "hc.h"
46#include "ohci_endpoint.h"
47
48#define OHCI_USED_INTERRUPTS \
49 (I_SO | I_WDH | I_UE | I_RHSC)
50
51static const irq_pio_range_t ohci_pio_ranges[] = {
52 {
53 .base = 0,
54 .size = sizeof(ohci_regs_t)
55 }
56};
57
58static const irq_cmd_t ohci_irq_commands[] = {
59 {
60 .cmd = CMD_PIO_READ_32,
61 .dstarg = 1,
62 .addr = NULL
63 },
64 {
65 .cmd = CMD_AND,
66 .srcarg = 1,
67 .dstarg = 2,
68 .value = 0
69 },
70 {
71 .cmd = CMD_PREDICATE,
72 .srcarg = 2,
73 .value = 2
74 },
75 {
76 .cmd = CMD_PIO_WRITE_A_32,
77 .srcarg = 1,
78 .addr = NULL
79 },
80 {
81 .cmd = CMD_ACCEPT
82 }
83};
84
85static void hc_gain_control(hc_t *instance);
86static void hc_start(hc_t *instance);
87static int hc_init_transfer_lists(hc_t *instance);
88static int hc_init_memory(hc_t *instance);
89static int interrupt_emulator(hc_t *instance);
90
91/** Get number of PIO ranges used in IRQ code.
92 * @return Number of ranges.
93 */
94size_t hc_irq_pio_range_count(void)
95{
96 return sizeof(ohci_pio_ranges) / sizeof(irq_pio_range_t);
97}
98
99/** Get number of commands used in IRQ code.
100 * @return Number of commands.
101 */
102size_t hc_irq_cmd_count(void)
103{
104 return sizeof(ohci_irq_commands) / sizeof(irq_cmd_t);
105}
106
107/** Generate IRQ code.
108 * @param[out] ranges PIO ranges buffer.
109 * @param[in] ranges_size Size of the ranges buffer (bytes).
110 * @param[out] cmds Commands buffer.
111 * @param[in] cmds_size Size of the commands buffer (bytes).
112 * @param[in] regs Physical address of device's registers.
113 * @param[in] reg_size Size of the register area (bytes).
114 *
115 * @return Error code.
116 */
117int
118hc_get_irq_code(irq_pio_range_t ranges[], size_t ranges_size, irq_cmd_t cmds[],
119 size_t cmds_size, uintptr_t regs, size_t reg_size)
120{
121 if ((ranges_size < sizeof(ohci_pio_ranges)) ||
122 (cmds_size < sizeof(ohci_irq_commands)) ||
123 (reg_size < sizeof(ohci_regs_t)))
124 return EOVERFLOW;
125
126 memcpy(ranges, ohci_pio_ranges, sizeof(ohci_pio_ranges));
127 ranges[0].base = regs;
128
129 memcpy(cmds, ohci_irq_commands, sizeof(ohci_irq_commands));
130 ohci_regs_t *registers = (ohci_regs_t *) regs;
131 cmds[0].addr = (void *) &registers->interrupt_status;
132 cmds[3].addr = (void *) &registers->interrupt_status;
133 OHCI_WR(cmds[1].value, OHCI_USED_INTERRUPTS);
134
135 return EOK;
136}
137
138/** Initialize OHCI hc driver structure
139 *
140 * @param[in] instance Memory place for the structure.
141 * @param[in] regs Address of the memory mapped I/O registers.
142 * @param[in] reg_size Size of the memory mapped area.
143 * @param[in] interrupts True if w interrupts should be used
144 * @return Error code
145 */
146int hc_init(hc_t *instance, uintptr_t regs, size_t reg_size, bool interrupts)
147{
148 assert(instance);
149
150#define CHECK_RET_RETURN(ret, message...) \
151if (ret != EOK) { \
152 usb_log_error(message); \
153 return ret; \
154} else (void)0
155
156 int ret =
157 pio_enable((void*)regs, reg_size, (void**)&instance->registers);
158 CHECK_RET_RETURN(ret,
159 "Failed to gain access to device registers: %s.\n", str_error(ret));
160
161 list_initialize(&instance->pending_batches);
162
163 ret = hc_init_memory(instance);
164 CHECK_RET_RETURN(ret, "Failed to create OHCI memory structures: %s.\n",
165 str_error(ret));
166#undef CHECK_RET_RETURN
167
168 fibril_mutex_initialize(&instance->guard);
169
170 hc_gain_control(instance);
171
172 if (!interrupts) {
173 instance->interrupt_emulator =
174 fibril_create((int(*)(void*))interrupt_emulator, instance);
175 fibril_add_ready(instance->interrupt_emulator);
176 }
177
178 rh_init(&instance->rh, instance->registers);
179 hc_start(instance);
180
181 return EOK;
182}
183
184void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
185{
186 assert(instance);
187 assert(ep);
188
189 endpoint_list_t *list = &instance->lists[ep->transfer_type];
190 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
191 assert(list);
192 assert(ohci_ep);
193
194 /* Enqueue ep */
195 switch (ep->transfer_type) {
196 case USB_TRANSFER_CONTROL:
197 OHCI_CLR(instance->registers->control, C_CLE);
198 endpoint_list_add_ep(list, ohci_ep);
199 OHCI_WR(instance->registers->control_current, 0);
200 OHCI_SET(instance->registers->control, C_CLE);
201 break;
202 case USB_TRANSFER_BULK:
203 OHCI_CLR(instance->registers->control, C_BLE);
204 endpoint_list_add_ep(list, ohci_ep);
205 OHCI_WR(instance->registers->bulk_current, 0);
206 OHCI_SET(instance->registers->control, C_BLE);
207 break;
208 case USB_TRANSFER_ISOCHRONOUS:
209 case USB_TRANSFER_INTERRUPT:
210 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
211 endpoint_list_add_ep(list, ohci_ep);
212 OHCI_SET(instance->registers->control, C_PLE | C_IE);
213 break;
214 }
215}
216
217void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
218{
219 assert(instance);
220 assert(ep);
221
222 /* Dequeue ep */
223 endpoint_list_t *list = &instance->lists[ep->transfer_type];
224 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
225
226 assert(list);
227 assert(ohci_ep);
228 switch (ep->transfer_type) {
229 case USB_TRANSFER_CONTROL:
230 OHCI_CLR(instance->registers->control, C_CLE);
231 endpoint_list_remove_ep(list, ohci_ep);
232 OHCI_WR(instance->registers->control_current, 0);
233 OHCI_SET(instance->registers->control, C_CLE);
234 break;
235 case USB_TRANSFER_BULK:
236 OHCI_CLR(instance->registers->control, C_BLE);
237 endpoint_list_remove_ep(list, ohci_ep);
238 OHCI_WR(instance->registers->bulk_current, 0);
239 OHCI_SET(instance->registers->control, C_BLE);
240 break;
241 case USB_TRANSFER_ISOCHRONOUS:
242 case USB_TRANSFER_INTERRUPT:
243 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
244 endpoint_list_remove_ep(list, ohci_ep);
245 OHCI_SET(instance->registers->control, C_PLE | C_IE);
246 break;
247 default:
248 break;
249 }
250}
251
252/** Add USB transfer to the schedule.
253 *
254 * @param[in] instance OHCI hc driver structure.
255 * @param[in] batch Batch representing the transfer.
256 * @return Error code.
257 */
258int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
259{
260 assert(hcd);
261 hc_t *instance = hcd->private_data;
262 assert(instance);
263
264 /* Check for root hub communication */
265 if (batch->ep->address == instance->rh.address) {
266 usb_log_debug("OHCI root hub request.\n");
267 rh_request(&instance->rh, batch);
268 return EOK;
269 }
270 ohci_transfer_batch_t *ohci_batch = ohci_transfer_batch_get(batch);
271 if (!ohci_batch)
272 return ENOMEM;
273
274 fibril_mutex_lock(&instance->guard);
275 list_append(&ohci_batch->link, &instance->pending_batches);
276 ohci_transfer_batch_commit(ohci_batch);
277
278 /* Control and bulk schedules need a kick to start working */
279 switch (batch->ep->transfer_type)
280 {
281 case USB_TRANSFER_CONTROL:
282 OHCI_SET(instance->registers->command_status, CS_CLF);
283 break;
284 case USB_TRANSFER_BULK:
285 OHCI_SET(instance->registers->command_status, CS_BLF);
286 break;
287 default:
288 break;
289 }
290 fibril_mutex_unlock(&instance->guard);
291 return EOK;
292}
293
294/** Interrupt handling routine
295 *
296 * @param[in] instance OHCI hc driver structure.
297 * @param[in] status Value of the status register at the time of interrupt.
298 */
299void hc_interrupt(hc_t *instance, uint32_t status)
300{
301 status = OHCI_RD(status);
302 assert(instance);
303 if ((status & ~I_SF) == 0) /* ignore sof status */
304 return;
305 usb_log_debug2("OHCI(%p) interrupt: %x.\n", instance, status);
306 if (status & I_RHSC)
307 rh_interrupt(&instance->rh);
308
309 if (status & I_WDH) {
310 fibril_mutex_lock(&instance->guard);
311 usb_log_debug2("HCCA: %p-%#" PRIx32 " (%p).\n", instance->hcca,
312 OHCI_RD(instance->registers->hcca),
313 (void *) addr_to_phys(instance->hcca));
314 usb_log_debug2("Periodic current: %#" PRIx32 ".\n",
315 OHCI_RD(instance->registers->periodic_current));
316
317 link_t *current = list_first(&instance->pending_batches);
318 while (current && current != &instance->pending_batches.head) {
319 link_t *next = current->next;
320 ohci_transfer_batch_t *batch =
321 ohci_transfer_batch_from_link(current);
322
323 if (ohci_transfer_batch_is_complete(batch)) {
324 list_remove(current);
325 ohci_transfer_batch_finish_dispose(batch);
326 }
327
328 current = next;
329 }
330 fibril_mutex_unlock(&instance->guard);
331 }
332
333 if (status & I_UE) {
334 usb_log_fatal("Error like no other!\n");
335 hc_start(instance);
336 }
337
338}
339
340/** Check status register regularly
341 *
342 * @param[in] instance OHCI hc driver structure.
343 * @return Error code
344 */
345int interrupt_emulator(hc_t *instance)
346{
347 assert(instance);
348 usb_log_info("Started interrupt emulator.\n");
349 while (1) {
350 const uint32_t status = instance->registers->interrupt_status;
351 instance->registers->interrupt_status = status;
352 hc_interrupt(instance, status);
353 async_usleep(10000);
354 }
355 return EOK;
356}
357
358/** Turn off any (BIOS)driver that might be in control of the device.
359 *
360 * This function implements routines described in chapter 5.1.1.3 of the OHCI
361 * specification (page 40, pdf page 54).
362 *
363 * @param[in] instance OHCI hc driver structure.
364 */
365void hc_gain_control(hc_t *instance)
366{
367 assert(instance);
368
369 usb_log_debug("Requesting OHCI control.\n");
370 if (OHCI_RD(instance->registers->revision) & R_LEGACY_FLAG) {
371 /* Turn off legacy emulation, it should be enough to zero
372 * the lowest bit, but it caused problems. Thus clear all
373 * except GateA20 (causes restart on some hw).
374 * See page 145 of the specs for details.
375 */
376 volatile uint32_t *ohci_emulation_reg =
377 (uint32_t*)((char*)instance->registers + LEGACY_REGS_OFFSET);
378 usb_log_debug("OHCI legacy register %p: %x.\n",
379 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
380 /* Zero everything but A20State */
381 OHCI_CLR(*ohci_emulation_reg, ~0x100);
382 usb_log_debug(
383 "OHCI legacy register (should be 0 or 0x100) %p: %x.\n",
384 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
385 }
386
387 /* Interrupt routing enabled => smm driver is active */
388 if (OHCI_RD(instance->registers->control) & C_IR) {
389 usb_log_debug("SMM driver: request ownership change.\n");
390 OHCI_SET(instance->registers->command_status, CS_OCR);
391 /* Hope that SMM actually knows its stuff or we can hang here */
392 while (OHCI_RD(instance->registers->control & C_IR)) {
393 async_usleep(1000);
394 }
395 usb_log_info("SMM driver: Ownership taken.\n");
396 C_HCFS_SET(instance->registers->control, C_HCFS_RESET);
397 async_usleep(50000);
398 return;
399 }
400
401 const unsigned hc_status = C_HCFS_GET(instance->registers->control);
402 /* Interrupt routing disabled && status != USB_RESET => BIOS active */
403 if (hc_status != C_HCFS_RESET) {
404 usb_log_debug("BIOS driver found.\n");
405 if (hc_status == C_HCFS_OPERATIONAL) {
406 usb_log_info("BIOS driver: HC operational.\n");
407 return;
408 }
409 /* HC is suspended assert resume for 20ms */
410 C_HCFS_SET(instance->registers->control, C_HCFS_RESUME);
411 async_usleep(20000);
412 usb_log_info("BIOS driver: HC resumed.\n");
413 return;
414 }
415
416 /* HC is in reset (hw startup) => no other driver
417 * maintain reset for at least the time specified in USB spec (50 ms)*/
418 usb_log_debug("Host controller found in reset state.\n");
419 async_usleep(50000);
420}
421
422/** OHCI hw initialization routine.
423 *
424 * @param[in] instance OHCI hc driver structure.
425 */
426void hc_start(hc_t *instance)
427{
428 /* OHCI guide page 42 */
429 assert(instance);
430 usb_log_debug2("Started hc initialization routine.\n");
431
432 /* Save contents of fm_interval register */
433 const uint32_t fm_interval = OHCI_RD(instance->registers->fm_interval);
434 usb_log_debug2("Old value of HcFmInterval: %x.\n", fm_interval);
435
436 /* Reset hc */
437 usb_log_debug2("HC reset.\n");
438 size_t time = 0;
439 OHCI_WR(instance->registers->command_status, CS_HCR);
440 while (OHCI_RD(instance->registers->command_status) & CS_HCR) {
441 async_usleep(10);
442 time += 10;
443 }
444 usb_log_debug2("HC reset complete in %zu us.\n", time);
445
446 /* Restore fm_interval */
447 OHCI_WR(instance->registers->fm_interval, fm_interval);
448 assert((OHCI_RD(instance->registers->command_status) & CS_HCR) == 0);
449
450 /* hc is now in suspend state */
451 usb_log_debug2("HC should be in suspend state(%x).\n",
452 OHCI_RD(instance->registers->control));
453
454 /* Use HCCA */
455 OHCI_WR(instance->registers->hcca, addr_to_phys(instance->hcca));
456
457 /* Use queues */
458 OHCI_WR(instance->registers->bulk_head,
459 instance->lists[USB_TRANSFER_BULK].list_head_pa);
460 usb_log_debug2("Bulk HEAD set to: %p (%#" PRIx32 ").\n",
461 instance->lists[USB_TRANSFER_BULK].list_head,
462 instance->lists[USB_TRANSFER_BULK].list_head_pa);
463
464 OHCI_WR(instance->registers->control_head,
465 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
466 usb_log_debug2("Control HEAD set to: %p (%#" PRIx32 ").\n",
467 instance->lists[USB_TRANSFER_CONTROL].list_head,
468 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
469
470 /* Enable queues */
471 OHCI_SET(instance->registers->control, (C_PLE | C_IE | C_CLE | C_BLE));
472 usb_log_debug("Queues enabled(%x).\n",
473 OHCI_RD(instance->registers->control));
474
475 /* Enable interrupts */
476 OHCI_WR(instance->registers->interrupt_enable, OHCI_USED_INTERRUPTS);
477 usb_log_debug("Enabled interrupts: %x.\n",
478 OHCI_RD(instance->registers->interrupt_enable));
479 OHCI_WR(instance->registers->interrupt_enable, I_MI);
480
481 /* Set periodic start to 90% */
482 const uint32_t frame_length =
483 (fm_interval >> FMI_FI_SHIFT) & FMI_FI_MASK;
484 OHCI_WR(instance->registers->periodic_start,
485 ((frame_length / 10) * 9) & PS_MASK << PS_SHIFT);
486 usb_log_debug2("All periodic start set to: %x(%u - 90%% of %d).\n",
487 OHCI_RD(instance->registers->periodic_start),
488 OHCI_RD(instance->registers->periodic_start), frame_length);
489 C_HCFS_SET(instance->registers->control, C_HCFS_OPERATIONAL);
490 usb_log_debug("OHCI HC up and running (ctl_reg=0x%x).\n",
491 OHCI_RD(instance->registers->control));
492}
493
494/** Initialize schedule queues
495 *
496 * @param[in] instance OHCI hc driver structure
497 * @return Error code
498 */
499int hc_init_transfer_lists(hc_t *instance)
500{
501 assert(instance);
502#define SETUP_ENDPOINT_LIST(type) \
503do { \
504 const char *name = usb_str_transfer_type(type); \
505 int ret = endpoint_list_init(&instance->lists[type], name); \
506 if (ret != EOK) { \
507 usb_log_error("Failed to setup %s endpoint list: %s.\n", \
508 name, str_error(ret)); \
509 endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]);\
510 endpoint_list_fini(&instance->lists[USB_TRANSFER_INTERRUPT]); \
511 endpoint_list_fini(&instance->lists[USB_TRANSFER_CONTROL]); \
512 endpoint_list_fini(&instance->lists[USB_TRANSFER_BULK]); \
513 return ret; \
514 } \
515} while (0)
516
517 SETUP_ENDPOINT_LIST(USB_TRANSFER_ISOCHRONOUS);
518 SETUP_ENDPOINT_LIST(USB_TRANSFER_INTERRUPT);
519 SETUP_ENDPOINT_LIST(USB_TRANSFER_CONTROL);
520 SETUP_ENDPOINT_LIST(USB_TRANSFER_BULK);
521#undef SETUP_ENDPOINT_LIST
522 endpoint_list_set_next(&instance->lists[USB_TRANSFER_INTERRUPT],
523 &instance->lists[USB_TRANSFER_ISOCHRONOUS]);
524
525 return EOK;
526}
527
528/** Initialize memory structures used by the OHCI hcd.
529 *
530 * @param[in] instance OHCI hc driver structure.
531 * @return Error code.
532 */
533int hc_init_memory(hc_t *instance)
534{
535 assert(instance);
536
537 bzero(&instance->rh, sizeof(instance->rh));
538 /* Init queues */
539 const int ret = hc_init_transfer_lists(instance);
540 if (ret != EOK) {
541 return ret;
542 }
543
544 /*Init HCCA */
545 instance->hcca = hcca_get();
546 if (instance->hcca == NULL)
547 return ENOMEM;
548 usb_log_debug2("OHCI HCCA initialized at %p.\n", instance->hcca);
549
550 for (unsigned i = 0; i < HCCA_INT_EP_COUNT; ++i) {
551 hcca_set_int_ep(instance->hcca, i,
552 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
553 }
554 usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").\n",
555 instance->lists[USB_TRANSFER_INTERRUPT].list_head,
556 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
557
558 return EOK;
559}
560
561/**
562 * @}
563 */
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