source: mainline/uspace/drv/bus/usb/ohci/hc.c

Last change on this file was 9dfb034, checked in by Jiri Svoboda <jiri@…>, 5 months ago

Implement quiesce for EHCI and OHCI.
  • Property mode set to 100644
File size: 18.2 KB
Line 
1/*
2 * Copyright (c) 2025 Jiri Svoboda
3 * Copyright (c) 2011 Jan Vesely
4 * Copyright (c) 2018 Ondrej Hlavaty
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * - Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * - Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * - The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31/** @addtogroup drvusbohci
32 * @{
33 */
34/** @file
35 * @brief OHCI Host controller driver routines
36 */
37
38#include <assert.h>
39#include <async.h>
40#include <errno.h>
41#include <macros.h>
42#include <mem.h>
43#include <stdlib.h>
44#include <str_error.h>
45#include <stddef.h>
46#include <stdint.h>
47
48#include <usb/debug.h>
49#include <usb/host/utility.h>
50#include <usb/usb.h>
51
52#include "ohci_bus.h"
53#include "ohci_batch.h"
54
55#include "hc.h"
56
57#define OHCI_USED_INTERRUPTS \
58 (I_SO | I_WDH | I_UE | I_RHSC)
59
60static const irq_pio_range_t ohci_pio_ranges[] = {
61 {
62 .base = 0,
63 .size = sizeof(ohci_regs_t)
64 }
65};
66
67static const irq_cmd_t ohci_irq_commands[] = {
68 {
69 .cmd = CMD_PIO_READ_32,
70 .dstarg = 1,
71 .addr = NULL
72 },
73 {
74 .cmd = CMD_AND,
75 .srcarg = 1,
76 .dstarg = 2,
77 .value = 0
78 },
79 {
80 .cmd = CMD_PREDICATE,
81 .srcarg = 2,
82 .value = 2
83 },
84 {
85 .cmd = CMD_PIO_WRITE_A_32,
86 .srcarg = 1,
87 .addr = NULL
88 },
89 {
90 .cmd = CMD_ACCEPT
91 }
92};
93
94static errno_t hc_init_transfer_lists(hc_t *instance);
95static errno_t hc_init_memory(hc_t *instance);
96
97/** Generate IRQ code.
98 * @param[out] ranges PIO ranges buffer.
99 * @param[in] ranges_size Size of the ranges buffer (bytes).
100 * @param[out] cmds Commands buffer.
101 * @param[in] cmds_size Size of the commands buffer (bytes).
102 * @param[in] hw_res Device's resources.
103 *
104 * @return Error code.
105 */
106errno_t hc_gen_irq_code(irq_code_t *code, hc_device_t *hcd, const hw_res_list_parsed_t *hw_res, int *irq)
107{
108 assert(code);
109 assert(hw_res);
110
111 if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
112 return EINVAL;
113
114 const addr_range_t regs = hw_res->mem_ranges.ranges[0];
115
116 if (RNGSZ(regs) < sizeof(ohci_regs_t))
117 return EOVERFLOW;
118
119 code->ranges = malloc(sizeof(ohci_pio_ranges));
120 if (code->ranges == NULL)
121 return ENOMEM;
122
123 code->cmds = malloc(sizeof(ohci_irq_commands));
124 if (code->cmds == NULL) {
125 free(code->ranges);
126 return ENOMEM;
127 }
128
129 code->rangecount = ARRAY_SIZE(ohci_pio_ranges);
130 code->cmdcount = ARRAY_SIZE(ohci_irq_commands);
131
132 memcpy(code->ranges, ohci_pio_ranges, sizeof(ohci_pio_ranges));
133 code->ranges[0].base = RNGABS(regs);
134
135 memcpy(code->cmds, ohci_irq_commands, sizeof(ohci_irq_commands));
136 ohci_regs_t *registers = (ohci_regs_t *) RNGABSPTR(regs);
137 code->cmds[0].addr = (void *) &registers->interrupt_status;
138 code->cmds[3].addr = (void *) &registers->interrupt_status;
139 OHCI_WR(code->cmds[1].value, OHCI_USED_INTERRUPTS);
140
141 usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.",
142 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
143
144 *irq = hw_res->irqs.irqs[0];
145 return EOK;
146}
147
148/** Initialize OHCI hc driver structure
149 *
150 * @param[in] instance Memory place for the structure.
151 * @param[in] regs Device's resources
152 * @param[in] interrupts True if w interrupts should be used
153 * @return Error code
154 */
155errno_t hc_add(hc_device_t *hcd, const hw_res_list_parsed_t *hw_res)
156{
157 hc_t *instance = hcd_to_hc(hcd);
158 assert(hw_res);
159 if (hw_res->mem_ranges.count != 1 ||
160 hw_res->mem_ranges.ranges[0].size < sizeof(ohci_regs_t))
161 return EINVAL;
162
163 errno_t ret = pio_enable_range(&hw_res->mem_ranges.ranges[0],
164 (void **) &instance->registers);
165 if (ret != EOK) {
166 usb_log_error("Failed to gain access to registers: %s.",
167 str_error(ret));
168 return ret;
169 }
170 usb_log_debug("Device registers at %" PRIx64 " (%zuB) accessible.",
171 hw_res->mem_ranges.ranges[0].address.absolute,
172 hw_res->mem_ranges.ranges[0].size);
173
174 list_initialize(&instance->pending_endpoints);
175 fibril_mutex_initialize(&instance->guard);
176
177 ret = hc_init_memory(instance);
178 if (ret != EOK) {
179 usb_log_error("Failed to create OHCI memory structures: %s.",
180 str_error(ret));
181 // TODO: We should disable pio access here
182 return ret;
183 }
184
185 return EOK;
186}
187
188/** Safely dispose host controller internal structures
189 *
190 * @param[in] instance Host controller structure to use.
191 */
192int hc_gone(hc_device_t *instance)
193{
194 assert(instance);
195 /* TODO: implement */
196 return ENOTSUP;
197}
198
199/** Quiesce host controller
200 *
201 * @param hcd Host controller device
202 */
203int hc_quiesce(hc_device_t *hcd)
204{
205 hc_t *instance = hcd_to_hc(hcd);
206
207 /* OHCI guide page 42 */
208 usb_log_debug2("Started hc initialization routine.");
209
210 /* Reset hc */
211 usb_log_debug2("HC reset.");
212 size_t time = 0;
213 OHCI_WR(instance->registers->command_status, CS_HCR);
214 while (OHCI_RD(instance->registers->command_status) & CS_HCR) {
215 fibril_usleep(10);
216 time += 10;
217 }
218 usb_log_debug2("HC reset complete in %zu us.", time);
219
220 return EOK;
221}
222
223void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
224{
225 assert(instance);
226 assert(ep);
227
228 endpoint_list_t *list = &instance->lists[ep->transfer_type];
229 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
230 assert(list);
231 assert(ohci_ep);
232
233 /* Enqueue ep */
234 switch (ep->transfer_type) {
235 case USB_TRANSFER_CONTROL:
236 OHCI_CLR(instance->registers->control, C_CLE);
237 endpoint_list_add_ep(list, ohci_ep);
238 OHCI_WR(instance->registers->control_current, 0);
239 OHCI_SET(instance->registers->control, C_CLE);
240 break;
241 case USB_TRANSFER_BULK:
242 OHCI_CLR(instance->registers->control, C_BLE);
243 endpoint_list_add_ep(list, ohci_ep);
244 OHCI_WR(instance->registers->bulk_current, 0);
245 OHCI_SET(instance->registers->control, C_BLE);
246 break;
247 case USB_TRANSFER_ISOCHRONOUS:
248 case USB_TRANSFER_INTERRUPT:
249 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
250 endpoint_list_add_ep(list, ohci_ep);
251 OHCI_SET(instance->registers->control, C_PLE | C_IE);
252 break;
253 }
254}
255
256void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
257{
258 assert(instance);
259 assert(ep);
260
261 /* Dequeue ep */
262 endpoint_list_t *list = &instance->lists[ep->transfer_type];
263 ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
264
265 assert(list);
266 assert(ohci_ep);
267 switch (ep->transfer_type) {
268 case USB_TRANSFER_CONTROL:
269 OHCI_CLR(instance->registers->control, C_CLE);
270 endpoint_list_remove_ep(list, ohci_ep);
271 OHCI_WR(instance->registers->control_current, 0);
272 OHCI_SET(instance->registers->control, C_CLE);
273 break;
274 case USB_TRANSFER_BULK:
275 OHCI_CLR(instance->registers->control, C_BLE);
276 endpoint_list_remove_ep(list, ohci_ep);
277 OHCI_WR(instance->registers->bulk_current, 0);
278 OHCI_SET(instance->registers->control, C_BLE);
279 break;
280 case USB_TRANSFER_ISOCHRONOUS:
281 case USB_TRANSFER_INTERRUPT:
282 OHCI_CLR(instance->registers->control, C_PLE | C_IE);
283 endpoint_list_remove_ep(list, ohci_ep);
284 OHCI_SET(instance->registers->control, C_PLE | C_IE);
285 break;
286 default:
287 break;
288 }
289}
290
291errno_t ohci_hc_status(bus_t *bus_base, uint32_t *status)
292{
293 assert(bus_base);
294 assert(status);
295
296 ohci_bus_t *bus = (ohci_bus_t *) bus_base;
297 hc_t *hc = bus->hc;
298 assert(hc);
299
300 if (hc->registers) {
301 *status = OHCI_RD(hc->registers->interrupt_status);
302 OHCI_WR(hc->registers->interrupt_status, *status);
303 }
304 return EOK;
305}
306
307/** Add USB transfer to the schedule.
308 *
309 * @param[in] hcd HCD driver structure.
310 * @param[in] batch Batch representing the transfer.
311 * @return Error code.
312 */
313errno_t ohci_hc_schedule(usb_transfer_batch_t *batch)
314{
315 assert(batch);
316
317 ohci_bus_t *bus = (ohci_bus_t *) endpoint_get_bus(batch->ep);
318 hc_t *hc = bus->hc;
319 assert(hc);
320
321 /* Check for root hub communication */
322 if (batch->target.address == ohci_rh_get_address(&hc->rh)) {
323 usb_log_debug("OHCI root hub request.");
324 return ohci_rh_schedule(&hc->rh, batch);
325 }
326
327 endpoint_t *ep = batch->ep;
328 ohci_endpoint_t *const ohci_ep = ohci_endpoint_get(ep);
329 ohci_transfer_batch_t *ohci_batch = ohci_transfer_batch_get(batch);
330 int err;
331
332 if ((err = ohci_transfer_batch_prepare(ohci_batch)))
333 return err;
334
335 fibril_mutex_lock(&hc->guard);
336 if ((err = endpoint_activate_locked(ep, batch))) {
337 fibril_mutex_unlock(&hc->guard);
338 return err;
339 }
340
341 ohci_transfer_batch_commit(ohci_batch);
342 list_append(&ohci_ep->pending_link, &hc->pending_endpoints);
343 fibril_mutex_unlock(&hc->guard);
344
345 /* Control and bulk schedules need a kick to start working */
346 switch (batch->ep->transfer_type) {
347 case USB_TRANSFER_CONTROL:
348 OHCI_SET(hc->registers->command_status, CS_CLF);
349 break;
350 case USB_TRANSFER_BULK:
351 OHCI_SET(hc->registers->command_status, CS_BLF);
352 break;
353 default:
354 break;
355 }
356
357 return EOK;
358}
359
360/** Interrupt handling routine
361 *
362 * @param[in] hcd HCD driver structure.
363 * @param[in] status Value of the status register at the time of interrupt.
364 */
365void ohci_hc_interrupt(bus_t *bus_base, uint32_t status)
366{
367 assert(bus_base);
368
369 ohci_bus_t *bus = (ohci_bus_t *) bus_base;
370 hc_t *hc = bus->hc;
371 assert(hc);
372
373 status = OHCI_RD(status);
374 assert(hc);
375 if ((status & ~I_SF) == 0) /* ignore sof status */
376 return;
377 usb_log_debug2("OHCI(%p) interrupt: %x.", hc, status);
378 if (status & I_RHSC)
379 ohci_rh_interrupt(&hc->rh);
380
381 if (status & I_WDH) {
382 fibril_mutex_lock(&hc->guard);
383 usb_log_debug2("HCCA: %p-%#" PRIx32 " (%p).", hc->hcca,
384 OHCI_RD(hc->registers->hcca),
385 (void *) addr_to_phys(hc->hcca));
386 usb_log_debug2("Periodic current: %#" PRIx32 ".",
387 OHCI_RD(hc->registers->periodic_current));
388
389 list_foreach_safe(hc->pending_endpoints, current, next) {
390 ohci_endpoint_t *ep =
391 list_get_instance(current, ohci_endpoint_t, pending_link);
392
393 ohci_transfer_batch_t *batch =
394 ohci_transfer_batch_get(ep->base.active_batch);
395 assert(batch);
396
397 if (ohci_transfer_batch_check_completed(batch)) {
398 endpoint_deactivate_locked(&ep->base);
399 list_remove(current);
400 hc_reset_toggles(&batch->base, &ohci_ep_toggle_reset);
401 usb_transfer_batch_finish(&batch->base);
402 }
403 }
404 fibril_mutex_unlock(&hc->guard);
405 }
406
407 if (status & I_UE) {
408 usb_log_fatal("Error like no other!");
409 hc_start(&hc->base);
410 }
411
412}
413
414/** Turn off any (BIOS)driver that might be in control of the device.
415 *
416 * This function implements routines described in chapter 5.1.1.3 of the OHCI
417 * specification (page 40, pdf page 54).
418 *
419 * @param[in] instance OHCI hc driver structure.
420 */
421int hc_gain_control(hc_device_t *hcd)
422{
423 hc_t *instance = hcd_to_hc(hcd);
424
425 usb_log_debug("Requesting OHCI control.");
426 if (OHCI_RD(instance->registers->revision) & R_LEGACY_FLAG) {
427 /*
428 * Turn off legacy emulation, it should be enough to zero
429 * the lowest bit, but it caused problems. Thus clear all
430 * except GateA20 (causes restart on some hw).
431 * See page 145 of the specs for details.
432 */
433 volatile uint32_t *ohci_emulation_reg =
434 (uint32_t *)((char *)instance->registers + LEGACY_REGS_OFFSET);
435 usb_log_debug("OHCI legacy register %p: %x.",
436 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
437 /* Zero everything but A20State */
438 // TODO: should we ack interrupts before doing this?
439 OHCI_CLR(*ohci_emulation_reg, ~0x100);
440 usb_log_debug(
441 "OHCI legacy register (should be 0 or 0x100) %p: %x.",
442 ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
443 }
444
445 /* Interrupt routing enabled => smm driver is active */
446 if (OHCI_RD(instance->registers->control) & C_IR) {
447 usb_log_debug("SMM driver: request ownership change.");
448 // TODO: should we ack interrupts before doing this?
449 OHCI_SET(instance->registers->command_status, CS_OCR);
450 /* Hope that SMM actually knows its stuff or we can hang here */
451 while (OHCI_RD(instance->registers->control) & C_IR) {
452 fibril_usleep(1000);
453 }
454 usb_log_info("SMM driver: Ownership taken.");
455 C_HCFS_SET(instance->registers->control, C_HCFS_RESET);
456 fibril_usleep(50000);
457 return EOK;
458 }
459
460 const unsigned hc_status = C_HCFS_GET(instance->registers->control);
461 /* Interrupt routing disabled && status != USB_RESET => BIOS active */
462 if (hc_status != C_HCFS_RESET) {
463 usb_log_debug("BIOS driver found.");
464 if (hc_status == C_HCFS_OPERATIONAL) {
465 usb_log_info("BIOS driver: HC operational.");
466 return EOK;
467 }
468 /* HC is suspended assert resume for 20ms */
469 C_HCFS_SET(instance->registers->control, C_HCFS_RESUME);
470 fibril_usleep(20000);
471 usb_log_info("BIOS driver: HC resumed.");
472 return EOK;
473 }
474
475 /*
476 * HC is in reset (hw startup) => no other driver
477 * maintain reset for at least the time specified in USB spec (50 ms)
478 */
479 usb_log_debug("Host controller found in reset state.");
480 fibril_usleep(50000);
481 return EOK;
482}
483
484/** OHCI hw initialization routine.
485 *
486 * @param[in] instance OHCI hc driver structure.
487 */
488int hc_start(hc_device_t *hcd)
489{
490 hc_t *instance = hcd_to_hc(hcd);
491 ohci_rh_init(&instance->rh, instance->registers, &instance->guard, "ohci rh");
492
493 /* OHCI guide page 42 */
494 assert(instance);
495 usb_log_debug2("Started hc initialization routine.");
496
497 /* Save contents of fm_interval register */
498 const uint32_t fm_interval = OHCI_RD(instance->registers->fm_interval);
499 usb_log_debug2("Old value of HcFmInterval: %x.", fm_interval);
500
501 /* Reset hc */
502 usb_log_debug2("HC reset.");
503 size_t time = 0;
504 OHCI_WR(instance->registers->command_status, CS_HCR);
505 while (OHCI_RD(instance->registers->command_status) & CS_HCR) {
506 fibril_usleep(10);
507 time += 10;
508 }
509 usb_log_debug2("HC reset complete in %zu us.", time);
510
511 /* Restore fm_interval */
512 OHCI_WR(instance->registers->fm_interval, fm_interval);
513 assert((OHCI_RD(instance->registers->command_status) & CS_HCR) == 0);
514
515 /* hc is now in suspend state */
516 usb_log_debug2("HC should be in suspend state(%x).",
517 OHCI_RD(instance->registers->control));
518
519 /* Use HCCA */
520 OHCI_WR(instance->registers->hcca, addr_to_phys(instance->hcca));
521
522 /* Use queues */
523 OHCI_WR(instance->registers->bulk_head,
524 instance->lists[USB_TRANSFER_BULK].list_head_pa);
525 usb_log_debug2("Bulk HEAD set to: %p (%#" PRIx32 ").",
526 instance->lists[USB_TRANSFER_BULK].list_head,
527 instance->lists[USB_TRANSFER_BULK].list_head_pa);
528
529 OHCI_WR(instance->registers->control_head,
530 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
531 usb_log_debug2("Control HEAD set to: %p (%#" PRIx32 ").",
532 instance->lists[USB_TRANSFER_CONTROL].list_head,
533 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
534
535 /* Enable queues */
536 OHCI_SET(instance->registers->control, (C_PLE | C_IE | C_CLE | C_BLE));
537 usb_log_debug("Queues enabled(%x).",
538 OHCI_RD(instance->registers->control));
539
540 /* Enable interrupts */
541 if (cap_handle_valid(instance->base.irq_handle)) {
542 OHCI_WR(instance->registers->interrupt_enable,
543 OHCI_USED_INTERRUPTS);
544 usb_log_debug("Enabled interrupts: %x.",
545 OHCI_RD(instance->registers->interrupt_enable));
546 OHCI_WR(instance->registers->interrupt_enable, I_MI);
547 }
548
549 /* Set periodic start to 90% */
550 const uint32_t frame_length =
551 (fm_interval >> FMI_FI_SHIFT) & FMI_FI_MASK;
552 OHCI_WR(instance->registers->periodic_start,
553 ((frame_length / 10) * 9) & PS_MASK << PS_SHIFT);
554 usb_log_debug2("All periodic start set to: %x(%u - 90%% of %d).",
555 OHCI_RD(instance->registers->periodic_start),
556 OHCI_RD(instance->registers->periodic_start), frame_length);
557 C_HCFS_SET(instance->registers->control, C_HCFS_OPERATIONAL);
558 usb_log_debug("OHCI HC up and running (ctl_reg=0x%x).",
559 OHCI_RD(instance->registers->control));
560
561 return EOK;
562}
563
564/**
565 * Setup roothub as a virtual hub.
566 */
567int hc_setup_roothub(hc_device_t *hcd)
568{
569 return hc_setup_virtual_root_hub(hcd, USB_SPEED_FULL);
570}
571
572/** Initialize schedule queues
573 *
574 * @param[in] instance OHCI hc driver structure
575 * @return Error code
576 */
577errno_t hc_init_transfer_lists(hc_t *instance)
578{
579 assert(instance);
580#define SETUP_ENDPOINT_LIST(type) \
581do { \
582 const char *name = usb_str_transfer_type(type); \
583 const errno_t ret = endpoint_list_init(&instance->lists[type], name); \
584 if (ret != EOK) { \
585 usb_log_error("Failed to setup %s endpoint list: %s.", \
586 name, str_error(ret)); \
587 endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]);\
588 endpoint_list_fini(&instance->lists[USB_TRANSFER_INTERRUPT]); \
589 endpoint_list_fini(&instance->lists[USB_TRANSFER_CONTROL]); \
590 endpoint_list_fini(&instance->lists[USB_TRANSFER_BULK]); \
591 return ret; \
592 } \
593} while (0)
594
595 SETUP_ENDPOINT_LIST(USB_TRANSFER_ISOCHRONOUS);
596 SETUP_ENDPOINT_LIST(USB_TRANSFER_INTERRUPT);
597 SETUP_ENDPOINT_LIST(USB_TRANSFER_CONTROL);
598 SETUP_ENDPOINT_LIST(USB_TRANSFER_BULK);
599#undef SETUP_ENDPOINT_LIST
600 endpoint_list_set_next(&instance->lists[USB_TRANSFER_INTERRUPT],
601 &instance->lists[USB_TRANSFER_ISOCHRONOUS]);
602
603 return EOK;
604}
605
606/** Initialize memory structures used by the OHCI hcd.
607 *
608 * @param[in] instance OHCI hc driver structure.
609 * @return Error code.
610 */
611errno_t hc_init_memory(hc_t *instance)
612{
613 assert(instance);
614
615 memset(&instance->rh, 0, sizeof(instance->rh));
616 /* Init queues */
617 errno_t ret = hc_init_transfer_lists(instance);
618 if (ret != EOK) {
619 return ret;
620 }
621
622 /* Init HCCA */
623 instance->hcca = hcca_get();
624 if (instance->hcca == NULL)
625 return ENOMEM;
626 usb_log_debug2("OHCI HCCA initialized at %p.", instance->hcca);
627
628 for (unsigned i = 0; i < HCCA_INT_EP_COUNT; ++i) {
629 hcca_set_int_ep(instance->hcca, i,
630 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
631 }
632 usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").",
633 instance->lists[USB_TRANSFER_INTERRUPT].list_head,
634 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
635
636 if ((ret = ohci_bus_init(&instance->bus, instance))) {
637 usb_log_error("HC(%p): Failed to setup bus : %s",
638 instance, str_error(ret));
639 return ret;
640 }
641
642 hc_device_setup(&instance->base, (bus_t *) &instance->bus);
643
644 return EOK;
645}
646
647/**
648 * @}
649 */
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