[41b96b4] | 1 | /*
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| 2 | * Copyright (c) 2011 Jan Vesely
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 | /** @addtogroup drvusbohcihc
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| 29 | * @{
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| 30 | */
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| 31 | /** @file
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| 32 | * @brief OHCI Host controller driver routines
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| 33 | */
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| 34 | #include <errno.h>
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| 35 | #include <str_error.h>
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| 36 | #include <adt/list.h>
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| 37 | #include <libarch/ddi.h>
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| 38 |
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| 39 | #include <usb/debug.h>
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| 40 | #include <usb/usb.h>
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| 41 | #include <usb/ddfiface.h>
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| 42 |
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[bab71635] | 43 | #include "hc.h"
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[2759c52] | 44 | #include "hcd_endpoint.h"
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[41b96b4] | 45 |
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[561112f] | 46 | #define OHCI_USED_INTERRUPTS \
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| 47 | (I_SO | I_WDH | I_UE | I_RHSC)
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[7d6a676] | 48 | static int interrupt_emulator(hc_t *instance);
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[2c617b0] | 49 | static void hc_gain_control(hc_t *instance);
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[6b6e3ed3] | 50 | static int hc_init_transfer_lists(hc_t *instance);
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[344925c] | 51 | static int hc_init_memory(hc_t *instance);
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[a6d1bc1] | 52 | /*----------------------------------------------------------------------------*/
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[02cacce] | 53 | /** Announce OHCI root hub to the DDF
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| 54 | *
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| 55 | * @param[in] instance OHCI driver intance
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| 56 | * @param[in] hub_fun DDF fuction representing OHCI root hub
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| 57 | * @return Error code
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| 58 | */
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[53f1c87] | 59 | int hc_register_hub(hc_t *instance, ddf_fun_t *hub_fun)
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| 60 | {
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| 61 | assert(instance);
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| 62 | assert(hub_fun);
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| 63 |
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[2ff7360] | 64 | const usb_address_t hub_address =
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[53f1c87] | 65 | device_keeper_get_free_address(&instance->manager, USB_SPEED_FULL);
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[8148ee3a] | 66 | if (hub_address <= 0) {
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[c4fb5ecd] | 67 | usb_log_error("Failed to get OHCI root hub address: %s\n",
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| 68 | str_error(hub_address));
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[8148ee3a] | 69 | return hub_address;
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| 70 | }
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[53f1c87] | 71 | instance->rh.address = hub_address;
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| 72 | usb_device_keeper_bind(
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| 73 | &instance->manager, hub_address, hub_fun->handle);
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| 74 |
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[2ff7360] | 75 | #define CHECK_RET_RELEASE(ret, message...) \
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| 76 | if (ret != EOK) { \
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| 77 | usb_log_error(message); \
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| 78 | hc_remove_endpoint(instance, hub_address, 0, USB_DIRECTION_BOTH); \
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| 79 | usb_device_keeper_release(&instance->manager, hub_address); \
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| 80 | return ret; \
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| 81 | } else (void)0
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| 82 |
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| 83 | int ret = hc_add_endpoint(instance, hub_address, 0, USB_SPEED_FULL,
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[9a6fde4] | 84 | USB_TRANSFER_CONTROL, USB_DIRECTION_BOTH, 64, 0, 0);
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[2ff7360] | 85 | CHECK_RET_RELEASE(ret, "Failed(%d) to add OHCI rh endpoint 0.\n", ret);
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[6bec59b] | 86 |
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[53f1c87] | 87 | char *match_str = NULL;
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[8148ee3a] | 88 | /* DDF needs heap allocated string */
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[6bec59b] | 89 | ret = asprintf(&match_str, "usb&class=hub");
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[2ff7360] | 90 | ret = ret > 0 ? 0 : ret;
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| 91 | CHECK_RET_RELEASE(ret, "Failed(%d) to create match-id string.\n", ret);
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[53f1c87] | 92 |
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| 93 | ret = ddf_fun_add_match_id(hub_fun, match_str, 100);
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[2ff7360] | 94 | CHECK_RET_RELEASE(ret, "Failed(%d) add root hub match-id.\n", ret);
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| 95 |
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[5d07f54] | 96 | ret = ddf_fun_bind(hub_fun);
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[2ff7360] | 97 | CHECK_RET_RELEASE(ret, "Failed(%d) to bind root hub function.\n", ret);
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| 98 |
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| 99 | return EOK;
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| 100 | #undef CHECK_RET_RELEASE
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[53f1c87] | 101 | }
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| 102 | /*----------------------------------------------------------------------------*/
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[02cacce] | 103 | /** Initialize OHCI hc driver structure
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| 104 | *
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| 105 | * @param[in] instance Memory place for the structure.
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| 106 | * @param[in] regs Address of the memory mapped I/O registers.
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| 107 | * @param[in] reg_size Size of the memory mapped area.
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| 108 | * @param[in] interrupts True if w interrupts should be used
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| 109 | * @return Error code
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| 110 | */
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[62265ce] | 111 | int hc_init(hc_t *instance, uintptr_t regs, size_t reg_size, bool interrupts)
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[41b96b4] | 112 | {
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| 113 | assert(instance);
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[ff582d47] | 114 | int ret = EOK;
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[c2be0e5] | 115 | #define CHECK_RET_RETURN(ret, message...) \
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| 116 | if (ret != EOK) { \
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| 117 | usb_log_error(message); \
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| 118 | return ret; \
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| 119 | } else (void)0
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[ff582d47] | 120 |
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| 121 | ret = pio_enable((void*)regs, reg_size, (void**)&instance->registers);
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[c2be0e5] | 122 | CHECK_RET_RETURN(ret,
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| 123 | "Failed(%d) to gain access to device registers: %s.\n",
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| 124 | ret, str_error(ret));
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| 125 |
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[bba0dc20] | 126 | list_initialize(&instance->pending_batches);
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[68b5ed6e] | 127 | usb_device_keeper_init(&instance->manager);
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[5876d36] | 128 | ret = usb_endpoint_manager_init(&instance->ep_manager,
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| 129 | BANDWIDTH_AVAILABLE_USB11);
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| 130 | CHECK_RET_RETURN(ret, "Failed to initialize endpoint manager: %s.\n",
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[4125b7d] | 131 | str_error(ret));
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[e7bc999] | 132 |
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[8790650] | 133 | ret = hc_init_memory(instance);
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[4125b7d] | 134 | CHECK_RET_RETURN(ret, "Failed to create OHCI memory structures: %s.\n",
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| 135 | str_error(ret));
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[bba0dc20] | 136 | #undef CHECK_RET_RETURN
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| 137 |
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[aa9ccf7] | 138 | fibril_mutex_initialize(&instance->guard);
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[2ff7360] | 139 | hc_gain_control(instance);
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[2c617b0] | 140 |
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[8148ee3a] | 141 | rh_init(&instance->rh, instance->registers);
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[ff582d47] | 142 |
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[ff0e354] | 143 | if (!interrupts) {
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| 144 | instance->interrupt_emulator =
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| 145 | fibril_create((int(*)(void*))interrupt_emulator, instance);
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| 146 | fibril_add_ready(instance->interrupt_emulator);
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| 147 | }
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[7013b14] | 148 |
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[8627377] | 149 | return EOK;
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[a6d1bc1] | 150 | }
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| 151 | /*----------------------------------------------------------------------------*/
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[02cacce] | 152 | /** Create end register endpoint structures
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| 153 | *
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| 154 | * @param[in] instance OHCI driver structure.
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| 155 | * @param[in] address USB address of the device.
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| 156 | * @param[in] endpoint USB endpoint number.
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| 157 | * @param[in] speed Communication speeed of the device.
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| 158 | * @param[in] type Endpoint's transfer type.
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| 159 | * @param[in] direction Endpoint's direction.
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| 160 | * @param[in] mps Maximum packet size the endpoint accepts.
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| 161 | * @param[in] size Maximum allowed buffer size.
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| 162 | * @param[in] interval Time between transfers(interrupt transfers only).
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| 163 | * @return Error code
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| 164 | */
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[6bb0f43] | 165 | int hc_add_endpoint(
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| 166 | hc_t *instance, usb_address_t address, usb_endpoint_t endpoint,
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| 167 | usb_speed_t speed, usb_transfer_type_t type, usb_direction_t direction,
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| 168 | size_t mps, size_t size, unsigned interval)
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| 169 | {
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| 170 | endpoint_t *ep = malloc(sizeof(endpoint_t));
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| 171 | if (ep == NULL)
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| 172 | return ENOMEM;
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| 173 | int ret =
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| 174 | endpoint_init(ep, address, endpoint, direction, type, speed, mps);
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| 175 | if (ret != EOK) {
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| 176 | free(ep);
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| 177 | return ret;
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| 178 | }
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| 179 |
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[2759c52] | 180 | hcd_endpoint_t *hcd_ep = hcd_endpoint_assign(ep);
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| 181 | if (hcd_ep == NULL) {
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[592369ae] | 182 | endpoint_destroy(ep);
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[2759c52] | 183 | return ENOMEM;
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| 184 | }
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| 185 |
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[6bb0f43] | 186 | ret = usb_endpoint_manager_register_ep(&instance->ep_manager, ep, size);
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| 187 | if (ret != EOK) {
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[592369ae] | 188 | hcd_endpoint_clear(ep);
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[6bb0f43] | 189 | endpoint_destroy(ep);
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[5a2c42b] | 190 | return ret;
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| 191 | }
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| 192 |
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| 193 | /* Enqueue hcd_ep */
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| 194 | switch (ep->transfer_type) {
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| 195 | case USB_TRANSFER_CONTROL:
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| 196 | instance->registers->control &= ~C_CLE;
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| 197 | endpoint_list_add_ep(
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| 198 | &instance->lists[ep->transfer_type], hcd_ep);
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| 199 | instance->registers->control_current = 0;
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| 200 | instance->registers->control |= C_CLE;
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| 201 | break;
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| 202 | case USB_TRANSFER_BULK:
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| 203 | instance->registers->control &= ~C_BLE;
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| 204 | endpoint_list_add_ep(
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| 205 | &instance->lists[ep->transfer_type], hcd_ep);
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| 206 | instance->registers->control |= C_BLE;
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| 207 | break;
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| 208 | case USB_TRANSFER_ISOCHRONOUS:
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| 209 | case USB_TRANSFER_INTERRUPT:
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| 210 | instance->registers->control &= (~C_PLE & ~C_IE);
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| 211 | endpoint_list_add_ep(
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| 212 | &instance->lists[ep->transfer_type], hcd_ep);
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| 213 | instance->registers->control |= C_PLE | C_IE;
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| 214 | break;
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| 215 | default:
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| 216 | break;
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[6bb0f43] | 217 | }
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[5a2c42b] | 218 |
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[592369ae] | 219 | return EOK;
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[6bb0f43] | 220 | }
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| 221 | /*----------------------------------------------------------------------------*/
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[02cacce] | 222 | /** Dequeue and delete endpoint structures
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| 223 | *
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| 224 | * @param[in] instance OHCI hc driver structure.
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| 225 | * @param[in] address USB address of the device.
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| 226 | * @param[in] endpoint USB endpoint number.
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| 227 | * @param[in] direction Direction of the endpoint.
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| 228 | * @return Error code
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| 229 | */
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[6bb0f43] | 230 | int hc_remove_endpoint(hc_t *instance, usb_address_t address,
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| 231 | usb_endpoint_t endpoint, usb_direction_t direction)
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| 232 | {
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[592369ae] | 233 | assert(instance);
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| 234 | fibril_mutex_lock(&instance->guard);
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[2759c52] | 235 | endpoint_t *ep = usb_endpoint_manager_get_ep(&instance->ep_manager,
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| 236 | address, endpoint, direction, NULL);
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| 237 | if (ep == NULL) {
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[592369ae] | 238 | usb_log_error("Endpoint unregister failed: No such EP.\n");
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| 239 | fibril_mutex_unlock(&instance->guard);
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[2759c52] | 240 | return ENOENT;
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| 241 | }
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| 242 |
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| 243 | hcd_endpoint_t *hcd_ep = hcd_endpoint_get(ep);
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| 244 | if (hcd_ep) {
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[5a2c42b] | 245 | /* Dequeue hcd_ep */
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| 246 | switch (ep->transfer_type) {
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| 247 | case USB_TRANSFER_CONTROL:
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| 248 | instance->registers->control &= ~C_CLE;
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| 249 | endpoint_list_remove_ep(
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| 250 | &instance->lists[ep->transfer_type], hcd_ep);
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| 251 | instance->registers->control_current = 0;
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| 252 | instance->registers->control |= C_CLE;
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| 253 | break;
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| 254 | case USB_TRANSFER_BULK:
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| 255 | instance->registers->control &= ~C_BLE;
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| 256 | endpoint_list_remove_ep(
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| 257 | &instance->lists[ep->transfer_type], hcd_ep);
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| 258 | instance->registers->control |= C_BLE;
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| 259 | break;
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| 260 | case USB_TRANSFER_ISOCHRONOUS:
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| 261 | case USB_TRANSFER_INTERRUPT:
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| 262 | instance->registers->control &= (~C_PLE & ~C_IE);
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| 263 | endpoint_list_remove_ep(
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| 264 | &instance->lists[ep->transfer_type], hcd_ep);
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| 265 | instance->registers->control |= C_PLE | C_IE;
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| 266 | break;
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| 267 | default:
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| 268 | break;
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| 269 | }
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[2759c52] | 270 | hcd_endpoint_clear(ep);
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| 271 | } else {
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| 272 | usb_log_warning("Endpoint without hcd equivalent structure.\n");
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| 273 | }
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[592369ae] | 274 | int ret = usb_endpoint_manager_unregister_ep(&instance->ep_manager,
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[6bb0f43] | 275 | address, endpoint, direction);
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[592369ae] | 276 | fibril_mutex_unlock(&instance->guard);
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| 277 | return ret;
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| 278 | }
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| 279 | /*----------------------------------------------------------------------------*/
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[02cacce] | 280 | /** Get access to endpoint structures
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| 281 | *
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| 282 | * @param[in] instance OHCI hc driver structure.
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| 283 | * @param[in] address USB address of the device.
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| 284 | * @param[in] endpoint USB endpoint number.
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| 285 | * @param[in] direction Direction of the endpoint.
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| 286 | * @param[out] bw Reserved bandwidth.
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| 287 | * @return Error code
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| 288 | */
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[592369ae] | 289 | endpoint_t * hc_get_endpoint(hc_t *instance, usb_address_t address,
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| 290 | usb_endpoint_t endpoint, usb_direction_t direction, size_t *bw)
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| 291 | {
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| 292 | assert(instance);
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| 293 | fibril_mutex_lock(&instance->guard);
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| 294 | endpoint_t *ep = usb_endpoint_manager_get_ep(&instance->ep_manager,
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| 295 | address, endpoint, direction, bw);
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| 296 | fibril_mutex_unlock(&instance->guard);
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| 297 | return ep;
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[6bb0f43] | 298 | }
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| 299 | /*----------------------------------------------------------------------------*/
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[02cacce] | 300 | /** Add USB transfer to the schedule.
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| 301 | *
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| 302 | * @param[in] instance OHCI hc driver structure.
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| 303 | * @param[in] batch Batch representing the transfer.
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| 304 | * @return Error code.
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| 305 | */
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[1387692] | 306 | int hc_schedule(hc_t *instance, usb_transfer_batch_t *batch)
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[41b96b4] | 307 | {
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| 308 | assert(instance);
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| 309 | assert(batch);
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[d017cea] | 310 | assert(batch->ep);
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[9ff5ff82] | 311 |
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[02cacce] | 312 | /* Check for root hub communication */
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[d017cea] | 313 | if (batch->ep->address == instance->rh.address) {
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[2bf8f8c] | 314 | return rh_request(&instance->rh, batch);
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[41b96b4] | 315 | }
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[7013b14] | 316 |
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[aa9ccf7] | 317 | fibril_mutex_lock(&instance->guard);
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[7013b14] | 318 | list_append(&batch->link, &instance->pending_batches);
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| 319 | batch_commit(batch);
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[02cacce] | 320 |
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| 321 | /* Control and bulk schedules need a kick to start working */
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| 322 | switch (batch->ep->transfer_type)
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| 323 | {
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[9ff5ff82] | 324 | case USB_TRANSFER_CONTROL:
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| 325 | instance->registers->command_status |= CS_CLF;
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| 326 | break;
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| 327 | case USB_TRANSFER_BULK:
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| 328 | instance->registers->command_status |= CS_BLF;
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| 329 | break;
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| 330 | default:
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| 331 | break;
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| 332 | }
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[aa9ccf7] | 333 | fibril_mutex_unlock(&instance->guard);
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[4c28d17] | 334 | return EOK;
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[41b96b4] | 335 | }
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| 336 | /*----------------------------------------------------------------------------*/
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[02cacce] | 337 | /** Interrupt handling routine
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| 338 | *
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| 339 | * @param[in] instance OHCI hc driver structure.
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| 340 | * @param[in] status Value of the status register at the time of interrupt.
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| 341 | */
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[7d6a676] | 342 | void hc_interrupt(hc_t *instance, uint32_t status)
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[41b96b4] | 343 | {
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| 344 | assert(instance);
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[561112f] | 345 | if ((status & ~I_SF) == 0) /* ignore sof status */
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[eaf1e3d] | 346 | return;
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[2df648c2] | 347 | usb_log_debug2("OHCI(%p) interrupt: %x.\n", instance, status);
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[561112f] | 348 | if (status & I_RHSC)
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[7d6a676] | 349 | rh_interrupt(&instance->rh);
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| 350 |
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[561112f] | 351 | if (status & I_WDH) {
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[aa9ccf7] | 352 | fibril_mutex_lock(&instance->guard);
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[4125b7d] | 353 | usb_log_debug2("HCCA: %p-%#" PRIx32 " (%p).\n", instance->hcca,
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| 354 | instance->registers->hcca,
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| 355 | (void *) addr_to_phys(instance->hcca));
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| 356 | usb_log_debug2("Periodic current: %#" PRIx32 ".\n",
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[aa9ccf7] | 357 | instance->registers->periodic_current);
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[eaf1e3d] | 358 |
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[b72efe8] | 359 | link_t *current = instance->pending_batches.head.next;
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| 360 | while (current != &instance->pending_batches.head) {
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[7013b14] | 361 | link_t *next = current->next;
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[eaf1e3d] | 362 | usb_transfer_batch_t *batch =
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[7013b14] | 363 | usb_transfer_batch_from_link(current);
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| 364 |
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| 365 | if (batch_is_complete(batch)) {
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[d6522dd] | 366 | list_remove(current);
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[7013b14] | 367 | usb_transfer_batch_finish(batch);
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| 368 | }
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[b72efe8] | 369 |
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[7013b14] | 370 | current = next;
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[eaf1e3d] | 371 | }
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[aa9ccf7] | 372 | fibril_mutex_unlock(&instance->guard);
|
---|
[4c28d17] | 373 | }
|
---|
[68b9f148] | 374 |
|
---|
| 375 | if (status & I_UE) {
|
---|
| 376 | hc_start_hw(instance);
|
---|
| 377 | }
|
---|
| 378 |
|
---|
[41b96b4] | 379 | }
|
---|
[7d6a676] | 380 | /*----------------------------------------------------------------------------*/
|
---|
[02cacce] | 381 | /** Check status register regularly
|
---|
| 382 | *
|
---|
| 383 | * @param[in] instance OHCI hc driver structure.
|
---|
| 384 | * @return Error code
|
---|
| 385 | */
|
---|
[53f1c87] | 386 | int interrupt_emulator(hc_t *instance)
|
---|
[7d6a676] | 387 | {
|
---|
| 388 | assert(instance);
|
---|
| 389 | usb_log_info("Started interrupt emulator.\n");
|
---|
| 390 | while (1) {
|
---|
[2c617b0] | 391 | const uint32_t status = instance->registers->interrupt_status;
|
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[7d6a676] | 392 | instance->registers->interrupt_status = status;
|
---|
| 393 | hc_interrupt(instance, status);
|
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[02cacce] | 394 | async_usleep(10000);
|
---|
[7d6a676] | 395 | }
|
---|
| 396 | return EOK;
|
---|
| 397 | }
|
---|
[2c617b0] | 398 | /*----------------------------------------------------------------------------*/
|
---|
[02cacce] | 399 | /** Turn off any (BIOS)driver that might be in control of the device.
|
---|
| 400 | *
|
---|
| 401 | * @param[in] instance OHCI hc driver structure.
|
---|
| 402 | */
|
---|
[2c617b0] | 403 | void hc_gain_control(hc_t *instance)
|
---|
| 404 | {
|
---|
| 405 | assert(instance);
|
---|
[c8eddf4] | 406 | usb_log_debug("Requesting OHCI control.\n");
|
---|
[112d159] | 407 | /* Turn off legacy emulation */
|
---|
| 408 | volatile uint32_t *ohci_emulation_reg =
|
---|
| 409 | (uint32_t*)((char*)instance->registers + 0x100);
|
---|
| 410 | usb_log_debug("OHCI legacy register %p: %x.\n",
|
---|
[bba0dc20] | 411 | ohci_emulation_reg, *ohci_emulation_reg);
|
---|
| 412 | /* Do not change A20 state */
|
---|
| 413 | *ohci_emulation_reg &= 0x100;
|
---|
| 414 | usb_log_debug("OHCI legacy register %p: %x.\n",
|
---|
| 415 | ohci_emulation_reg, *ohci_emulation_reg);
|
---|
[112d159] | 416 |
|
---|
[2c617b0] | 417 | /* Interrupt routing enabled => smm driver is active */
|
---|
| 418 | if (instance->registers->control & C_IR) {
|
---|
[112d159] | 419 | usb_log_debug("SMM driver: request ownership change.\n");
|
---|
[2c617b0] | 420 | instance->registers->command_status |= CS_OCR;
|
---|
| 421 | while (instance->registers->control & C_IR) {
|
---|
| 422 | async_usleep(1000);
|
---|
| 423 | }
|
---|
[112d159] | 424 | usb_log_info("SMM driver: Ownership taken.\n");
|
---|
[5d07f54] | 425 | instance->registers->control &= (C_HCFS_RESET << C_HCFS_SHIFT);
|
---|
| 426 | async_usleep(50000);
|
---|
[2c617b0] | 427 | return;
|
---|
| 428 | }
|
---|
| 429 |
|
---|
| 430 | const unsigned hc_status =
|
---|
| 431 | (instance->registers->control >> C_HCFS_SHIFT) & C_HCFS_MASK;
|
---|
| 432 | /* Interrupt routing disabled && status != USB_RESET => BIOS active */
|
---|
| 433 | if (hc_status != C_HCFS_RESET) {
|
---|
[112d159] | 434 | usb_log_debug("BIOS driver found.\n");
|
---|
[2c617b0] | 435 | if (hc_status == C_HCFS_OPERATIONAL) {
|
---|
[112d159] | 436 | usb_log_info("BIOS driver: HC operational.\n");
|
---|
[2c617b0] | 437 | return;
|
---|
| 438 | }
|
---|
| 439 | /* HC is suspended assert resume for 20ms */
|
---|
| 440 | instance->registers->control &= (C_HCFS_RESUME << C_HCFS_SHIFT);
|
---|
| 441 | async_usleep(20000);
|
---|
[112d159] | 442 | usb_log_info("BIOS driver: HC resumed.\n");
|
---|
[2c617b0] | 443 | return;
|
---|
| 444 | }
|
---|
| 445 |
|
---|
| 446 | /* HC is in reset (hw startup) => no other driver
|
---|
| 447 | * maintain reset for at least the time specified in USB spec (50 ms)*/
|
---|
[c4fb5ecd] | 448 | usb_log_debug("Host controller found in reset state.\n");
|
---|
[2c617b0] | 449 | async_usleep(50000);
|
---|
| 450 | }
|
---|
| 451 | /*----------------------------------------------------------------------------*/
|
---|
[02cacce] | 452 | /** OHCI hw initialization routine.
|
---|
| 453 | *
|
---|
| 454 | * @param[in] instance OHCI hc driver structure.
|
---|
| 455 | */
|
---|
[f1d16663] | 456 | void hc_start_hw(hc_t *instance)
|
---|
[2c617b0] | 457 | {
|
---|
[112d159] | 458 | /* OHCI guide page 42 */
|
---|
[2c617b0] | 459 | assert(instance);
|
---|
[112d159] | 460 | usb_log_debug2("Started hc initialization routine.\n");
|
---|
| 461 |
|
---|
| 462 | /* Save contents of fm_interval register */
|
---|
[2c617b0] | 463 | const uint32_t fm_interval = instance->registers->fm_interval;
|
---|
[112d159] | 464 | usb_log_debug2("Old value of HcFmInterval: %x.\n", fm_interval);
|
---|
[344925c] | 465 |
|
---|
[112d159] | 466 | /* Reset hc */
|
---|
| 467 | usb_log_debug2("HC reset.\n");
|
---|
| 468 | size_t time = 0;
|
---|
[2c617b0] | 469 | instance->registers->command_status = CS_HCR;
|
---|
[112d159] | 470 | while (instance->registers->command_status & CS_HCR) {
|
---|
| 471 | async_usleep(10);
|
---|
| 472 | time += 10;
|
---|
| 473 | }
|
---|
| 474 | usb_log_debug2("HC reset complete in %zu us.\n", time);
|
---|
[344925c] | 475 |
|
---|
[112d159] | 476 | /* Restore fm_interval */
|
---|
[2c617b0] | 477 | instance->registers->fm_interval = fm_interval;
|
---|
| 478 | assert((instance->registers->command_status & CS_HCR) == 0);
|
---|
[344925c] | 479 |
|
---|
[2c617b0] | 480 | /* hc is now in suspend state */
|
---|
[112d159] | 481 | usb_log_debug2("HC should be in suspend state(%x).\n",
|
---|
| 482 | instance->registers->control);
|
---|
[344925c] | 483 |
|
---|
[78d4e1f] | 484 | /* Use HCCA */
|
---|
| 485 | instance->registers->hcca = addr_to_phys(instance->hcca);
|
---|
| 486 |
|
---|
| 487 | /* Use queues */
|
---|
[5a2c42b] | 488 | instance->registers->bulk_head =
|
---|
| 489 | instance->lists[USB_TRANSFER_BULK].list_head_pa;
|
---|
[4125b7d] | 490 | usb_log_debug2("Bulk HEAD set to: %p (%#" PRIx32 ").\n",
|
---|
[5a2c42b] | 491 | instance->lists[USB_TRANSFER_BULK].list_head,
|
---|
| 492 | instance->lists[USB_TRANSFER_BULK].list_head_pa);
|
---|
[78d4e1f] | 493 |
|
---|
| 494 | instance->registers->control_head =
|
---|
[5a2c42b] | 495 | instance->lists[USB_TRANSFER_CONTROL].list_head_pa;
|
---|
[4125b7d] | 496 | usb_log_debug2("Control HEAD set to: %p (%#" PRIx32 ").\n",
|
---|
[5a2c42b] | 497 | instance->lists[USB_TRANSFER_CONTROL].list_head,
|
---|
| 498 | instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
|
---|
[78d4e1f] | 499 |
|
---|
[112d159] | 500 | /* Enable queues */
|
---|
[344925c] | 501 | instance->registers->control |= (C_PLE | C_IE | C_CLE | C_BLE);
|
---|
[112d159] | 502 | usb_log_debug2("All queues enabled(%x).\n",
|
---|
| 503 | instance->registers->control);
|
---|
| 504 |
|
---|
[561112f] | 505 | /* Enable interrupts */
|
---|
| 506 | instance->registers->interrupt_enable = OHCI_USED_INTERRUPTS;
|
---|
[112d159] | 507 | usb_log_debug2("Enabled interrupts: %x.\n",
|
---|
| 508 | instance->registers->interrupt_enable);
|
---|
[561112f] | 509 | instance->registers->interrupt_enable = I_MI;
|
---|
[112d159] | 510 |
|
---|
| 511 | /* Set periodic start to 90% */
|
---|
| 512 | uint32_t frame_length = ((fm_interval >> FMI_FI_SHIFT) & FMI_FI_MASK);
|
---|
| 513 | instance->registers->periodic_start = (frame_length / 10) * 9;
|
---|
| 514 | usb_log_debug2("All periodic start set to: %x(%u - 90%% of %d).\n",
|
---|
| 515 | instance->registers->periodic_start,
|
---|
| 516 | instance->registers->periodic_start, frame_length);
|
---|
[2c617b0] | 517 |
|
---|
| 518 | instance->registers->control &= (C_HCFS_OPERATIONAL << C_HCFS_SHIFT);
|
---|
[c4fb5ecd] | 519 | usb_log_debug("OHCI HC up and running (ctl_reg=0x%x).\n",
|
---|
[112d159] | 520 | instance->registers->control);
|
---|
[2c617b0] | 521 | }
|
---|
[6b6e3ed3] | 522 | /*----------------------------------------------------------------------------*/
|
---|
[02cacce] | 523 | /** Initialize schedule queues
|
---|
| 524 | *
|
---|
| 525 | * @param[in] instance OHCI hc driver structure
|
---|
| 526 | * @return Error code
|
---|
| 527 | */
|
---|
[6b6e3ed3] | 528 | int hc_init_transfer_lists(hc_t *instance)
|
---|
| 529 | {
|
---|
| 530 | assert(instance);
|
---|
[5a2c42b] | 531 | #define SETUP_ENDPOINT_LIST(type) \
|
---|
[344925c] | 532 | do { \
|
---|
[5a2c42b] | 533 | const char *name = usb_str_transfer_type(type); \
|
---|
| 534 | int ret = endpoint_list_init(&instance->lists[type], name); \
|
---|
[6b6e3ed3] | 535 | if (ret != EOK) { \
|
---|
[5a2c42b] | 536 | usb_log_error("Failed(%d) to setup %s endpoint list.\n", \
|
---|
[344925c] | 537 | ret, name); \
|
---|
[68b9f148] | 538 | endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]);\
|
---|
[5a2c42b] | 539 | endpoint_list_fini(&instance->lists[USB_TRANSFER_INTERRUPT]); \
|
---|
| 540 | endpoint_list_fini(&instance->lists[USB_TRANSFER_CONTROL]); \
|
---|
| 541 | endpoint_list_fini(&instance->lists[USB_TRANSFER_BULK]); \
|
---|
[70c85320] | 542 | return ret; \
|
---|
[344925c] | 543 | } \
|
---|
| 544 | } while (0)
|
---|
[6b6e3ed3] | 545 |
|
---|
[5a2c42b] | 546 | SETUP_ENDPOINT_LIST(USB_TRANSFER_ISOCHRONOUS);
|
---|
| 547 | SETUP_ENDPOINT_LIST(USB_TRANSFER_INTERRUPT);
|
---|
| 548 | SETUP_ENDPOINT_LIST(USB_TRANSFER_CONTROL);
|
---|
| 549 | SETUP_ENDPOINT_LIST(USB_TRANSFER_BULK);
|
---|
| 550 | #undef SETUP_ENDPOINT_LIST
|
---|
| 551 | endpoint_list_set_next(&instance->lists[USB_TRANSFER_INTERRUPT],
|
---|
| 552 | &instance->lists[USB_TRANSFER_ISOCHRONOUS]);
|
---|
[6b6e3ed3] | 553 |
|
---|
| 554 | return EOK;
|
---|
| 555 | }
|
---|
[344925c] | 556 | /*----------------------------------------------------------------------------*/
|
---|
[02cacce] | 557 | /** Initialize memory structures used by the OHCI hcd.
|
---|
| 558 | *
|
---|
| 559 | * @param[in] instance OHCI hc driver structure.
|
---|
| 560 | * @return Error code.
|
---|
| 561 | */
|
---|
[344925c] | 562 | int hc_init_memory(hc_t *instance)
|
---|
| 563 | {
|
---|
| 564 | assert(instance);
|
---|
[5d07f54] | 565 |
|
---|
| 566 | bzero(&instance->rh, sizeof(instance->rh));
|
---|
[8790650] | 567 | /* Init queues */
|
---|
[8953514] | 568 | const int ret = hc_init_transfer_lists(instance);
|
---|
| 569 | if (ret != EOK) {
|
---|
| 570 | return ret;
|
---|
| 571 | }
|
---|
[344925c] | 572 |
|
---|
[8790650] | 573 | /*Init HCCA */
|
---|
[344925c] | 574 | instance->hcca = malloc32(sizeof(hcca_t));
|
---|
| 575 | if (instance->hcca == NULL)
|
---|
| 576 | return ENOMEM;
|
---|
| 577 | bzero(instance->hcca, sizeof(hcca_t));
|
---|
[78d4e1f] | 578 | usb_log_debug2("OHCI HCCA initialized at %p.\n", instance->hcca);
|
---|
[344925c] | 579 |
|
---|
| 580 | unsigned i = 0;
|
---|
| 581 | for (; i < 32; ++i) {
|
---|
| 582 | instance->hcca->int_ep[i] =
|
---|
[5a2c42b] | 583 | instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa;
|
---|
[344925c] | 584 | }
|
---|
[4125b7d] | 585 | usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").\n",
|
---|
[5a2c42b] | 586 | instance->lists[USB_TRANSFER_INTERRUPT].list_head,
|
---|
| 587 | instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
|
---|
[344925c] | 588 |
|
---|
[561112f] | 589 | /* Init interrupt code */
|
---|
| 590 | instance->interrupt_code.cmds = instance->interrupt_commands;
|
---|
[02cacce] | 591 | instance->interrupt_code.cmdcount = OHCI_NEEDED_IRQ_COMMANDS;
|
---|
[561112f] | 592 | {
|
---|
| 593 | /* Read status register */
|
---|
| 594 | instance->interrupt_commands[0].cmd = CMD_MEM_READ_32;
|
---|
| 595 | instance->interrupt_commands[0].dstarg = 1;
|
---|
[03cfda08] | 596 | instance->interrupt_commands[0].addr =
|
---|
| 597 | (void*)&instance->registers->interrupt_status;
|
---|
[561112f] | 598 |
|
---|
| 599 | /* Test whether we are the interrupt cause */
|
---|
| 600 | instance->interrupt_commands[1].cmd = CMD_BTEST;
|
---|
| 601 | instance->interrupt_commands[1].value =
|
---|
| 602 | OHCI_USED_INTERRUPTS;
|
---|
| 603 | instance->interrupt_commands[1].srcarg = 1;
|
---|
| 604 | instance->interrupt_commands[1].dstarg = 2;
|
---|
| 605 |
|
---|
| 606 | /* Predicate cleaning and accepting */
|
---|
| 607 | instance->interrupt_commands[2].cmd = CMD_PREDICATE;
|
---|
| 608 | instance->interrupt_commands[2].value = 2;
|
---|
| 609 | instance->interrupt_commands[2].srcarg = 2;
|
---|
| 610 |
|
---|
[02cacce] | 611 | /* Write-clean status register */
|
---|
[03cfda08] | 612 | instance->interrupt_commands[3].cmd = CMD_MEM_WRITE_A_32;
|
---|
[561112f] | 613 | instance->interrupt_commands[3].srcarg = 1;
|
---|
[03cfda08] | 614 | instance->interrupt_commands[3].addr =
|
---|
| 615 | (void*)&instance->registers->interrupt_status;
|
---|
[561112f] | 616 |
|
---|
| 617 | /* Accept interrupt */
|
---|
| 618 | instance->interrupt_commands[4].cmd = CMD_ACCEPT;
|
---|
| 619 | }
|
---|
| 620 |
|
---|
[344925c] | 621 | return EOK;
|
---|
| 622 | }
|
---|
[41b96b4] | 623 | /**
|
---|
| 624 | * @}
|
---|
| 625 | */
|
---|