| [41b96b4] | 1 | /*
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| 2 | * Copyright (c) 2011 Jan Vesely
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| [8486c07] | 28 |
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| [41b96b4] | 29 | /** @addtogroup drvusbohcihc
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | * @brief OHCI Host controller driver routines
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| 34 | */
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| [8486c07] | 35 |
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| [0d4b110] | 36 | #include <assert.h>
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| 37 | #include <async.h>
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| [41b96b4] | 38 | #include <errno.h>
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| [0d4b110] | 39 | #include <macros.h>
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| 40 | #include <mem.h>
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| 41 | #include <stdlib.h>
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| [41b96b4] | 42 | #include <str_error.h>
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| [8d2dd7f2] | 43 | #include <stddef.h>
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| 44 | #include <stdint.h>
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| [41b96b4] | 45 |
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| 46 | #include <usb/debug.h>
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| 47 | #include <usb/usb.h>
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| 48 |
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| [e20eaed] | 49 | #include "ohci_endpoint.h"
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| [0d4b110] | 50 | #include "ohci_batch.h"
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| 51 |
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| 52 | #include "hc.h"
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| [41b96b4] | 53 |
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| [561112f] | 54 | #define OHCI_USED_INTERRUPTS \
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| 55 | (I_SO | I_WDH | I_UE | I_RHSC)
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| [1ecc5de] | 56 |
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| [d57122c] | 57 | static const irq_pio_range_t ohci_pio_ranges[] = {
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| 58 | {
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| [8486c07] | 59 | .base = 0,
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| [d57122c] | 60 | .size = sizeof(ohci_regs_t)
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| 61 | }
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| 62 | };
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| 63 |
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| 64 | static const irq_cmd_t ohci_irq_commands[] = {
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| [8486c07] | 65 | {
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| 66 | .cmd = CMD_PIO_READ_32,
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| 67 | .dstarg = 1,
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| 68 | .addr = NULL
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| 69 | },
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| 70 | {
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| 71 | .cmd = CMD_AND,
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| 72 | .srcarg = 1,
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| 73 | .dstarg = 2,
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| [ea8b91d] | 74 | .value = 0
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| [8486c07] | 75 | },
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| 76 | {
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| 77 | .cmd = CMD_PREDICATE,
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| 78 | .srcarg = 2,
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| 79 | .value = 2
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| 80 | },
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| 81 | {
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| 82 | .cmd = CMD_PIO_WRITE_A_32,
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| 83 | .srcarg = 1,
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| 84 | .addr = NULL
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| 85 | },
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| 86 | {
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| 87 | .cmd = CMD_ACCEPT
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| 88 | }
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| [1ecc5de] | 89 | };
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| 90 |
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| [6b6e3ed3] | 91 | static int hc_init_transfer_lists(hc_t *instance);
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| [344925c] | 92 | static int hc_init_memory(hc_t *instance);
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| [76fbd9a] | 93 |
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| [d57122c] | 94 | /** Generate IRQ code.
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| 95 | * @param[out] ranges PIO ranges buffer.
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| 96 | * @param[in] ranges_size Size of the ranges buffer (bytes).
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| 97 | * @param[out] cmds Commands buffer.
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| 98 | * @param[in] cmds_size Size of the commands buffer (bytes).
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| [ba4a03a5] | 99 | * @param[in] hw_res Device's resources.
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| [1cb4f05] | 100 | *
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| 101 | * @return Error code.
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| 102 | */
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| [e4d7363] | 103 | int ohci_hc_gen_irq_code(irq_code_t *code, hcd_t *hcd, const hw_res_list_parsed_t *hw_res)
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| [1cb4f05] | 104 | {
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| [6210a333] | 105 | assert(code);
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| [ba4a03a5] | 106 | assert(hw_res);
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| 107 |
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| 108 | if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
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| 109 | return EINVAL;
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| 110 |
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| 111 | const addr_range_t regs = hw_res->mem_ranges.ranges[0];
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| 112 |
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| 113 | if (RNGSZ(regs) < sizeof(ohci_regs_t))
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| [1cb4f05] | 114 | return EOVERFLOW;
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| 115 |
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| [6210a333] | 116 | code->ranges = malloc(sizeof(ohci_pio_ranges));
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| 117 | if (code->ranges == NULL)
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| 118 | return ENOMEM;
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| [1cb4f05] | 119 |
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| [6210a333] | 120 | code->cmds = malloc(sizeof(ohci_irq_commands));
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| 121 | if (code->cmds == NULL) {
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| 122 | free(code->ranges);
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| 123 | return ENOMEM;
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| 124 | }
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| 125 |
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| 126 | code->rangecount = ARRAY_SIZE(ohci_pio_ranges);
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| 127 | code->cmdcount = ARRAY_SIZE(ohci_irq_commands);
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| 128 |
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| 129 | memcpy(code->ranges, ohci_pio_ranges, sizeof(ohci_pio_ranges));
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| [ba4a03a5] | 130 | code->ranges[0].base = RNGABS(regs);
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| [6210a333] | 131 |
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| 132 | memcpy(code->cmds, ohci_irq_commands, sizeof(ohci_irq_commands));
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| [ba4a03a5] | 133 | ohci_regs_t *registers = (ohci_regs_t *) RNGABSPTR(regs);
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| [6210a333] | 134 | code->cmds[0].addr = (void *) ®isters->interrupt_status;
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| 135 | code->cmds[3].addr = (void *) ®isters->interrupt_status;
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| 136 | OHCI_WR(code->cmds[1].value, OHCI_USED_INTERRUPTS);
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| [1cb4f05] | 137 |
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| [ba4a03a5] | 138 | usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.\n",
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| 139 | RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
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| 140 |
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| 141 | return hw_res->irqs.irqs[0];
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| [1cb4f05] | 142 | }
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| [76fbd9a] | 143 |
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| [02cacce] | 144 | /** Initialize OHCI hc driver structure
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| 145 | *
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| 146 | * @param[in] instance Memory place for the structure.
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| [7813516] | 147 | * @param[in] regs Device's resources
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| [02cacce] | 148 | * @param[in] interrupts True if w interrupts should be used
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| 149 | * @return Error code
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| 150 | */
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| [e4d7363] | 151 | int hc_init(hc_t *instance, const hw_res_list_parsed_t *hw_res)
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| [41b96b4] | 152 | {
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| 153 | assert(instance);
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| [7813516] | 154 | assert(hw_res);
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| 155 | if (hw_res->mem_ranges.count != 1 ||
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| 156 | hw_res->mem_ranges.ranges[0].size < sizeof(ohci_regs_t))
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| 157 | return EINVAL;
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| [1cb4f05] | 158 |
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| [7813516] | 159 | int ret = pio_enable_range(&hw_res->mem_ranges.ranges[0],
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| 160 | (void **) &instance->registers);
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| [6340a6ff] | 161 | if (ret != EOK) {
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| [7813516] | 162 | usb_log_error("Failed to gain access to registers: %s.\n",
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| [6340a6ff] | 163 | str_error(ret));
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| 164 | return ret;
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| 165 | }
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| [7813516] | 166 | usb_log_debug("Device registers at %" PRIx64 " (%zuB) accessible.\n",
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| 167 | hw_res->mem_ranges.ranges[0].address.absolute,
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| 168 | hw_res->mem_ranges.ranges[0].size);
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| [c2be0e5] | 169 |
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| [bba0dc20] | 170 | list_initialize(&instance->pending_batches);
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| [6340a6ff] | 171 | fibril_mutex_initialize(&instance->guard);
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| [e7bc999] | 172 |
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| [8790650] | 173 | ret = hc_init_memory(instance);
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| [6340a6ff] | 174 | if (ret != EOK) {
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| 175 | usb_log_error("Failed to create OHCI memory structures: %s.\n",
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| 176 | str_error(ret));
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| [58563585] | 177 | // TODO: We should disable pio access here
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| [6340a6ff] | 178 | return ret;
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| 179 | }
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| [2c617b0] | 180 |
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| [8627377] | 181 | return EOK;
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| [a6d1bc1] | 182 | }
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| [76fbd9a] | 183 |
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| [7813516] | 184 | /** Safely dispose host controller internal structures
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| 185 | *
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| 186 | * @param[in] instance Host controller structure to use.
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| 187 | */
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| 188 | void hc_fini(hc_t *instance)
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| 189 | {
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| 190 | assert(instance);
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| 191 | /* TODO: implement*/
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| 192 | };
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| 193 |
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| [57e06ef] | 194 | void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
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| [620c710] | 195 | {
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| [57e06ef] | 196 | assert(instance);
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| 197 | assert(ep);
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| 198 |
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| [620c710] | 199 | endpoint_list_t *list = &instance->lists[ep->transfer_type];
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| 200 | ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
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| [57e06ef] | 201 | assert(list);
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| 202 | assert(ohci_ep);
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| 203 |
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| [620c710] | 204 | /* Enqueue ep */
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| 205 | switch (ep->transfer_type) {
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| 206 | case USB_TRANSFER_CONTROL:
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| [bfc5c9dd] | 207 | OHCI_CLR(instance->registers->control, C_CLE);
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| [620c710] | 208 | endpoint_list_add_ep(list, ohci_ep);
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| [bfc5c9dd] | 209 | OHCI_WR(instance->registers->control_current, 0);
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| 210 | OHCI_SET(instance->registers->control, C_CLE);
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| [620c710] | 211 | break;
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| 212 | case USB_TRANSFER_BULK:
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| [bfc5c9dd] | 213 | OHCI_CLR(instance->registers->control, C_BLE);
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| [f974519] | 214 | endpoint_list_add_ep(list, ohci_ep);
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| [bfc5c9dd] | 215 | OHCI_WR(instance->registers->bulk_current, 0);
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| 216 | OHCI_SET(instance->registers->control, C_BLE);
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| [620c710] | 217 | break;
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| 218 | case USB_TRANSFER_ISOCHRONOUS:
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| 219 | case USB_TRANSFER_INTERRUPT:
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| [bfc5c9dd] | 220 | OHCI_CLR(instance->registers->control, C_PLE | C_IE);
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| [f974519] | 221 | endpoint_list_add_ep(list, ohci_ep);
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| [bfc5c9dd] | 222 | OHCI_SET(instance->registers->control, C_PLE | C_IE);
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| [620c710] | 223 | break;
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| 224 | }
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| 225 | }
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| [76fbd9a] | 226 |
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| [57e06ef] | 227 | void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
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| [620c710] | 228 | {
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| [57e06ef] | 229 | assert(instance);
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| 230 | assert(ep);
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| 231 |
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| [620c710] | 232 | /* Dequeue ep */
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| 233 | endpoint_list_t *list = &instance->lists[ep->transfer_type];
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| 234 | ohci_endpoint_t *ohci_ep = ohci_endpoint_get(ep);
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| [57e06ef] | 235 |
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| 236 | assert(list);
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| 237 | assert(ohci_ep);
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| [620c710] | 238 | switch (ep->transfer_type) {
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| 239 | case USB_TRANSFER_CONTROL:
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| [bfc5c9dd] | 240 | OHCI_CLR(instance->registers->control, C_CLE);
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| [620c710] | 241 | endpoint_list_remove_ep(list, ohci_ep);
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| [bfc5c9dd] | 242 | OHCI_WR(instance->registers->control_current, 0);
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| 243 | OHCI_SET(instance->registers->control, C_CLE);
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| [620c710] | 244 | break;
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| 245 | case USB_TRANSFER_BULK:
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| [bfc5c9dd] | 246 | OHCI_CLR(instance->registers->control, C_BLE);
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| [620c710] | 247 | endpoint_list_remove_ep(list, ohci_ep);
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| [bfc5c9dd] | 248 | OHCI_WR(instance->registers->bulk_current, 0);
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| 249 | OHCI_SET(instance->registers->control, C_BLE);
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| [620c710] | 250 | break;
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| 251 | case USB_TRANSFER_ISOCHRONOUS:
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| 252 | case USB_TRANSFER_INTERRUPT:
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| [bfc5c9dd] | 253 | OHCI_CLR(instance->registers->control, C_PLE | C_IE);
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| [620c710] | 254 | endpoint_list_remove_ep(list, ohci_ep);
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| [bfc5c9dd] | 255 | OHCI_SET(instance->registers->control, C_PLE | C_IE);
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| [620c710] | 256 | break;
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| 257 | default:
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| 258 | break;
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| 259 | }
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| 260 | }
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| [76fbd9a] | 261 |
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| [fccf289] | 262 | int ohci_hc_status(hcd_t *hcd, uint32_t *status)
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| [e26a9d95] | 263 | {
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| 264 | assert(hcd);
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| 265 | assert(status);
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| [b5f813c] | 266 | hc_t *instance = hcd_get_driver_data(hcd);
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| [e26a9d95] | 267 | assert(instance);
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| 268 |
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| 269 | if (instance->registers){
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| 270 | *status = OHCI_RD(instance->registers->interrupt_status);
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| 271 | OHCI_WR(instance->registers->interrupt_status, *status);
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| 272 | }
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| 273 | return EOK;
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| 274 | }
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| 275 |
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| [02cacce] | 276 | /** Add USB transfer to the schedule.
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| 277 | *
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| [fccf289] | 278 | * @param[in] hcd HCD driver structure.
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| [02cacce] | 279 | * @param[in] batch Batch representing the transfer.
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| 280 | * @return Error code.
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| 281 | */
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| [fccf289] | 282 | int ohci_hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
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| [41b96b4] | 283 | {
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| [09ace19] | 284 | assert(hcd);
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| [b5f813c] | 285 | hc_t *instance = hcd_get_driver_data(hcd);
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| [41b96b4] | 286 | assert(instance);
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| [9ff5ff82] | 287 |
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| [02cacce] | 288 | /* Check for root hub communication */
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| [171e668] | 289 | if (batch->ep->address == ohci_rh_get_address(&instance->rh)) {
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| [ffcc5776] | 290 | usb_log_debug("OHCI root hub request.\n");
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| [171e668] | 291 | return ohci_rh_schedule(&instance->rh, batch);
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| [41b96b4] | 292 | }
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| [9c10e51] | 293 | ohci_transfer_batch_t *ohci_batch = ohci_transfer_batch_get(batch);
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| 294 | if (!ohci_batch)
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| 295 | return ENOMEM;
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| [7013b14] | 296 |
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| [aa9ccf7] | 297 | fibril_mutex_lock(&instance->guard);
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| [9c10e51] | 298 | list_append(&ohci_batch->link, &instance->pending_batches);
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| 299 | ohci_transfer_batch_commit(ohci_batch);
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| [02cacce] | 300 |
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| 301 | /* Control and bulk schedules need a kick to start working */
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| 302 | switch (batch->ep->transfer_type)
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| 303 | {
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| [9ff5ff82] | 304 | case USB_TRANSFER_CONTROL:
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| [bfc5c9dd] | 305 | OHCI_SET(instance->registers->command_status, CS_CLF);
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| [9ff5ff82] | 306 | break;
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| 307 | case USB_TRANSFER_BULK:
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| [bfc5c9dd] | 308 | OHCI_SET(instance->registers->command_status, CS_BLF);
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| [9ff5ff82] | 309 | break;
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| 310 | default:
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| 311 | break;
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| 312 | }
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| [aa9ccf7] | 313 | fibril_mutex_unlock(&instance->guard);
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| [4c28d17] | 314 | return EOK;
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| [41b96b4] | 315 | }
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| [76fbd9a] | 316 |
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| [02cacce] | 317 | /** Interrupt handling routine
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| 318 | *
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| [fccf289] | 319 | * @param[in] hcd HCD driver structure.
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| [02cacce] | 320 | * @param[in] status Value of the status register at the time of interrupt.
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| 321 | */
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| [fccf289] | 322 | void ohci_hc_interrupt(hcd_t *hcd, uint32_t status)
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| [41b96b4] | 323 | {
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| [4bfcf22] | 324 | assert(hcd);
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| [b5f813c] | 325 | hc_t *instance = hcd_get_driver_data(hcd);
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| [d1ca752] | 326 | status = OHCI_RD(status);
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| [41b96b4] | 327 | assert(instance);
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| [561112f] | 328 | if ((status & ~I_SF) == 0) /* ignore sof status */
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| [eaf1e3d] | 329 | return;
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| [2df648c2] | 330 | usb_log_debug2("OHCI(%p) interrupt: %x.\n", instance, status);
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| [561112f] | 331 | if (status & I_RHSC)
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| [171e668] | 332 | ohci_rh_interrupt(&instance->rh);
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| [7d6a676] | 333 |
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| [561112f] | 334 | if (status & I_WDH) {
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| [aa9ccf7] | 335 | fibril_mutex_lock(&instance->guard);
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| [4125b7d] | 336 | usb_log_debug2("HCCA: %p-%#" PRIx32 " (%p).\n", instance->hcca,
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| [bfc5c9dd] | 337 | OHCI_RD(instance->registers->hcca),
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| [4125b7d] | 338 | (void *) addr_to_phys(instance->hcca));
|
|---|
| 339 | usb_log_debug2("Periodic current: %#" PRIx32 ".\n",
|
|---|
| [bfc5c9dd] | 340 | OHCI_RD(instance->registers->periodic_current));
|
|---|
| [eaf1e3d] | 341 |
|
|---|
| [9c10e51] | 342 | link_t *current = list_first(&instance->pending_batches);
|
|---|
| 343 | while (current && current != &instance->pending_batches.head) {
|
|---|
| [7013b14] | 344 | link_t *next = current->next;
|
|---|
| [9c10e51] | 345 | ohci_transfer_batch_t *batch =
|
|---|
| 346 | ohci_transfer_batch_from_link(current);
|
|---|
| [7013b14] | 347 |
|
|---|
| [9c10e51] | 348 | if (ohci_transfer_batch_is_complete(batch)) {
|
|---|
| [d6522dd] | 349 | list_remove(current);
|
|---|
| [9c10e51] | 350 | ohci_transfer_batch_finish_dispose(batch);
|
|---|
| [7013b14] | 351 | }
|
|---|
| [b72efe8] | 352 |
|
|---|
| [7013b14] | 353 | current = next;
|
|---|
| [eaf1e3d] | 354 | }
|
|---|
| [aa9ccf7] | 355 | fibril_mutex_unlock(&instance->guard);
|
|---|
| [4c28d17] | 356 | }
|
|---|
| [68b9f148] | 357 |
|
|---|
| 358 | if (status & I_UE) {
|
|---|
| [f974519] | 359 | usb_log_fatal("Error like no other!\n");
|
|---|
| [1ef93fa] | 360 | hc_start(instance);
|
|---|
| [68b9f148] | 361 | }
|
|---|
| 362 |
|
|---|
| [41b96b4] | 363 | }
|
|---|
| [76fbd9a] | 364 |
|
|---|
| [02cacce] | 365 | /** Turn off any (BIOS)driver that might be in control of the device.
|
|---|
| [78ab6d4] | 366 | *
|
|---|
| 367 | * This function implements routines described in chapter 5.1.1.3 of the OHCI
|
|---|
| 368 | * specification (page 40, pdf page 54).
|
|---|
| [02cacce] | 369 | *
|
|---|
| 370 | * @param[in] instance OHCI hc driver structure.
|
|---|
| 371 | */
|
|---|
| [2c617b0] | 372 | void hc_gain_control(hc_t *instance)
|
|---|
| 373 | {
|
|---|
| 374 | assert(instance);
|
|---|
| [78ab6d4] | 375 |
|
|---|
| [c8eddf4] | 376 | usb_log_debug("Requesting OHCI control.\n");
|
|---|
| [bfc5c9dd] | 377 | if (OHCI_RD(instance->registers->revision) & R_LEGACY_FLAG) {
|
|---|
| [78ab6d4] | 378 | /* Turn off legacy emulation, it should be enough to zero
|
|---|
| 379 | * the lowest bit, but it caused problems. Thus clear all
|
|---|
| 380 | * except GateA20 (causes restart on some hw).
|
|---|
| 381 | * See page 145 of the specs for details.
|
|---|
| 382 | */
|
|---|
| 383 | volatile uint32_t *ohci_emulation_reg =
|
|---|
| 384 | (uint32_t*)((char*)instance->registers + LEGACY_REGS_OFFSET);
|
|---|
| 385 | usb_log_debug("OHCI legacy register %p: %x.\n",
|
|---|
| [bfc5c9dd] | 386 | ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
|
|---|
| [78ab6d4] | 387 | /* Zero everything but A20State */
|
|---|
| [58563585] | 388 | // TODO: should we ack interrupts before doing this?
|
|---|
| [bfc5c9dd] | 389 | OHCI_CLR(*ohci_emulation_reg, ~0x100);
|
|---|
| [78ab6d4] | 390 | usb_log_debug(
|
|---|
| 391 | "OHCI legacy register (should be 0 or 0x100) %p: %x.\n",
|
|---|
| [bfc5c9dd] | 392 | ohci_emulation_reg, OHCI_RD(*ohci_emulation_reg));
|
|---|
| [78ab6d4] | 393 | }
|
|---|
| [112d159] | 394 |
|
|---|
| [2c617b0] | 395 | /* Interrupt routing enabled => smm driver is active */
|
|---|
| [bfc5c9dd] | 396 | if (OHCI_RD(instance->registers->control) & C_IR) {
|
|---|
| [112d159] | 397 | usb_log_debug("SMM driver: request ownership change.\n");
|
|---|
| [58563585] | 398 | // TODO: should we ack interrupts before doing this?
|
|---|
| [bfc5c9dd] | 399 | OHCI_SET(instance->registers->command_status, CS_OCR);
|
|---|
| [78ab6d4] | 400 | /* Hope that SMM actually knows its stuff or we can hang here */
|
|---|
| [f5bfd98] | 401 | while (OHCI_RD(instance->registers->control) & C_IR) {
|
|---|
| [2c617b0] | 402 | async_usleep(1000);
|
|---|
| 403 | }
|
|---|
| [112d159] | 404 | usb_log_info("SMM driver: Ownership taken.\n");
|
|---|
| [78ab6d4] | 405 | C_HCFS_SET(instance->registers->control, C_HCFS_RESET);
|
|---|
| [5d07f54] | 406 | async_usleep(50000);
|
|---|
| [2c617b0] | 407 | return;
|
|---|
| 408 | }
|
|---|
| [8486c07] | 409 |
|
|---|
| [78ab6d4] | 410 | const unsigned hc_status = C_HCFS_GET(instance->registers->control);
|
|---|
| [2c617b0] | 411 | /* Interrupt routing disabled && status != USB_RESET => BIOS active */
|
|---|
| 412 | if (hc_status != C_HCFS_RESET) {
|
|---|
| [112d159] | 413 | usb_log_debug("BIOS driver found.\n");
|
|---|
| [2c617b0] | 414 | if (hc_status == C_HCFS_OPERATIONAL) {
|
|---|
| [112d159] | 415 | usb_log_info("BIOS driver: HC operational.\n");
|
|---|
| [2c617b0] | 416 | return;
|
|---|
| 417 | }
|
|---|
| [bfc5c9dd] | 418 | /* HC is suspended assert resume for 20ms */
|
|---|
| [78ab6d4] | 419 | C_HCFS_SET(instance->registers->control, C_HCFS_RESUME);
|
|---|
| [2c617b0] | 420 | async_usleep(20000);
|
|---|
| [112d159] | 421 | usb_log_info("BIOS driver: HC resumed.\n");
|
|---|
| [2c617b0] | 422 | return;
|
|---|
| 423 | }
|
|---|
| 424 |
|
|---|
| 425 | /* HC is in reset (hw startup) => no other driver
|
|---|
| 426 | * maintain reset for at least the time specified in USB spec (50 ms)*/
|
|---|
| [c4fb5ecd] | 427 | usb_log_debug("Host controller found in reset state.\n");
|
|---|
| [2c617b0] | 428 | async_usleep(50000);
|
|---|
| 429 | }
|
|---|
| [76fbd9a] | 430 |
|
|---|
| [02cacce] | 431 | /** OHCI hw initialization routine.
|
|---|
| 432 | *
|
|---|
| 433 | * @param[in] instance OHCI hc driver structure.
|
|---|
| 434 | */
|
|---|
| [1ef93fa] | 435 | void hc_start(hc_t *instance)
|
|---|
| [2c617b0] | 436 | {
|
|---|
| [e4d7363] | 437 | ohci_rh_init(&instance->rh, instance->registers, "ohci rh");
|
|---|
| 438 |
|
|---|
| [112d159] | 439 | /* OHCI guide page 42 */
|
|---|
| [2c617b0] | 440 | assert(instance);
|
|---|
| [112d159] | 441 | usb_log_debug2("Started hc initialization routine.\n");
|
|---|
| 442 |
|
|---|
| 443 | /* Save contents of fm_interval register */
|
|---|
| [bfc5c9dd] | 444 | const uint32_t fm_interval = OHCI_RD(instance->registers->fm_interval);
|
|---|
| [112d159] | 445 | usb_log_debug2("Old value of HcFmInterval: %x.\n", fm_interval);
|
|---|
| [344925c] | 446 |
|
|---|
| [112d159] | 447 | /* Reset hc */
|
|---|
| 448 | usb_log_debug2("HC reset.\n");
|
|---|
| 449 | size_t time = 0;
|
|---|
| [bfc5c9dd] | 450 | OHCI_WR(instance->registers->command_status, CS_HCR);
|
|---|
| 451 | while (OHCI_RD(instance->registers->command_status) & CS_HCR) {
|
|---|
| [112d159] | 452 | async_usleep(10);
|
|---|
| 453 | time += 10;
|
|---|
| 454 | }
|
|---|
| 455 | usb_log_debug2("HC reset complete in %zu us.\n", time);
|
|---|
| [344925c] | 456 |
|
|---|
| [112d159] | 457 | /* Restore fm_interval */
|
|---|
| [bfc5c9dd] | 458 | OHCI_WR(instance->registers->fm_interval, fm_interval);
|
|---|
| 459 | assert((OHCI_RD(instance->registers->command_status) & CS_HCR) == 0);
|
|---|
| [344925c] | 460 |
|
|---|
| [2c617b0] | 461 | /* hc is now in suspend state */
|
|---|
| [112d159] | 462 | usb_log_debug2("HC should be in suspend state(%x).\n",
|
|---|
| [bfc5c9dd] | 463 | OHCI_RD(instance->registers->control));
|
|---|
| [344925c] | 464 |
|
|---|
| [78d4e1f] | 465 | /* Use HCCA */
|
|---|
| [bfc5c9dd] | 466 | OHCI_WR(instance->registers->hcca, addr_to_phys(instance->hcca));
|
|---|
| [78d4e1f] | 467 |
|
|---|
| 468 | /* Use queues */
|
|---|
| [bfc5c9dd] | 469 | OHCI_WR(instance->registers->bulk_head,
|
|---|
| 470 | instance->lists[USB_TRANSFER_BULK].list_head_pa);
|
|---|
| [4125b7d] | 471 | usb_log_debug2("Bulk HEAD set to: %p (%#" PRIx32 ").\n",
|
|---|
| [5a2c42b] | 472 | instance->lists[USB_TRANSFER_BULK].list_head,
|
|---|
| 473 | instance->lists[USB_TRANSFER_BULK].list_head_pa);
|
|---|
| [78d4e1f] | 474 |
|
|---|
| [bfc5c9dd] | 475 | OHCI_WR(instance->registers->control_head,
|
|---|
| 476 | instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
|
|---|
| [4125b7d] | 477 | usb_log_debug2("Control HEAD set to: %p (%#" PRIx32 ").\n",
|
|---|
| [5a2c42b] | 478 | instance->lists[USB_TRANSFER_CONTROL].list_head,
|
|---|
| 479 | instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
|
|---|
| [78d4e1f] | 480 |
|
|---|
| [112d159] | 481 | /* Enable queues */
|
|---|
| [65eac7b] | 482 | OHCI_SET(instance->registers->control, (C_PLE | C_IE | C_CLE | C_BLE));
|
|---|
| 483 | usb_log_debug("Queues enabled(%x).\n",
|
|---|
| 484 | OHCI_RD(instance->registers->control));
|
|---|
| [112d159] | 485 |
|
|---|
| [561112f] | 486 | /* Enable interrupts */
|
|---|
| [a5361fb] | 487 | if (instance->hw_interrupts) {
|
|---|
| 488 | OHCI_WR(instance->registers->interrupt_enable,
|
|---|
| 489 | OHCI_USED_INTERRUPTS);
|
|---|
| 490 | usb_log_debug("Enabled interrupts: %x.\n",
|
|---|
| 491 | OHCI_RD(instance->registers->interrupt_enable));
|
|---|
| 492 | OHCI_WR(instance->registers->interrupt_enable, I_MI);
|
|---|
| 493 | }
|
|---|
| [112d159] | 494 |
|
|---|
| 495 | /* Set periodic start to 90% */
|
|---|
| [bfc5c9dd] | 496 | const uint32_t frame_length =
|
|---|
| 497 | (fm_interval >> FMI_FI_SHIFT) & FMI_FI_MASK;
|
|---|
| 498 | OHCI_WR(instance->registers->periodic_start,
|
|---|
| 499 | ((frame_length / 10) * 9) & PS_MASK << PS_SHIFT);
|
|---|
| [112d159] | 500 | usb_log_debug2("All periodic start set to: %x(%u - 90%% of %d).\n",
|
|---|
| [bfc5c9dd] | 501 | OHCI_RD(instance->registers->periodic_start),
|
|---|
| 502 | OHCI_RD(instance->registers->periodic_start), frame_length);
|
|---|
| [78ab6d4] | 503 | C_HCFS_SET(instance->registers->control, C_HCFS_OPERATIONAL);
|
|---|
| [c4fb5ecd] | 504 | usb_log_debug("OHCI HC up and running (ctl_reg=0x%x).\n",
|
|---|
| [bfc5c9dd] | 505 | OHCI_RD(instance->registers->control));
|
|---|
| [2c617b0] | 506 | }
|
|---|
| [76fbd9a] | 507 |
|
|---|
| [02cacce] | 508 | /** Initialize schedule queues
|
|---|
| 509 | *
|
|---|
| 510 | * @param[in] instance OHCI hc driver structure
|
|---|
| 511 | * @return Error code
|
|---|
| 512 | */
|
|---|
| [6b6e3ed3] | 513 | int hc_init_transfer_lists(hc_t *instance)
|
|---|
| 514 | {
|
|---|
| 515 | assert(instance);
|
|---|
| [5a2c42b] | 516 | #define SETUP_ENDPOINT_LIST(type) \
|
|---|
| [344925c] | 517 | do { \
|
|---|
| [5a2c42b] | 518 | const char *name = usb_str_transfer_type(type); \
|
|---|
| [6340a6ff] | 519 | const int ret = endpoint_list_init(&instance->lists[type], name); \
|
|---|
| [6b6e3ed3] | 520 | if (ret != EOK) { \
|
|---|
| [1cb4f05] | 521 | usb_log_error("Failed to setup %s endpoint list: %s.\n", \
|
|---|
| 522 | name, str_error(ret)); \
|
|---|
| [68b9f148] | 523 | endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]);\
|
|---|
| [5a2c42b] | 524 | endpoint_list_fini(&instance->lists[USB_TRANSFER_INTERRUPT]); \
|
|---|
| 525 | endpoint_list_fini(&instance->lists[USB_TRANSFER_CONTROL]); \
|
|---|
| 526 | endpoint_list_fini(&instance->lists[USB_TRANSFER_BULK]); \
|
|---|
| [70c85320] | 527 | return ret; \
|
|---|
| [344925c] | 528 | } \
|
|---|
| 529 | } while (0)
|
|---|
| [6b6e3ed3] | 530 |
|
|---|
| [5a2c42b] | 531 | SETUP_ENDPOINT_LIST(USB_TRANSFER_ISOCHRONOUS);
|
|---|
| 532 | SETUP_ENDPOINT_LIST(USB_TRANSFER_INTERRUPT);
|
|---|
| 533 | SETUP_ENDPOINT_LIST(USB_TRANSFER_CONTROL);
|
|---|
| 534 | SETUP_ENDPOINT_LIST(USB_TRANSFER_BULK);
|
|---|
| 535 | #undef SETUP_ENDPOINT_LIST
|
|---|
| 536 | endpoint_list_set_next(&instance->lists[USB_TRANSFER_INTERRUPT],
|
|---|
| 537 | &instance->lists[USB_TRANSFER_ISOCHRONOUS]);
|
|---|
| [6b6e3ed3] | 538 |
|
|---|
| 539 | return EOK;
|
|---|
| 540 | }
|
|---|
| [76fbd9a] | 541 |
|
|---|
| [02cacce] | 542 | /** Initialize memory structures used by the OHCI hcd.
|
|---|
| 543 | *
|
|---|
| 544 | * @param[in] instance OHCI hc driver structure.
|
|---|
| 545 | * @return Error code.
|
|---|
| 546 | */
|
|---|
| [344925c] | 547 | int hc_init_memory(hc_t *instance)
|
|---|
| 548 | {
|
|---|
| 549 | assert(instance);
|
|---|
| [5d07f54] | 550 |
|
|---|
| [acdb5bac] | 551 | memset(&instance->rh, 0, sizeof(instance->rh));
|
|---|
| [8790650] | 552 | /* Init queues */
|
|---|
| [8953514] | 553 | const int ret = hc_init_transfer_lists(instance);
|
|---|
| 554 | if (ret != EOK) {
|
|---|
| 555 | return ret;
|
|---|
| 556 | }
|
|---|
| [344925c] | 557 |
|
|---|
| [8790650] | 558 | /*Init HCCA */
|
|---|
| [f8dfb40] | 559 | instance->hcca = hcca_get();
|
|---|
| [344925c] | 560 | if (instance->hcca == NULL)
|
|---|
| 561 | return ENOMEM;
|
|---|
| [78d4e1f] | 562 | usb_log_debug2("OHCI HCCA initialized at %p.\n", instance->hcca);
|
|---|
| [344925c] | 563 |
|
|---|
| [1b90e90] | 564 | for (unsigned i = 0; i < HCCA_INT_EP_COUNT; ++i) {
|
|---|
| 565 | hcca_set_int_ep(instance->hcca, i,
|
|---|
| [65eac7b] | 566 | instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
|
|---|
| [344925c] | 567 | }
|
|---|
| [4125b7d] | 568 | usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").\n",
|
|---|
| [5a2c42b] | 569 | instance->lists[USB_TRANSFER_INTERRUPT].list_head,
|
|---|
| 570 | instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
|
|---|
| [344925c] | 571 |
|
|---|
| 572 | return EOK;
|
|---|
| 573 | }
|
|---|
| [1ecc5de] | 574 |
|
|---|
| [41b96b4] | 575 | /**
|
|---|
| 576 | * @}
|
|---|
| 577 | */
|
|---|