source: mainline/uspace/drv/bus/usb/ehci/res.c@ 698cb1cc

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 698cb1cc was 698cb1cc, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

ehci: cleanup and rename pci_* helper functions.

The functions are not pci specific.
Use libc provided pci interface instead of reimplementing it.
Use parsed hw_resource.
Cleanup includes.
  • Property mode set to 100644
File size: 9.4 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/**
30 * @addtogroup drvusbehci
31 * @{
32 */
33/**
34 * @file
35 * PCI related functions needed by the EHCI driver.
36 */
37
38#include <errno.h>
39#include <str_error.h>
40#include <assert.h>
41#include <devman.h>
42#include <ddi.h>
43#include <usb/debug.h>
44#include <device/hw_res_parsed.h>
45#include <device/pci.h>
46
47#include "res.h"
48
49#define PAGE_SIZE_MASK 0xfffff000
50
51#define HCC_PARAMS_OFFSET 0x8
52#define HCC_PARAMS_EECP_MASK 0xff
53#define HCC_PARAMS_EECP_OFFSET 8
54
55#define CMD_OFFSET 0x0
56#define STS_OFFSET 0x4
57#define INT_OFFSET 0x8
58#define CFG_OFFSET 0x40
59
60#define USBCMD_RUN 1
61#define USBSTS_HALTED (1 << 12)
62
63#define USBLEGSUP_OFFSET 0
64#define USBLEGSUP_BIOS_CONTROL (1 << 16)
65#define USBLEGSUP_OS_CONTROL (1 << 24)
66#define USBLEGCTLSTS_OFFSET 4
67
68#define DEFAULT_WAIT 1000
69#define WAIT_STEP 10
70
71
72/** Get address of registers and IRQ for given device.
73 *
74 * @param[in] dev Device asking for the addresses.
75 * @param[out] mem_reg_address Base address of the memory range.
76 * @param[out] mem_reg_size Size of the memory range.
77 * @param[out] irq_no IRQ assigned to the device.
78 * @return Error code.
79 */
80int get_my_registers(const ddf_dev_t *dev,
81 uintptr_t *mem_reg_address, size_t *mem_reg_size, int *irq_no)
82{
83 assert(dev);
84
85 async_sess_t *parent_sess = devman_parent_device_connect(
86 EXCHANGE_SERIALIZE, dev->handle, IPC_FLAG_BLOCKING);
87 if (!parent_sess)
88 return ENOMEM;
89
90 hw_res_list_parsed_t hw_res;
91 hw_res_list_parsed_init(&hw_res);
92 const int ret = hw_res_get_list_parsed(parent_sess, &hw_res, 0);
93 async_hangup(parent_sess);
94 if (ret != EOK) {
95 return ret;
96 }
97
98 if (hw_res.irqs.count != 1 || hw_res.mem_ranges.count != 1) {
99 hw_res_list_parsed_clean(&hw_res);
100 return ENOENT;
101 }
102
103 if (mem_reg_address)
104 *mem_reg_address = hw_res.mem_ranges.ranges[0].address;
105 if (mem_reg_size)
106 *mem_reg_size = hw_res.mem_ranges.ranges[0].size;
107 if (irq_no)
108 *irq_no = hw_res.irqs.irqs[0];
109
110 hw_res_list_parsed_clean(&hw_res);
111 return EOK;
112}
113/*----------------------------------------------------------------------------*/
114/** Calls the PCI driver with a request to enable interrupts
115 *
116 * @param[in] device Device asking for interrupts
117 * @return Error code.
118 */
119int enable_interrupts(const ddf_dev_t *device)
120{
121 async_sess_t *parent_sess = devman_parent_device_connect(
122 EXCHANGE_SERIALIZE, device->handle, IPC_FLAG_BLOCKING);
123 if (!parent_sess)
124 return ENOMEM;
125
126 const bool enabled = hw_res_enable_interrupt(parent_sess);
127 async_hangup(parent_sess);
128
129 return enabled ? EOK : EIO;
130}
131/*----------------------------------------------------------------------------*/
132/** Implements BIOS handoff routine as decribed in EHCI spec
133 *
134 * @param[in] device Device asking for interrupts
135 * @return Error code.
136 */
137int disable_legacy(const ddf_dev_t *device, uintptr_t reg_base, size_t reg_size)
138{
139 assert(device);
140 async_sess_t *parent_sess = devman_parent_device_connect(
141 EXCHANGE_SERIALIZE, device->handle, IPC_FLAG_BLOCKING);
142 if (!parent_sess)
143 return ENOMEM;
144
145#define CHECK_RET_RETURN(ret, message...) \
146 if (ret != EOK) { \
147 usb_log_error(message); \
148 async_hangup(parent_sess); \
149 return ret; \
150 } else (void)0
151
152 /* Map EHCI registers */
153 void *regs = NULL;
154 int ret = pio_enable((void*)reg_base, reg_size, &regs);
155 CHECK_RET_RETURN(ret, "Failed to map registers %p: %s.\n",
156 (void *) reg_base, str_error(ret));
157
158 const uint32_t hcc_params =
159 *(uint32_t*)(regs + HCC_PARAMS_OFFSET);
160 usb_log_debug("Value of hcc params register: %x.\n", hcc_params);
161
162 /* Read value of EHCI Extended Capabilities Pointer
163 * position of EEC registers (points to PCI config space) */
164 const uint32_t eecp =
165 (hcc_params >> HCC_PARAMS_EECP_OFFSET) & HCC_PARAMS_EECP_MASK;
166 usb_log_debug("Value of EECP: %x.\n", eecp);
167
168 /* Read the first EEC. i.e. Legacy Support register */
169 uint32_t usblegsup;
170 ret = pci_config_space_read_32(parent_sess,
171 eecp + USBLEGSUP_OFFSET, &usblegsup);
172 CHECK_RET_RETURN(ret, "Failed to read USBLEGSUP: %s.\n", str_error(ret));
173 usb_log_debug("USBLEGSUP: %" PRIx32 ".\n", usblegsup);
174
175 /* Request control from firmware/BIOS, by writing 1 to highest byte.
176 * (OS Control semaphore)*/
177 usb_log_debug("Requesting OS control.\n");
178 ret = pci_config_space_write_8(parent_sess,
179 eecp + USBLEGSUP_OFFSET + 3, 1);
180 CHECK_RET_RETURN(ret, "Failed to request OS EHCI control: %s.\n",
181 str_error(ret));
182
183 size_t wait = 0;
184 /* Wait for BIOS to release control. */
185 ret = pci_config_space_read_32(parent_sess,
186 eecp + USBLEGSUP_OFFSET, &usblegsup);
187 while ((wait < DEFAULT_WAIT) && (usblegsup & USBLEGSUP_BIOS_CONTROL)) {
188 async_usleep(WAIT_STEP);
189 ret = pci_config_space_read_32(parent_sess,
190 eecp + USBLEGSUP_OFFSET, &usblegsup);
191 wait += WAIT_STEP;
192 }
193
194
195 if ((usblegsup & USBLEGSUP_BIOS_CONTROL) == 0) {
196 usb_log_info("BIOS released control after %zu usec.\n", wait);
197 } else {
198 /* BIOS failed to hand over control, this should not happen. */
199 usb_log_warning( "BIOS failed to release control after "
200 "%zu usecs, force it.\n", wait);
201 ret = pci_config_space_write_32(parent_sess,
202 eecp + USBLEGSUP_OFFSET, USBLEGSUP_OS_CONTROL);
203 CHECK_RET_RETURN(ret, "Failed to force OS control: %s.\n",
204 str_error(ret));
205 /* Check capability type here, A value of 01h
206 * identifies the capability as Legacy Support.
207 * This extended capability requires one
208 * additional 32-bit register for control/status information,
209 * and this register is located at offset EECP+04h
210 * */
211 if ((usblegsup & 0xff) == 1) {
212 /* Read the second EEC
213 * Legacy Support and Control register */
214 uint32_t usblegctlsts;
215 ret = pci_config_space_read_32(parent_sess,
216 eecp + USBLEGCTLSTS_OFFSET, &usblegctlsts);
217 CHECK_RET_RETURN(ret,
218 "Failed to get USBLEGCTLSTS: %s.\n", str_error(ret));
219 usb_log_debug("USBLEGCTLSTS: %" PRIx32 ".\n",
220 usblegctlsts);
221 /* Zero SMI enables in legacy control register.
222 * It should prevent pre-OS code from interfering.
223 * Three upper bits are WC */
224 ret = pci_config_space_write_32(parent_sess,
225 eecp + USBLEGCTLSTS_OFFSET, 0xe0000000);
226 CHECK_RET_RETURN(ret,
227 "Failed(%d) zero USBLEGCTLSTS.\n", ret);
228 udelay(10);
229 ret = pci_config_space_read_32(parent_sess,
230 eecp + USBLEGCTLSTS_OFFSET, &usblegctlsts);
231 CHECK_RET_RETURN(ret,
232 "Failed to get USBLEGCTLSTS 2: %s.\n",
233 str_error(ret));
234 usb_log_debug("Zeroed USBLEGCTLSTS: %" PRIx32 ".\n",
235 usblegctlsts);
236 }
237 }
238
239
240 /* Read again Legacy Support register */
241 ret = pci_config_space_read_32(parent_sess,
242 eecp + USBLEGSUP_OFFSET, &usblegsup);
243 CHECK_RET_RETURN(ret, "Failed to read USBLEGSUP: %s.\n", str_error(ret));
244 usb_log_debug("USBLEGSUP: %" PRIx32 ".\n", usblegsup);
245
246 async_hangup(parent_sess);
247#undef CHECK_RET_RETURN
248
249 /*
250 * TURN OFF EHCI FOR NOW, DRIVER WILL REINITIALIZE IT IF NEEDED
251 */
252
253 /* Get size of capability registers in memory space. */
254 const unsigned operation_offset = *(uint8_t*)regs;
255 usb_log_debug("USBCMD offset: %d.\n", operation_offset);
256
257 /* Zero USBCMD register. */
258 volatile uint32_t *usbcmd =
259 (uint32_t*)((uint8_t*)regs + operation_offset + CMD_OFFSET);
260 volatile uint32_t *usbsts =
261 (uint32_t*)((uint8_t*)regs + operation_offset + STS_OFFSET);
262 volatile uint32_t *usbconf =
263 (uint32_t*)((uint8_t*)regs + operation_offset + CFG_OFFSET);
264 volatile uint32_t *usbint =
265 (uint32_t*)((uint8_t*)regs + operation_offset + INT_OFFSET);
266 usb_log_debug("USBCMD value: %x.\n", *usbcmd);
267 if (*usbcmd & USBCMD_RUN) {
268 *usbsts = 0x3f; /* ack all interrupts */
269 *usbint = 0; /* disable all interrutps */
270 *usbconf = 0; /* relase control of RH ports */
271
272 *usbcmd = 0;
273 /* Wait until hc is halted */
274 while ((*usbsts & USBSTS_HALTED) == 0);
275 usb_log_info("EHCI turned off.\n");
276 } else {
277 usb_log_info("EHCI was not running.\n");
278 }
279 usb_log_debug("Registers: \n"
280 "\t USBCMD: %x(0x00080000 = at least 1ms between interrupts)\n"
281 "\t USBSTS: %x(0x00001000 = HC halted)\n"
282 "\t USBINT: %x(0x0 = no interrupts).\n"
283 "\t CONFIG: %x(0x0 = ports controlled by companion hc).\n",
284 *usbcmd, *usbsts, *usbint, *usbconf);
285
286 return ret;
287}
288
289/**
290 * @}
291 */
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