source: mainline/uspace/drv/bus/usb/ehci/res.c@ 39d15f3

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 39d15f3 was 39d15f3, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

ehci: Remove unused define
  • Property mode set to 100644
File size: 9.3 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/**
30 * @addtogroup drvusbehci
31 * @{
32 */
33/**
34 * @file
35 * PCI related functions needed by the EHCI driver.
36 */
37
38#include <errno.h>
39#include <str_error.h>
40#include <assert.h>
41#include <devman.h>
42#include <ddi.h>
43#include <usb/debug.h>
44#include <device/hw_res_parsed.h>
45#include <device/pci.h>
46
47#include "res.h"
48
49#define HCC_PARAMS_OFFSET 0x8
50#define HCC_PARAMS_EECP_MASK 0xff
51#define HCC_PARAMS_EECP_OFFSET 8
52
53#define CMD_OFFSET 0x0
54#define STS_OFFSET 0x4
55#define INT_OFFSET 0x8
56#define CFG_OFFSET 0x40
57
58#define USBCMD_RUN 1
59#define USBSTS_HALTED (1 << 12)
60
61#define USBLEGSUP_OFFSET 0
62#define USBLEGSUP_BIOS_CONTROL (1 << 16)
63#define USBLEGSUP_OS_CONTROL (1 << 24)
64#define USBLEGCTLSTS_OFFSET 4
65
66#define DEFAULT_WAIT 1000
67#define WAIT_STEP 10
68
69
70/** Get address of registers and IRQ for given device.
71 *
72 * @param[in] dev Device asking for the addresses.
73 * @param[out] mem_reg_address Base address of the memory range.
74 * @param[out] mem_reg_size Size of the memory range.
75 * @param[out] irq_no IRQ assigned to the device.
76 * @return Error code.
77 */
78int get_my_registers(const ddf_dev_t *dev,
79 uintptr_t *mem_reg_address, size_t *mem_reg_size, int *irq_no)
80{
81 assert(dev);
82
83 async_sess_t *parent_sess = devman_parent_device_connect(
84 EXCHANGE_SERIALIZE, dev->handle, IPC_FLAG_BLOCKING);
85 if (!parent_sess)
86 return ENOMEM;
87
88 hw_res_list_parsed_t hw_res;
89 hw_res_list_parsed_init(&hw_res);
90 const int ret = hw_res_get_list_parsed(parent_sess, &hw_res, 0);
91 async_hangup(parent_sess);
92 if (ret != EOK) {
93 return ret;
94 }
95
96 if (hw_res.irqs.count != 1 || hw_res.mem_ranges.count != 1) {
97 hw_res_list_parsed_clean(&hw_res);
98 return ENOENT;
99 }
100
101 if (mem_reg_address)
102 *mem_reg_address = hw_res.mem_ranges.ranges[0].address;
103 if (mem_reg_size)
104 *mem_reg_size = hw_res.mem_ranges.ranges[0].size;
105 if (irq_no)
106 *irq_no = hw_res.irqs.irqs[0];
107
108 hw_res_list_parsed_clean(&hw_res);
109 return EOK;
110}
111/*----------------------------------------------------------------------------*/
112/** Calls the PCI driver with a request to enable interrupts
113 *
114 * @param[in] device Device asking for interrupts
115 * @return Error code.
116 */
117int enable_interrupts(const ddf_dev_t *device)
118{
119 async_sess_t *parent_sess = devman_parent_device_connect(
120 EXCHANGE_SERIALIZE, device->handle, IPC_FLAG_BLOCKING);
121 if (!parent_sess)
122 return ENOMEM;
123
124 const bool enabled = hw_res_enable_interrupt(parent_sess);
125 async_hangup(parent_sess);
126
127 return enabled ? EOK : EIO;
128}
129/*----------------------------------------------------------------------------*/
130/** Implements BIOS handoff routine as decribed in EHCI spec
131 *
132 * @param[in] device Device asking for interrupts
133 * @return Error code.
134 */
135int disable_legacy(const ddf_dev_t *device, uintptr_t reg_base, size_t reg_size)
136{
137 assert(device);
138 async_sess_t *parent_sess = devman_parent_device_connect(
139 EXCHANGE_SERIALIZE, device->handle, IPC_FLAG_BLOCKING);
140 if (!parent_sess)
141 return ENOMEM;
142
143#define CHECK_RET_RETURN(ret, message...) \
144 if (ret != EOK) { \
145 usb_log_error(message); \
146 async_hangup(parent_sess); \
147 return ret; \
148 } else (void)0
149
150 /* Map EHCI registers */
151 void *regs = NULL;
152 int ret = pio_enable((void*)reg_base, reg_size, &regs);
153 CHECK_RET_RETURN(ret, "Failed to map registers %p: %s.\n",
154 (void *) reg_base, str_error(ret));
155
156 const uint32_t hcc_params =
157 *(uint32_t*)(regs + HCC_PARAMS_OFFSET);
158 usb_log_debug("Value of hcc params register: %x.\n", hcc_params);
159
160 /* Read value of EHCI Extended Capabilities Pointer
161 * position of EEC registers (points to PCI config space) */
162 const uint32_t eecp =
163 (hcc_params >> HCC_PARAMS_EECP_OFFSET) & HCC_PARAMS_EECP_MASK;
164 usb_log_debug("Value of EECP: %x.\n", eecp);
165
166 /* Read the first EEC. i.e. Legacy Support register */
167 uint32_t usblegsup;
168 ret = pci_config_space_read_32(parent_sess,
169 eecp + USBLEGSUP_OFFSET, &usblegsup);
170 CHECK_RET_RETURN(ret, "Failed to read USBLEGSUP: %s.\n", str_error(ret));
171 usb_log_debug("USBLEGSUP: %" PRIx32 ".\n", usblegsup);
172
173 /* Request control from firmware/BIOS, by writing 1 to highest byte.
174 * (OS Control semaphore)*/
175 usb_log_debug("Requesting OS control.\n");
176 ret = pci_config_space_write_8(parent_sess,
177 eecp + USBLEGSUP_OFFSET + 3, 1);
178 CHECK_RET_RETURN(ret, "Failed to request OS EHCI control: %s.\n",
179 str_error(ret));
180
181 size_t wait = 0;
182 /* Wait for BIOS to release control. */
183 ret = pci_config_space_read_32(parent_sess,
184 eecp + USBLEGSUP_OFFSET, &usblegsup);
185 while ((wait < DEFAULT_WAIT) && (usblegsup & USBLEGSUP_BIOS_CONTROL)) {
186 async_usleep(WAIT_STEP);
187 ret = pci_config_space_read_32(parent_sess,
188 eecp + USBLEGSUP_OFFSET, &usblegsup);
189 wait += WAIT_STEP;
190 }
191
192
193 if ((usblegsup & USBLEGSUP_BIOS_CONTROL) == 0) {
194 usb_log_info("BIOS released control after %zu usec.\n", wait);
195 } else {
196 /* BIOS failed to hand over control, this should not happen. */
197 usb_log_warning( "BIOS failed to release control after "
198 "%zu usecs, force it.\n", wait);
199 ret = pci_config_space_write_32(parent_sess,
200 eecp + USBLEGSUP_OFFSET, USBLEGSUP_OS_CONTROL);
201 CHECK_RET_RETURN(ret, "Failed to force OS control: %s.\n",
202 str_error(ret));
203 /* Check capability type here, A value of 01h
204 * identifies the capability as Legacy Support.
205 * This extended capability requires one
206 * additional 32-bit register for control/status information,
207 * and this register is located at offset EECP+04h
208 * */
209 if ((usblegsup & 0xff) == 1) {
210 /* Read the second EEC
211 * Legacy Support and Control register */
212 uint32_t usblegctlsts;
213 ret = pci_config_space_read_32(parent_sess,
214 eecp + USBLEGCTLSTS_OFFSET, &usblegctlsts);
215 CHECK_RET_RETURN(ret,
216 "Failed to get USBLEGCTLSTS: %s.\n", str_error(ret));
217 usb_log_debug("USBLEGCTLSTS: %" PRIx32 ".\n",
218 usblegctlsts);
219 /* Zero SMI enables in legacy control register.
220 * It should prevent pre-OS code from interfering.
221 * Three upper bits are WC */
222 ret = pci_config_space_write_32(parent_sess,
223 eecp + USBLEGCTLSTS_OFFSET, 0xe0000000);
224 CHECK_RET_RETURN(ret,
225 "Failed(%d) zero USBLEGCTLSTS.\n", ret);
226 udelay(10);
227 ret = pci_config_space_read_32(parent_sess,
228 eecp + USBLEGCTLSTS_OFFSET, &usblegctlsts);
229 CHECK_RET_RETURN(ret,
230 "Failed to get USBLEGCTLSTS 2: %s.\n",
231 str_error(ret));
232 usb_log_debug("Zeroed USBLEGCTLSTS: %" PRIx32 ".\n",
233 usblegctlsts);
234 }
235 }
236
237
238 /* Read again Legacy Support register */
239 ret = pci_config_space_read_32(parent_sess,
240 eecp + USBLEGSUP_OFFSET, &usblegsup);
241 CHECK_RET_RETURN(ret, "Failed to read USBLEGSUP: %s.\n", str_error(ret));
242 usb_log_debug("USBLEGSUP: %" PRIx32 ".\n", usblegsup);
243
244 async_hangup(parent_sess);
245#undef CHECK_RET_RETURN
246
247 /*
248 * TURN OFF EHCI FOR NOW, DRIVER WILL REINITIALIZE IT IF NEEDED
249 */
250
251 /* Get size of capability registers in memory space. */
252 const unsigned operation_offset = *(uint8_t*)regs;
253 usb_log_debug("USBCMD offset: %d.\n", operation_offset);
254
255 /* Zero USBCMD register. */
256 volatile uint32_t *usbcmd =
257 (uint32_t*)((uint8_t*)regs + operation_offset + CMD_OFFSET);
258 volatile uint32_t *usbsts =
259 (uint32_t*)((uint8_t*)regs + operation_offset + STS_OFFSET);
260 volatile uint32_t *usbconf =
261 (uint32_t*)((uint8_t*)regs + operation_offset + CFG_OFFSET);
262 volatile uint32_t *usbint =
263 (uint32_t*)((uint8_t*)regs + operation_offset + INT_OFFSET);
264 usb_log_debug("USBCMD value: %x.\n", *usbcmd);
265 if (*usbcmd & USBCMD_RUN) {
266 *usbsts = 0x3f; /* ack all interrupts */
267 *usbint = 0; /* disable all interrutps */
268 *usbconf = 0; /* relase control of RH ports */
269
270 *usbcmd = 0;
271 /* Wait until hc is halted */
272 while ((*usbsts & USBSTS_HALTED) == 0);
273 usb_log_info("EHCI turned off.\n");
274 } else {
275 usb_log_info("EHCI was not running.\n");
276 }
277 usb_log_debug("Registers: \n"
278 "\t USBCMD: %x(0x00080000 = at least 1ms between interrupts)\n"
279 "\t USBSTS: %x(0x00001000 = HC halted)\n"
280 "\t USBINT: %x(0x0 = no interrupts).\n"
281 "\t CONFIG: %x(0x0 = ports controlled by companion hc).\n",
282 *usbcmd, *usbsts, *usbint, *usbconf);
283
284 return ret;
285}
286
287/**
288 * @}
289 */
Note: See TracBrowser for help on using the repository browser.