source: mainline/uspace/drv/bus/usb/ehci/res.c@ 224174f

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 224174f was d930980, checked in by Jiri Svoboda <jiri@…>, 12 years ago

Eliminate remaning CHECK_RETxxx macros.
  • Property mode set to 100644
File size: 10.0 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/**
30 * @addtogroup drvusbehci
31 * @{
32 */
33/**
34 * @file
35 * PCI related functions needed by the EHCI driver.
36 */
37
38#include <errno.h>
39#include <str_error.h>
40#include <assert.h>
41#include <devman.h>
42#include <ddi.h>
43#include <usb/debug.h>
44#include <device/hw_res_parsed.h>
45#include <device/pci.h>
46
47#include "res.h"
48
49#define HCC_PARAMS_OFFSET 0x8
50#define HCC_PARAMS_EECP_MASK 0xff
51#define HCC_PARAMS_EECP_OFFSET 8
52
53#define CMD_OFFSET 0x0
54#define STS_OFFSET 0x4
55#define INT_OFFSET 0x8
56#define CFG_OFFSET 0x40
57
58#define USBCMD_RUN 1
59#define USBSTS_HALTED (1 << 12)
60
61#define USBLEGSUP_OFFSET 0
62#define USBLEGSUP_BIOS_CONTROL (1 << 16)
63#define USBLEGSUP_OS_CONTROL (1 << 24)
64#define USBLEGCTLSTS_OFFSET 4
65
66#define DEFAULT_WAIT 1000
67#define WAIT_STEP 10
68
69
70/** Get address of registers and IRQ for given device.
71 *
72 * @param[in] dev Device asking for the addresses.
73 * @param[out] mem_reg_address Base address of the memory range.
74 * @param[out] mem_reg_size Size of the memory range.
75 * @param[out] irq_no IRQ assigned to the device.
76 * @return Error code.
77 */
78int get_my_registers(ddf_dev_t *dev,
79 uintptr_t *mem_reg_address, size_t *mem_reg_size, int *irq_no)
80{
81 assert(dev);
82
83 async_sess_t *parent_sess = devman_parent_device_connect(
84 EXCHANGE_SERIALIZE, ddf_dev_get_handle(dev), IPC_FLAG_BLOCKING);
85 if (!parent_sess)
86 return ENOMEM;
87
88 hw_res_list_parsed_t hw_res;
89 hw_res_list_parsed_init(&hw_res);
90 const int ret = hw_res_get_list_parsed(parent_sess, &hw_res, 0);
91 async_hangup(parent_sess);
92 if (ret != EOK) {
93 return ret;
94 }
95
96 if (hw_res.irqs.count != 1 || hw_res.mem_ranges.count != 1) {
97 hw_res_list_parsed_clean(&hw_res);
98 return ENOENT;
99 }
100
101 if (mem_reg_address)
102 *mem_reg_address = hw_res.mem_ranges.ranges[0].address;
103 if (mem_reg_size)
104 *mem_reg_size = hw_res.mem_ranges.ranges[0].size;
105 if (irq_no)
106 *irq_no = hw_res.irqs.irqs[0];
107
108 hw_res_list_parsed_clean(&hw_res);
109 return EOK;
110}
111
112/** Calls the PCI driver with a request to enable interrupts
113 *
114 * @param[in] device Device asking for interrupts
115 * @return Error code.
116 */
117int enable_interrupts(ddf_dev_t *device)
118{
119 async_sess_t *parent_sess = devman_parent_device_connect(
120 EXCHANGE_SERIALIZE, ddf_dev_get_handle(device), IPC_FLAG_BLOCKING);
121 if (!parent_sess)
122 return ENOMEM;
123
124 const bool enabled = hw_res_enable_interrupt(parent_sess);
125 async_hangup(parent_sess);
126
127 return enabled ? EOK : EIO;
128}
129
130/** Implements BIOS hands-off routine as described in EHCI spec
131 *
132 * @param device EHCI device
133 * @param eecp Value of EHCI Extended Capabilities pointer.
134 * @return Error code.
135 */
136static int disable_extended_caps(ddf_dev_t *device, unsigned eecp)
137{
138 /* nothing to do */
139 if (eecp == 0)
140 return EOK;
141
142 async_sess_t *parent_sess = devman_parent_device_connect(
143 EXCHANGE_SERIALIZE, ddf_dev_get_handle(device), IPC_FLAG_BLOCKING);
144 if (!parent_sess)
145 return ENOMEM;
146
147 /* Read the first EEC. i.e. Legacy Support register */
148 uint32_t usblegsup;
149 int rc = pci_config_space_read_32(parent_sess,
150 eecp + USBLEGSUP_OFFSET, &usblegsup);
151 if (rc != EOK) {
152 usb_log_error("Failed to read USBLEGSUP: %s.\n",
153 str_error(rc));
154 goto error;
155 }
156
157 usb_log_debug("USBLEGSUP: %" PRIx32 ".\n", usblegsup);
158
159 /* Request control from firmware/BIOS by writing 1 to highest
160 * byte. (OS Control semaphore)*/
161 usb_log_debug("Requesting OS control.\n");
162 rc = pci_config_space_write_8(parent_sess,
163 eecp + USBLEGSUP_OFFSET + 3, 1);
164 if (rc != EOK) {
165 usb_log_error("Failed to request OS EHCI control: %s.\n",
166 str_error(rc));
167 goto error;
168 }
169
170 size_t wait = 0;
171 /* Wait for BIOS to release control. */
172 rc = pci_config_space_read_32(
173 parent_sess, eecp + USBLEGSUP_OFFSET, &usblegsup);
174 if (rc != EOK) {
175 usb_log_error("Failed reading PCI config space: %s.\n",
176 str_error(rc));
177 goto error;
178 }
179
180 while ((wait < DEFAULT_WAIT) && (usblegsup & USBLEGSUP_BIOS_CONTROL)) {
181 async_usleep(WAIT_STEP);
182 rc = pci_config_space_read_32(parent_sess,
183 eecp + USBLEGSUP_OFFSET, &usblegsup);
184 if (rc != EOK) {
185 usb_log_error("Failed reading PCI config space: %s.\n",
186 str_error(rc));
187 goto error;
188 }
189 wait += WAIT_STEP;
190 }
191
192 if ((usblegsup & USBLEGSUP_BIOS_CONTROL) == 0) {
193 usb_log_info("BIOS released control after %zu usec.\n", wait);
194 async_hangup(parent_sess);
195 return EOK;
196 }
197
198 /* BIOS failed to hand over control, this should not happen. */
199 usb_log_warning( "BIOS failed to release control after "
200 "%zu usecs, force it.\n", wait);
201 rc = pci_config_space_write_32(parent_sess,
202 eecp + USBLEGSUP_OFFSET, USBLEGSUP_OS_CONTROL);
203 if (rc != EOK) {
204 usb_log_error("Failed to force OS control: "
205 "%s.\n", str_error(rc));
206 goto error;
207 }
208
209 /*
210 * Check capability type here, value of 01h identifies the capability
211 * as Legacy Support. This extended capability requires one additional
212 * 32-bit register for control/status information and this register is
213 * located at offset EECP+04h
214 */
215 if ((usblegsup & 0xff) == 1) {
216 /* Read the second EEC Legacy Support and Control register */
217 uint32_t usblegctlsts;
218 rc = pci_config_space_read_32(parent_sess,
219 eecp + USBLEGCTLSTS_OFFSET, &usblegctlsts);
220 if (rc != EOK) {
221 usb_log_error("Failed to get USBLEGCTLSTS: %s.\n",
222 str_error(rc));
223 goto error;
224 }
225
226 usb_log_debug("USBLEGCTLSTS: %" PRIx32 ".\n", usblegctlsts);
227 /*
228 * Zero SMI enables in legacy control register.
229 * It should prevent pre-OS code from
230 * interfering. NOTE: Three upper bits are WC
231 */
232 rc = pci_config_space_write_32(parent_sess,
233 eecp + USBLEGCTLSTS_OFFSET, 0xe0000000);
234 if (rc != EOK) {
235 usb_log_error("Failed(%d) zero USBLEGCTLSTS.\n", rc);
236 goto error;
237 }
238
239 udelay(10);
240 rc = pci_config_space_read_32(parent_sess,
241 eecp + USBLEGCTLSTS_OFFSET, &usblegctlsts);
242 if (rc != EOK) {
243 usb_log_error("Failed to get USBLEGCTLSTS 2: %s.\n",
244 str_error(rc));
245 goto error;
246 }
247
248 usb_log_debug("Zeroed USBLEGCTLSTS: %" PRIx32 ".\n",
249 usblegctlsts);
250 }
251
252 /* Read again Legacy Support register */
253 rc = pci_config_space_read_32(parent_sess,
254 eecp + USBLEGSUP_OFFSET, &usblegsup);
255 if (rc != EOK) {
256 usb_log_error("Failed to read USBLEGSUP: %s.\n",
257 str_error(rc));
258 goto error;
259 }
260
261 usb_log_debug("USBLEGSUP: %" PRIx32 ".\n", usblegsup);
262 async_hangup(parent_sess);
263 return EOK;
264error:
265 async_hangup(parent_sess);
266 return rc;
267}
268
269int disable_legacy(ddf_dev_t *device, uintptr_t reg_base, size_t reg_size)
270{
271 assert(device);
272 usb_log_debug("Disabling EHCI legacy support.\n");
273
274 /* Map EHCI registers */
275 void *regs = NULL;
276 int rc = pio_enable((void*)reg_base, reg_size, &regs);
277 if (rc != EOK) {
278 usb_log_error("Failed to map registers %p: %s.\n",
279 (void *) reg_base, str_error(rc));
280 return rc;
281 }
282
283 usb_log_debug2("Registers mapped at: %p.\n", regs);
284
285 const uint32_t hcc_params =
286 *(uint32_t*)(regs + HCC_PARAMS_OFFSET);
287 usb_log_debug("Value of hcc params register: %x.\n", hcc_params);
288
289 /* Read value of EHCI Extended Capabilities Pointer
290 * position of EEC registers (points to PCI config space) */
291 const uint32_t eecp =
292 (hcc_params >> HCC_PARAMS_EECP_OFFSET) & HCC_PARAMS_EECP_MASK;
293 usb_log_debug("Value of EECP: %x.\n", eecp);
294
295 rc = disable_extended_caps(device, eecp);
296 if (rc != EOK) {
297 usb_log_error("Failed to disable extended capabilities: %s.\n",
298 str_error(rc));
299 return rc;
300 }
301
302 /*
303 * TURN OFF EHCI FOR NOW, DRIVER WILL REINITIALIZE IT IF NEEDED
304 */
305
306 /* Get size of capability registers in memory space. */
307 const unsigned operation_offset = *(uint8_t*)regs;
308 usb_log_debug("USBCMD offset: %d.\n", operation_offset);
309
310 /* Zero USBCMD register. */
311 volatile uint32_t *usbcmd =
312 (uint32_t*)((uint8_t*)regs + operation_offset + CMD_OFFSET);
313 volatile uint32_t *usbsts =
314 (uint32_t*)((uint8_t*)regs + operation_offset + STS_OFFSET);
315 volatile uint32_t *usbconf =
316 (uint32_t*)((uint8_t*)regs + operation_offset + CFG_OFFSET);
317 volatile uint32_t *usbint =
318 (uint32_t*)((uint8_t*)regs + operation_offset + INT_OFFSET);
319 usb_log_debug("USBCMD value: %x.\n", *usbcmd);
320 if (*usbcmd & USBCMD_RUN) {
321 *usbsts = 0x3f; /* ack all interrupts */
322 *usbint = 0; /* disable all interrupts */
323 *usbconf = 0; /* release control of RH ports */
324
325 *usbcmd = 0;
326 /* Wait until hc is halted */
327 while ((*usbsts & USBSTS_HALTED) == 0);
328 usb_log_info("EHCI turned off.\n");
329 } else {
330 usb_log_info("EHCI was not running.\n");
331 }
332 usb_log_debug("Registers: \n"
333 "\t USBCMD(%p): %x(0x00080000 = at least 1ms between interrupts)\n"
334 "\t USBSTS(%p): %x(0x00001000 = HC halted)\n"
335 "\t USBINT(%p): %x(0x0 = no interrupts).\n"
336 "\t CONFIG(%p): %x(0x0 = ports controlled by companion hc).\n",
337 usbcmd, *usbcmd, usbsts, *usbsts, usbint, *usbint, usbconf,*usbconf);
338
339 return rc;
340}
341
342/**
343 * @}
344 */
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