source: mainline/uspace/drv/bus/usb/ehci/res.c@ 0dd16778

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 0dd16778 was 99e8fb7b, checked in by Jan Vesely <jano.vesely@…>, 12 years ago

libdrv: Move pci_config client side to libdrv

Remove duplicate includes, duplicate enum definitions, …
  • Property mode set to 100644
File size: 9.8 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/**
30 * @addtogroup drvusbehci
31 * @{
32 */
33/**
34 * @file
35 * PCI related functions needed by the EHCI driver.
36 */
37
38#include <errno.h>
39#include <str_error.h>
40#include <assert.h>
41#include <devman.h>
42#include <ddi.h>
43#include <usb/debug.h>
44#include <device/hw_res_parsed.h>
45#include <pci_dev_iface.h>
46
47#include "res.h"
48
49#define HCC_PARAMS_OFFSET 0x8
50#define HCC_PARAMS_EECP_MASK 0xff
51#define HCC_PARAMS_EECP_OFFSET 8
52
53#define CMD_OFFSET 0x0
54#define STS_OFFSET 0x4
55#define INT_OFFSET 0x8
56#define CFG_OFFSET 0x40
57
58#define USBCMD_RUN 1
59#define USBSTS_HALTED (1 << 12)
60
61#define USBLEGSUP_OFFSET 0
62#define USBLEGSUP_BIOS_CONTROL (1 << 16)
63#define USBLEGSUP_OS_CONTROL (1 << 24)
64#define USBLEGCTLSTS_OFFSET 4
65
66#define DEFAULT_WAIT 1000
67#define WAIT_STEP 10
68
69
70/** Get address of registers and IRQ for given device.
71 *
72 * @param[in] dev Device asking for the addresses.
73 * @param[out] mem_regs_p Pointer to the register range.
74 * @param[out] irq_no IRQ assigned to the device.
75 * @return Error code.
76 */
77int get_my_registers(ddf_dev_t *dev,
78 addr_range_t *mem_regs_p, int *irq_no)
79{
80 assert(dev);
81
82 async_sess_t *parent_sess = devman_parent_device_connect(
83 EXCHANGE_SERIALIZE, ddf_dev_get_handle(dev), IPC_FLAG_BLOCKING);
84 if (!parent_sess)
85 return ENOMEM;
86
87 hw_res_list_parsed_t hw_res;
88 hw_res_list_parsed_init(&hw_res);
89 const int ret = hw_res_get_list_parsed(parent_sess, &hw_res, 0);
90 async_hangup(parent_sess);
91 if (ret != EOK) {
92 return ret;
93 }
94
95 if (hw_res.irqs.count != 1 || hw_res.mem_ranges.count != 1) {
96 hw_res_list_parsed_clean(&hw_res);
97 return ENOENT;
98 }
99
100 if (mem_regs_p)
101 *mem_regs_p = hw_res.mem_ranges.ranges[0];
102 if (irq_no)
103 *irq_no = hw_res.irqs.irqs[0];
104
105 hw_res_list_parsed_clean(&hw_res);
106 return EOK;
107}
108
109/** Calls the PCI driver with a request to enable interrupts
110 *
111 * @param[in] device Device asking for interrupts
112 * @return Error code.
113 */
114int enable_interrupts(ddf_dev_t *device)
115{
116 async_sess_t *parent_sess = devman_parent_device_connect(
117 EXCHANGE_SERIALIZE, ddf_dev_get_handle(device), IPC_FLAG_BLOCKING);
118 if (!parent_sess)
119 return ENOMEM;
120
121 const bool enabled = hw_res_enable_interrupt(parent_sess);
122 async_hangup(parent_sess);
123
124 return enabled ? EOK : EIO;
125}
126
127/** Implements BIOS hands-off routine as described in EHCI spec
128 *
129 * @param device EHCI device
130 * @param eecp Value of EHCI Extended Capabilities pointer.
131 * @return Error code.
132 */
133static int disable_extended_caps(ddf_dev_t *device, unsigned eecp)
134{
135 /* nothing to do */
136 if (eecp == 0)
137 return EOK;
138
139 async_sess_t *parent_sess = devman_parent_device_connect(
140 EXCHANGE_SERIALIZE, ddf_dev_get_handle(device), IPC_FLAG_BLOCKING);
141 if (!parent_sess)
142 return ENOMEM;
143
144 /* Read the first EEC. i.e. Legacy Support register */
145 uint32_t usblegsup;
146 int rc = pci_config_space_read_32(parent_sess,
147 eecp + USBLEGSUP_OFFSET, &usblegsup);
148 if (rc != EOK) {
149 usb_log_error("Failed to read USBLEGSUP: %s.\n",
150 str_error(rc));
151 goto error;
152 }
153
154 usb_log_debug("USBLEGSUP: %" PRIx32 ".\n", usblegsup);
155
156 /* Request control from firmware/BIOS by writing 1 to highest
157 * byte. (OS Control semaphore)*/
158 usb_log_debug("Requesting OS control.\n");
159 rc = pci_config_space_write_8(parent_sess,
160 eecp + USBLEGSUP_OFFSET + 3, 1);
161 if (rc != EOK) {
162 usb_log_error("Failed to request OS EHCI control: %s.\n",
163 str_error(rc));
164 goto error;
165 }
166
167 size_t wait = 0;
168 /* Wait for BIOS to release control. */
169 rc = pci_config_space_read_32(
170 parent_sess, eecp + USBLEGSUP_OFFSET, &usblegsup);
171 if (rc != EOK) {
172 usb_log_error("Failed reading PCI config space: %s.\n",
173 str_error(rc));
174 goto error;
175 }
176
177 while ((wait < DEFAULT_WAIT) && (usblegsup & USBLEGSUP_BIOS_CONTROL)) {
178 async_usleep(WAIT_STEP);
179 rc = pci_config_space_read_32(parent_sess,
180 eecp + USBLEGSUP_OFFSET, &usblegsup);
181 if (rc != EOK) {
182 usb_log_error("Failed reading PCI config space: %s.\n",
183 str_error(rc));
184 goto error;
185 }
186 wait += WAIT_STEP;
187 }
188
189 if ((usblegsup & USBLEGSUP_BIOS_CONTROL) == 0) {
190 usb_log_info("BIOS released control after %zu usec.\n", wait);
191 async_hangup(parent_sess);
192 return EOK;
193 }
194
195 /* BIOS failed to hand over control, this should not happen. */
196 usb_log_warning( "BIOS failed to release control after "
197 "%zu usecs, force it.\n", wait);
198 rc = pci_config_space_write_32(parent_sess,
199 eecp + USBLEGSUP_OFFSET, USBLEGSUP_OS_CONTROL);
200 if (rc != EOK) {
201 usb_log_error("Failed to force OS control: "
202 "%s.\n", str_error(rc));
203 goto error;
204 }
205
206 /*
207 * Check capability type here, value of 01h identifies the capability
208 * as Legacy Support. This extended capability requires one additional
209 * 32-bit register for control/status information and this register is
210 * located at offset EECP+04h
211 */
212 if ((usblegsup & 0xff) == 1) {
213 /* Read the second EEC Legacy Support and Control register */
214 uint32_t usblegctlsts;
215 rc = pci_config_space_read_32(parent_sess,
216 eecp + USBLEGCTLSTS_OFFSET, &usblegctlsts);
217 if (rc != EOK) {
218 usb_log_error("Failed to get USBLEGCTLSTS: %s.\n",
219 str_error(rc));
220 goto error;
221 }
222
223 usb_log_debug("USBLEGCTLSTS: %" PRIx32 ".\n", usblegctlsts);
224 /*
225 * Zero SMI enables in legacy control register.
226 * It should prevent pre-OS code from
227 * interfering. NOTE: Three upper bits are WC
228 */
229 rc = pci_config_space_write_32(parent_sess,
230 eecp + USBLEGCTLSTS_OFFSET, 0xe0000000);
231 if (rc != EOK) {
232 usb_log_error("Failed(%d) zero USBLEGCTLSTS.\n", rc);
233 goto error;
234 }
235
236 udelay(10);
237 rc = pci_config_space_read_32(parent_sess,
238 eecp + USBLEGCTLSTS_OFFSET, &usblegctlsts);
239 if (rc != EOK) {
240 usb_log_error("Failed to get USBLEGCTLSTS 2: %s.\n",
241 str_error(rc));
242 goto error;
243 }
244
245 usb_log_debug("Zeroed USBLEGCTLSTS: %" PRIx32 ".\n",
246 usblegctlsts);
247 }
248
249 /* Read again Legacy Support register */
250 rc = pci_config_space_read_32(parent_sess,
251 eecp + USBLEGSUP_OFFSET, &usblegsup);
252 if (rc != EOK) {
253 usb_log_error("Failed to read USBLEGSUP: %s.\n",
254 str_error(rc));
255 goto error;
256 }
257
258 usb_log_debug("USBLEGSUP: %" PRIx32 ".\n", usblegsup);
259 async_hangup(parent_sess);
260 return EOK;
261error:
262 async_hangup(parent_sess);
263 return rc;
264}
265
266int disable_legacy(ddf_dev_t *device, addr_range_t *reg_range)
267{
268 assert(device);
269 usb_log_debug("Disabling EHCI legacy support.\n");
270
271 /* Map EHCI registers */
272 void *regs = NULL;
273 int rc = pio_enable_range(reg_range, &regs);
274 if (rc != EOK) {
275 usb_log_error("Failed to map registers %p: %s.\n",
276 RNGABSPTR(*reg_range), str_error(rc));
277 return rc;
278 }
279
280 usb_log_debug2("Registers mapped at: %p.\n", regs);
281
282 const uint32_t hcc_params =
283 *(uint32_t*)(regs + HCC_PARAMS_OFFSET);
284 usb_log_debug("Value of hcc params register: %x.\n", hcc_params);
285
286 /* Read value of EHCI Extended Capabilities Pointer
287 * position of EEC registers (points to PCI config space) */
288 const uint32_t eecp =
289 (hcc_params >> HCC_PARAMS_EECP_OFFSET) & HCC_PARAMS_EECP_MASK;
290 usb_log_debug("Value of EECP: %x.\n", eecp);
291
292 rc = disable_extended_caps(device, eecp);
293 if (rc != EOK) {
294 usb_log_error("Failed to disable extended capabilities: %s.\n",
295 str_error(rc));
296 return rc;
297 }
298
299 /*
300 * TURN OFF EHCI FOR NOW, DRIVER WILL REINITIALIZE IT IF NEEDED
301 */
302
303 /* Get size of capability registers in memory space. */
304 const unsigned operation_offset = *(uint8_t*)regs;
305 usb_log_debug("USBCMD offset: %d.\n", operation_offset);
306
307 /* Zero USBCMD register. */
308 volatile uint32_t *usbcmd =
309 (uint32_t*)((uint8_t*)regs + operation_offset + CMD_OFFSET);
310 volatile uint32_t *usbsts =
311 (uint32_t*)((uint8_t*)regs + operation_offset + STS_OFFSET);
312 volatile uint32_t *usbconf =
313 (uint32_t*)((uint8_t*)regs + operation_offset + CFG_OFFSET);
314 volatile uint32_t *usbint =
315 (uint32_t*)((uint8_t*)regs + operation_offset + INT_OFFSET);
316 usb_log_debug("USBCMD value: %x.\n", *usbcmd);
317 if (*usbcmd & USBCMD_RUN) {
318 *usbsts = 0x3f; /* ack all interrupts */
319 *usbint = 0; /* disable all interrupts */
320 *usbconf = 0; /* release control of RH ports */
321
322 *usbcmd = 0;
323 /* Wait until hc is halted */
324 while ((*usbsts & USBSTS_HALTED) == 0);
325 usb_log_info("EHCI turned off.\n");
326 } else {
327 usb_log_info("EHCI was not running.\n");
328 }
329 usb_log_debug("Registers: \n"
330 "\t USBCMD(%p): %x(0x00080000 = at least 1ms between interrupts)\n"
331 "\t USBSTS(%p): %x(0x00001000 = HC halted)\n"
332 "\t USBINT(%p): %x(0x0 = no interrupts).\n"
333 "\t CONFIG(%p): %x(0x0 = ports controlled by companion hc).\n",
334 usbcmd, *usbcmd, usbsts, *usbsts, usbint, *usbint, usbconf,*usbconf);
335
336 return rc;
337}
338
339/**
340 * @}
341 */
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