source: mainline/uspace/drv/bus/usb/ehci/hw_struct/queue_head.c@ 3d8a3bd

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 3d8a3bd was 708da59e, checked in by Jan Vesely <jano.vesely@…>, 10 years ago

ehci, qh: Refactor QH initialization

  • Property mode set to 100644
File size: 3.4 KB
Line 
1/*
2 * Copyright (c) 2013 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbehci
29 * @{
30 */
31/** @file
32 * @brief EHCI driver
33 */
34
35#include <assert.h>
36#include <usb/usb.h>
37#include <mem.h>
38#include <macros.h>
39
40#include "mem_access.h"
41#include "queue_head.h"
42
43static const uint32_t speed[] = {
44 [USB_SPEED_LOW] = QH_EP_CHAR_EPS_LS,
45 [USB_SPEED_FULL] = QH_EP_CHAR_EPS_FS,
46 [USB_SPEED_HIGH] = QH_EP_CHAR_EPS_HS,
47};
48
49void qh_init(qh_t *instance, const endpoint_t *ep)
50{
51 assert(instance);
52 memset(instance, 0, sizeof(*instance));
53
54 EHCI_MEM32_WR(instance->horizontal, LINK_POINTER_TERM);
55// EHCI_MEM32_WR(instance->current, LINK_POINTER_TERM);
56 EHCI_MEM32_WR(instance->next, LINK_POINTER_TERM);
57 EHCI_MEM32_WR(instance->alternate, LINK_POINTER_TERM);
58 if (ep == NULL) {
59 /* Mark as halted and list head,
60 * used by endpoint lists as dummy */
61 EHCI_MEM32_WR(instance->ep_char, QH_EP_CHAR_H_FLAG);
62 EHCI_MEM32_WR(instance->status, QH_STATUS_HALTED_FLAG);
63 return;
64 }
65 assert(ep->speed < ARRAY_SIZE(speed));
66 EHCI_MEM32_WR(instance->ep_char,
67 QH_EP_CHAR_ADDR_SET(ep->address) |
68 QH_EP_CHAR_EP_SET(ep->endpoint) |
69 speed[ep->speed] |
70 QH_EP_CHAR_MAX_LENGTH_SET(ep->max_packet_size)
71 );
72 if (ep->transfer_type == USB_TRANSFER_CONTROL) {
73 if (ep->speed != USB_SPEED_HIGH)
74 EHCI_MEM32_SET(instance->ep_char, QH_EP_CHAR_C_FLAG);
75 /* Let BULK and INT use queue head managed toggle,
76 * CONTROL needs special toggle handling anyway */
77 EHCI_MEM32_SET(instance->ep_char, QH_EP_CHAR_DTC_FLAG);
78 }
79 uint32_t ep_cap = QH_EP_CAP_C_MASK_SET(3 << 2) |
80 QH_EP_CAP_MULTI_SET(ep->packets);
81 if (ep->speed != USB_SPEED_HIGH) {
82 ep_cap |=
83 QH_EP_CAP_TT_PORT_SET(ep->tt.port) |
84 QH_EP_CAP_TT_ADDR_SET(ep->tt.address);
85 }
86 if (ep->transfer_type == USB_TRANSFER_INTERRUPT) {
87 ep_cap |= QH_EP_CAP_S_MASK_SET(3);
88 }
89
90 // TODO Figure out how to correctly use CMASK and SMASK for LS/FS
91 // INT transfers. Current values are just guesses
92 EHCI_MEM32_WR(instance->ep_cap, ep_cap);
93
94 /* The rest of the fields are transfer working area, it should be ok to
95 * leave it NULL */
96}
97
98/**
99 * @}
100 */
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