source: mainline/uspace/drv/bus/usb/ehci/hc.c@ fdaaad00

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since fdaaad00 was fdaaad00, checked in by Jan Vesely <jano.vesely@…>, 12 years ago

ehci: Make async schedule a loop.

Hw RR mechanism needs this.
  • Property mode set to 100644
File size: 12.2 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbehcihc
30 * @{
31 */
32/** @file
33 * @brief EHCI Host controller driver routines
34 */
35
36#include <assert.h>
37#include <async.h>
38#include <errno.h>
39#include <macros.h>
40#include <mem.h>
41#include <stdlib.h>
42#include <str_error.h>
43#include <sys/types.h>
44
45#include <usb/debug.h>
46#include <usb/usb.h>
47
48//#include "ehci_endpoint.h"
49//#include "ehci_batch.h"
50#include "utils/malloc32.h"
51
52#include "hc.h"
53
54#define EHCI_USED_INTERRUPTS \
55 (USB_INTR_IRQ_FLAG | USB_INTR_ERR_IRQ_FLAG | USB_INTR_PORT_CHANGE_FLAG)
56
57static const irq_pio_range_t ehci_pio_ranges[] = {
58 {
59 .base = 0,
60 .size = sizeof(ehci_regs_t)
61 }
62};
63
64static const irq_cmd_t ehci_irq_commands[] = {
65 {
66 .cmd = CMD_PIO_READ_32,
67 .dstarg = 1,
68 .addr = NULL
69 },
70 {
71 .cmd = CMD_AND,
72 .srcarg = 1,
73 .dstarg = 2,
74 .value = 0
75 },
76 {
77 .cmd = CMD_PREDICATE,
78 .srcarg = 2,
79 .value = 2
80 },
81 {
82 .cmd = CMD_PIO_WRITE_A_32,
83 .srcarg = 1,
84 .addr = NULL
85 },
86 {
87 .cmd = CMD_ACCEPT
88 }
89};
90
91static void hc_start(hc_t *instance);
92static int hc_init_memory(hc_t *instance);
93
94/** Generate IRQ code.
95 * @param[out] ranges PIO ranges buffer.
96 * @param[in] hw_res Device's resources.
97 *
98 * @return Error code.
99 */
100int ehci_hc_gen_irq_code(irq_code_t *code, const hw_res_list_parsed_t *hw_res)
101{
102 assert(code);
103 assert(hw_res);
104
105 if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
106 return EINVAL;
107
108 addr_range_t regs = hw_res->mem_ranges.ranges[0];
109
110 if (RNGSZ(regs) < sizeof(ehci_regs_t))
111 return EOVERFLOW;
112
113 code->ranges = malloc(sizeof(ehci_pio_ranges));
114 if (code->ranges == NULL)
115 return ENOMEM;
116
117 code->cmds = malloc(sizeof(ehci_irq_commands));
118 if (code->cmds == NULL) {
119 free(code->ranges);
120 return ENOMEM;
121 }
122
123 code->rangecount = ARRAY_SIZE(ehci_pio_ranges);
124 code->cmdcount = ARRAY_SIZE(ehci_irq_commands);
125
126 memcpy(code->ranges, ehci_pio_ranges, sizeof(ehci_pio_ranges));
127 code->ranges[0].base = RNGABS(regs);
128
129 memcpy(code->cmds, ehci_irq_commands, sizeof(ehci_irq_commands));
130 ehci_caps_regs_t *caps = NULL;
131 int ret = pio_enable_range(&regs, (void**)&caps);
132 if (ret != EOK) {
133 return ret;
134 }
135 ehci_regs_t *registers =
136 (ehci_regs_t *)(RNGABSPTR(regs) + EHCI_RD8(caps->caplength));
137 code->cmds[0].addr = (void *) &registers->usbsts;
138 code->cmds[3].addr = (void *) &registers->usbsts;
139 EHCI_WR(code->cmds[1].value, EHCI_USED_INTERRUPTS);
140
141 usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.\n",
142 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
143
144 return hw_res->irqs.irqs[0];
145}
146
147/** Initialize EHCI hc driver structure
148 *
149 * @param[in] instance Memory place for the structure.
150 * @param[in] regs Device's I/O registers range.
151 * @param[in] interrupts True if w interrupts should be used
152 * @return Error code
153 */
154int hc_init(hc_t *instance, const hw_res_list_parsed_t *hw_res, bool interrupts)
155{
156 assert(instance);
157 assert(hw_res);
158 if (hw_res->mem_ranges.count != 1 ||
159 hw_res->mem_ranges.ranges[0].size <
160 (sizeof(ehci_caps_regs_t) + sizeof(ehci_regs_t)))
161 return EINVAL;
162
163 int ret = pio_enable_range(&hw_res->mem_ranges.ranges[0],
164 (void **)&instance->caps);
165 if (ret != EOK) {
166 usb_log_error("Failed to gain access to device registers: %s.\n",
167 str_error(ret));
168 return ret;
169 }
170 usb_log_debug("Device registers at %" PRIx64 " (%zuB) accessible.\n",
171 hw_res->mem_ranges.ranges[0].address.absolute,
172 hw_res->mem_ranges.ranges[0].size);
173 instance->registers =
174 (void*)instance->caps + EHCI_RD8(instance->caps->caplength);
175
176 list_initialize(&instance->pending_batches);
177 fibril_mutex_initialize(&instance->guard);
178 fibril_condvar_initialize(&instance->async_doorbell);
179
180 ret = hc_init_memory(instance);
181 if (ret != EOK) {
182 usb_log_error("Failed to create EHCI memory structures: %s.\n",
183 str_error(ret));
184 return ret;
185 }
186
187 ehci_rh_init(
188 &instance->rh, instance->caps, instance->registers, "ehci rh");
189 hc_start(instance);
190
191 return EOK;
192}
193
194/** Safely dispose host controller internal structures
195 *
196 * @param[in] instance Host controller structure to use.
197 */
198void hc_fini(hc_t *instance)
199{
200 assert(instance);
201 //TODO: stop the hw
202#if 0
203 endpoint_list_fini(&instance->async_list);
204 endpoint_list_fini(&instance->int_list);
205 return_page(instance->periodic_list_base);
206#endif
207};
208
209void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
210{
211 assert(instance);
212 assert(ep);
213 ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
214 switch (ep->transfer_type)
215 {
216 case USB_TRANSFER_CONTROL:
217 case USB_TRANSFER_BULK:
218 endpoint_list_append_ep(&instance->async_list, ehci_ep);
219 break;
220 case USB_TRANSFER_INTERRUPT:
221 endpoint_list_append_ep(&instance->int_list, ehci_ep);
222 break;
223 case USB_TRANSFER_ISOCHRONOUS:
224 /* NOT SUPPORTED */
225 break;
226 }
227}
228
229void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
230{
231 assert(instance);
232 assert(ep);
233 ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
234 switch (ep->transfer_type)
235 {
236 case USB_TRANSFER_INTERRUPT:
237 endpoint_list_append_ep(&instance->int_list, ehci_ep);
238 /* Fall through */
239 case USB_TRANSFER_ISOCHRONOUS:
240 /* NOT SUPPORTED */
241 return;
242 case USB_TRANSFER_CONTROL:
243 case USB_TRANSFER_BULK:
244 endpoint_list_remove_ep(&instance->async_list, ehci_ep);
245 break;
246 }
247 fibril_mutex_lock(&instance->guard);
248 EHCI_SET(instance->registers->usbcmd, USB_CMD_ASYNC_SCHEDULE_FLAG);
249 fibril_condvar_wait(&instance->async_doorbell, &instance->guard);
250 fibril_mutex_unlock(&instance->guard);
251}
252
253int ehci_hc_status(hcd_t *hcd, uint32_t *status)
254{
255 assert(hcd);
256 hc_t *instance = hcd->driver.data;
257 assert(instance);
258 assert(status);
259 *status = 0;
260 if (instance->registers) {
261 *status = EHCI_RD(instance->registers->usbsts);
262 EHCI_WR(instance->registers->usbsts, *status);
263 }
264 return EOK;
265}
266
267/** Add USB transfer to the schedule.
268 *
269 * @param[in] hcd HCD driver structure.
270 * @param[in] batch Batch representing the transfer.
271 * @return Error code.
272 */
273int ehci_hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
274{
275 assert(hcd);
276 hc_t *instance = hcd->driver.data;
277 assert(instance);
278
279 /* Check for root hub communication */
280 if (batch->ep->address == ehci_rh_get_address(&instance->rh)) {
281 usb_log_debug("EHCI root hub request.\n");
282 return ehci_rh_schedule(&instance->rh, batch);
283 }
284 return ENOTSUP;
285}
286
287/** Interrupt handling routine
288 *
289 * @param[in] hcd HCD driver structure.
290 * @param[in] status Value of the status register at the time of interrupt.
291 */
292void ehci_hc_interrupt(hcd_t *hcd, uint32_t status)
293{
294 assert(hcd);
295 hc_t *instance = hcd->driver.data;
296 status = EHCI_RD(status);
297 assert(instance);
298 if (status & USB_STS_PORT_CHANGE_FLAG) {
299 ehci_rh_interrupt(&instance->rh);
300 }
301 if (status & USB_STS_ASYNC_SCHED_FLAG) {
302 fibril_condvar_signal(&instance->async_doorbell);
303 }
304}
305
306/** EHCI hw initialization routine.
307 *
308 * @param[in] instance EHCI hc driver structure.
309 */
310void hc_start(hc_t *instance)
311{
312 assert(instance);
313 /* Turn of the HC if it's running, Reseting a running device is
314 * undefined */
315 if (!(EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG)) {
316 /* disable all interrupts */
317 EHCI_WR(instance->registers->usbintr, 0);
318 /* ack all interrupts */
319 EHCI_WR(instance->registers->usbsts, 0x3f);
320 /* Stop HC hw */
321 EHCI_WR(instance->registers->usbcmd, 0);
322 /* Wait until hc is halted */
323 while ((EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG) == 0) {
324 async_usleep(1);
325 }
326 usb_log_info("EHCI turned off.\n");
327 } else {
328 usb_log_info("EHCI was not running.\n");
329 }
330
331 /* Hw initialization sequence, see page 53 (pdf 63) */
332 EHCI_SET(instance->registers->usbcmd, USB_CMD_HC_RESET_FLAG);
333 while (EHCI_RD(instance->registers->usbcmd) & USB_CMD_HC_RESET_FLAG) {
334 async_usleep(1);
335 }
336 /* Enable interrupts */
337 EHCI_WR(instance->registers->usbintr, USB_INTR_PORT_CHANGE_FLAG | USB_INTR_IRQ_FLAG | USB_INTR_ASYNC_ADVANCE_FLAG);
338 /* Use the lowest 4G segment */
339 EHCI_WR(instance->registers->ctrldssegment, 0);
340 /* Set periodic list */
341 assert(instance->periodic_list_base);
342 const uintptr_t phys_base =
343 addr_to_phys((void*)instance->periodic_list_base);
344 assert((phys_base & USB_PERIODIC_LIST_BASE_MASK) == phys_base);
345 EHCI_WR(instance->registers->periodiclistbase, phys_base);
346
347 /* start hc and get all ports */
348 EHCI_SET(instance->registers->usbcmd, USB_CMD_RUN_FLAG);
349 EHCI_SET(instance->registers->configflag, USB_CONFIG_FLAG_FLAG);
350
351 /* Enable Async schedule */
352 assert((instance->async_list.list_head_pa & USB_ASYNCLIST_MASK) ==
353 instance->async_list.list_head_pa);
354 EHCI_WR(instance->registers->asynclistaddr,
355 instance->async_list.list_head_pa);
356 EHCI_SET(instance->registers->usbcmd, USB_CMD_ASYNC_SCHEDULE_FLAG);
357#if 0
358 /*
359 * TURN OFF EHCI FOR NOW
360 */
361 usb_log_debug("USBCMD value: %x.\n",
362 EHCI_RD(instance->registers->usbcmd));
363 if (EHCI_RD(instance->registers->usbcmd) & USB_CMD_RUN_FLAG) {
364 /* disable all interrupts */
365 EHCI_WR(instance->registers->usbintr, 0);
366 /* ack all interrupts */
367 EHCI_WR(instance->registers->usbsts, 0x3f);
368 /* release RH ports */
369 EHCI_WR(instance->registers->configflag, 0);
370 EHCI_WR(instance->registers->usbcmd, 0);
371 /* Wait until hc is halted */
372 while ((EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG) == 0);
373 usb_log_info("EHCI turned off.\n");
374 } else {
375 usb_log_info("EHCI was not running.\n");
376 }
377#endif
378 usb_log_debug("Registers: \n"
379 "\t USBCMD(%p): %x(0x00080000 = at least 1ms between interrupts)\n"
380 "\t USBSTS(%p): %x(0x00001000 = HC halted)\n"
381 "\t USBINT(%p): %x(0x0 = no interrupts).\n"
382 "\t CONFIG(%p): %x(0x0 = ports controlled by companion hc).\n",
383 &instance->registers->usbcmd, EHCI_RD(instance->registers->usbcmd),
384 &instance->registers->usbsts, EHCI_RD(instance->registers->usbsts),
385 &instance->registers->usbintr, EHCI_RD(instance->registers->usbintr),
386 &instance->registers->configflag, EHCI_RD(instance->registers->configflag));
387}
388
389/** Initialize memory structures used by the EHCI hcd.
390 *
391 * @param[in] instance EHCI hc driver structure.
392 * @return Error code.
393 */
394int hc_init_memory(hc_t *instance)
395{
396 assert(instance);
397 int ret = endpoint_list_init(&instance->async_list, "ASYNC");
398 if (ret != EOK) {
399 usb_log_error("Failed to setup ASYNC list: %s", str_error(ret));
400 return ret;
401 }
402
403 ret = endpoint_list_init(&instance->int_list, "INT");
404 if (ret != EOK) {
405 usb_log_error("Failed to setup INT list: %s", str_error(ret));
406 endpoint_list_fini(&instance->async_list);
407 return ret;
408 }
409 /* Loop async list */
410 endpoint_list_chain(&instance->async_list, &instance->async_list);
411
412 /* Take 1024 periodic list heads, we ignore low mem options */
413 instance->periodic_list_base = get_page();
414 if (!instance->periodic_list_base) {
415 usb_log_error("Failed to get ISO schedule page.");
416 endpoint_list_fini(&instance->async_list);
417 endpoint_list_fini(&instance->int_list);
418 return ENOMEM;
419 }
420 for (unsigned i = 0;
421 i < PAGE_SIZE/sizeof(instance->periodic_list_base[0]); ++i)
422 {
423 /* Disable everything for now */
424 instance->periodic_list_base[i] =
425 LINK_POINTER_QH(instance->int_list.list_head_pa);
426 }
427 return EOK;
428}
429
430/**
431 * @}
432 */
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