source: mainline/uspace/drv/bus/usb/ehci/ehci_regs.h@ 09ab0a9a

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 09ab0a9a was 09ab0a9a, checked in by Jiri Svoboda <jiri@…>, 7 years ago

Fix vertical spacing with new Ccheck revision.
  • Property mode set to 100644
File size: 6.5 KB
Line 
1/*
2 * Copyright (c) 2013 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbehci
29 * @{
30 */
31/** @file
32 * @brief EHCI host controller register structure
33 */
34#ifndef DRV_EHCI_EHCI_REGS_H
35#define DRV_EHCI_EHCI_REGS_H
36
37#include <byteorder.h>
38#include <macros.h>
39#include <ddi.h>
40
41#define EHCI_WR(reg, val) pio_write_32(&(reg), host2uint32_t_le(val))
42#define EHCI_RD(reg) uint32_t_le2host(pio_read_32(&(reg)))
43#define EHCI_RD8(reg) pio_read_8(&(reg))
44#define EHCI_SET(reg, val) pio_set_32(&(reg), host2uint32_t_le(val), 10)
45#define EHCI_CLR(reg, val) pio_clear_32(&(reg), host2uint32_t_le(val), 10)
46
47/** EHCI memory mapped capability registers structure */
48typedef struct ehci_cap_regs {
49 const ioport8_t caplength;
50 PADD8(1);
51 const ioport16_t hciversion;
52 const ioport32_t hcsparams;
53#define EHCI_CAPS_HCS_DEBUG_PORT_MASK 0xf
54#define EHCI_CAPS_HCS_DEBUG_PORT_SHIFT (1 << 20)
55#define EHCI_CAPS_HCS_INDICATORS_FLAG (1 << 16)
56#define EHCI_CAPS_HCS_N_CC_MASK 0xf
57#define EHCI_CAPS_HCS_N_CC_SHIFT 12
58#define EHCI_CAPS_HCS_N_PCC_MASK 0xf
59#define EHCI_CAPS_HCS_N_PCC_SHIFT 8
60#define EHCI_CAPS_HCS_ROUTING_FLAG (1 << 7)
61#define EHCI_CAPS_HCS_PPC_FLAG (1 << 4)
62#define EHCI_CAPS_HCS_N_PORTS_MASK 0xf
63#define EHCI_CAPS_HCS_N_PORTS_SHIFT 0
64
65 const ioport32_t hccparams;
66#define EHCI_CAPS_HCC_EECP_MASK 0xff
67#define EHCI_CAPS_HCC_EECP_SHIFT 8
68#define EHCI_CAPS_HCC_ISO_THRESHOLD_MASK 0xf
69#define EHCI_CAPS_HCC_ISO_THRESHOLD_SHIFT 4
70#define EHCI_CAPS_HCC_ASYNC_PART_FLAG (1 << 2)
71#define EHCI_CAPS_HCC_PROG_FRAME_FLAG (1 << 1)
72#define EHCI_CAPS_HCC_64_FLAG (1 << 0)
73 ioport8_t hcsp_portoute[8];
74
75} ehci_caps_regs_t;
76
77/** EHCI memory mapped operational registers structure */
78typedef struct ehci_regs {
79 ioport32_t usbcmd;
80#define USB_CMD_INT_THRESHOLD_MASK 0xff
81#define USB_CMD_INT_THRESHOLD_SHIFT 16
82#define USB_CMD_PARK_MODE_FLAG (1 << 11)
83#define USB_CMD_PARK_COUNT_MASK 0x3
84#define USB_CMD_PARK_COUNT_SHIFT 8
85#define USB_CMD_LIGHT_RESET (1 << 7)
86#define USB_CMD_IRQ_ASYNC_DOORBELL (1 << 6)
87#define USB_CMD_ASYNC_SCHEDULE_FLAG (1 << 5)
88#define USB_CMD_PERIODIC_SCHEDULE_FLAG (1 << 4)
89#define USB_CMD_FRAME_LIST_SIZE_MASK 0x3
90#define USB_CMD_FRAME_LIST_SIZE_SHIFT 2
91#define USB_CMD_FRAME_LIST_SIZE_1024 0x0
92#define USB_CMD_FRAME_LIST_SIZE_512 0x1
93#define USB_CMD_FRAME_LIST_SIZE_256 0x2
94#define USB_CMD_HC_RESET_FLAG (1 << 1)
95#define USB_CMD_RUN_FLAG (1 << 0)
96
97 ioport32_t usbsts;
98#define USB_STS_ASYNC_SCHED_FLAG (1 << 15)
99#define USB_STS_PERIODIC_SCHED_FLAG (1 << 14)
100#define USB_STS_RECLAMATION_FLAG (1 << 13)
101#define USB_STS_HC_HALTED_FLAG (1 << 12)
102#define USB_STS_IRQ_ASYNC_ADVANCE_FLAG (1 << 5)
103#define USB_STS_HOST_ERROR_FLAG (1 << 4)
104#define USB_STS_FRAME_ROLLOVER_FLAG (1 << 3)
105#define USB_STS_PORT_CHANGE_FLAG (1 << 2)
106#define USB_STS_ERR_IRQ_FLAG (1 << 1)
107#define USB_STS_IRQ_FLAG (1 << 0)
108
109 ioport32_t usbintr;
110#define USB_INTR_ASYNC_ADVANCE_FLAG (1 << 5)
111#define USB_INTR_HOST_ERR_FLAG (1 << 4)
112#define USB_INTR_FRAME_ROLLOVER_FLAG (1 << 3)
113#define USB_INTR_PORT_CHANGE_FLAG (1 << 2)
114#define USB_INTR_ERR_IRQ_FLAG (1 << 1)
115#define USB_INTR_IRQ_FLAG (1 << 0)
116
117 ioport32_t frindex;
118#define USB_FRINDEX_MASK 0xfff
119
120 ioport32_t ctrldssegment;
121 ioport32_t periodiclistbase;
122#define USB_PERIODIC_LIST_BASE_MASK 0xfffff000
123
124 ioport32_t asynclistaddr;
125#define USB_ASYNCLIST_MASK 0xfffffff0
126
127 PADD32(9);
128
129 ioport32_t configflag;
130#define USB_CONFIG_FLAG_FLAG (1 << 0)
131
132 ioport32_t portsc[];
133#define USB_PORTSC_WKOC_E_FLAG (1 << 22)
134#define USB_PORTSC_WKDSCNNT_E_FLAG (1 << 21)
135#define USB_PORTSC_WKCNNT_E_FLAG (1 << 20)
136#define USB_PORTSC_PORT_TEST_MASK (0xf << 16)
137#define USB_PORTSC_NO_TEST (0x0 << 16)
138#define USB_PORTSC_TEST_J_STATE (0x1 << 16)
139#define USB_PORTSC_TEST_K_STATE (0x2 << 16)
140#define USB_PORTSC_TEST_SE0_NAK (0x3 << 16)
141#define USB_PORTSC_TEST_PACKET (0x4 << 16)
142#define USB_PORTSC_TEST_FORCE_ENABLE (0x5 << 16)
143#define USB_PORTSC_INDICATOR_MASK (0x3 << 14)
144#define USB_PORTSC_INDICATOR_OFF (0x0 << 14)
145#define USB_PORTSC_INDICATOR_AMBER (0x1 << 14)
146#define USB_PORTSC_INDICATOR_GREEN (0x2 << 14)
147#define USB_PORTSC_PORT_OWNER_FLAG (1 << 13)
148#define USB_PORTSC_PORT_POWER_FLAG (1 << 12)
149#define USB_PORTSC_LINE_STATUS_MASK (0x3 << 10)
150#define USB_PORTSC_LINE_STATUS_SE0 (0x0 << 10)
151#define USB_PORTSC_LINE_STATUS_K (0x1 << 10)
152#define USB_PORTSC_LINE_STATUS_J (0x2 << 10)
153#define USB_PORTSC_PORT_RESET_FLAG (1 << 8)
154#define USB_PORTSC_SUSPEND_FLAG (1 << 7)
155#define USB_PORTSC_RESUME_FLAG (1 << 6)
156#define USB_PORTSC_OC_CHANGE_FLAG (1 << 5)
157#define USB_PORTSC_OC_ACTIVE_FLAG (1 << 4)
158#define USB_PORTSC_EN_CHANGE_FLAG (1 << 3)
159#define USB_PORTSC_ENABLED_FLAG (1 << 2)
160#define USB_PORTSC_CONNECT_CH_FLAG (1 << 1)
161#define USB_PORTSC_CONNECT_FLAG (1 << 0)
162
163#define USB_PORTSC_WC_MASK \
164 (USB_PORTSC_CONNECT_CH_FLAG | USB_PORTSC_EN_CHANGE_FLAG | USB_PORTSC_OC_CHANGE_FLAG)
165} ehci_regs_t;
166
167#endif
168/**
169 * @}
170 */
Note: See TracBrowser for help on using the repository browser.