source: mainline/uspace/drv/bus/pci/pciintel/pci.h@ 6dbc500

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 6dbc500 was 6dbc500, checked in by Jakub Jermar <jakub@…>, 12 years ago

PIO_WINDOW_DEV_IFACE support for pciintel.

  • Property mode set to 100644
File size: 3.2 KB
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1/*
2 * Copyright (c) 2010 Lenka Trochtova
3 * Copyright (c) 2011 Jiri Svoboda
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/** @addtogroup pciintel
31 * @{
32 */
33/** @file
34 */
35
36#ifndef PCI_H_
37#define PCI_H_
38
39#include <ddf/driver.h>
40#include "pci_regs.h"
41
42#define PCI_MAX_HW_RES 10
43
44typedef struct pciintel_bus {
45 /** DDF device node */
46 ddf_dev_t *dnode;
47 uint32_t conf_io_addr;
48 uint32_t conf_io_data;
49 void *conf_data_port;
50 void *conf_addr_port;
51 pio_window_t pio_win;
52 fibril_mutex_t conf_mutex;
53} pci_bus_t;
54
55typedef struct pci_fun_data {
56 pci_bus_t *busptr;
57 ddf_fun_t *fnode;
58
59 int bus;
60 int dev;
61 int fn;
62 uint16_t vendor_id;
63 uint16_t device_id;
64 uint16_t command;
65 uint8_t class_code;
66 uint8_t subclass_code;
67 uint8_t prog_if;
68 uint8_t revision;
69 hw_resource_list_t hw_resources;
70 hw_resource_t resources[PCI_MAX_HW_RES];
71 pio_window_t pio_window;
72} pci_fun_t;
73
74extern void pci_fun_create_match_ids(pci_fun_t *);
75
76extern uint8_t pci_conf_read_8(pci_fun_t *, int);
77extern uint16_t pci_conf_read_16(pci_fun_t *, int);
78extern uint32_t pci_conf_read_32(pci_fun_t *, int);
79extern void pci_conf_write_8(pci_fun_t *, int, uint8_t);
80extern void pci_conf_write_16(pci_fun_t *, int, uint16_t);
81extern void pci_conf_write_32(pci_fun_t *, int, uint32_t);
82
83extern void pci_add_range(pci_fun_t *, uint64_t, size_t, bool);
84extern int pci_read_bar(pci_fun_t *, int);
85extern void pci_read_interrupt(pci_fun_t *);
86extern void pci_add_interrupt(pci_fun_t *, int);
87
88extern pci_fun_t *pci_fun_new(pci_bus_t *);
89extern void pci_fun_init(pci_fun_t *, int, int, int);
90extern void pci_fun_delete(pci_fun_t *);
91extern char *pci_fun_create_name(pci_fun_t *);
92
93extern void pci_bus_scan(pci_bus_t *, int);
94
95extern bool pci_alloc_resource_list(pci_fun_t *);
96extern void pci_clean_resource_list(pci_fun_t *);
97
98extern void pci_read_bars(pci_fun_t *);
99extern size_t pci_bar_mask_to_size(uint32_t);
100
101#endif
102
103/**
104 * @}
105 */
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