source: mainline/uspace/drv/bus/pci/pciintel/pci.c@ cd3fa47

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since cd3fa47 was 0464967, checked in by jzr <zarevucky.jiri@…>, 8 years ago

Fix gcc warnings when building with -O1 or -Og flags.
(Thanks Ondřej Hlavatý!)
  • Property mode set to 100644
File size: 22.3 KB
Line 
1/*
2 * Copyright (c) 2010 Lenka Trochtova
3 * Copyright (c) 2011 Jiri Svoboda
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/**
31 * @defgroup pciintel pci bus driver for intel method 1.
32 * @brief HelenOS root pci bus driver for intel method 1.
33 * @{
34 */
35
36/** @file
37 */
38
39#include <assert.h>
40#include <byteorder.h>
41#include <stdio.h>
42#include <errno.h>
43#include <stdbool.h>
44#include <fibril_synch.h>
45#include <str.h>
46#include <ctype.h>
47#include <macros.h>
48#include <str_error.h>
49
50#include <ddf/driver.h>
51#include <ddf/log.h>
52#include <ipc/dev_iface.h>
53#include <irc.h>
54#include <ops/hw_res.h>
55#include <device/hw_res.h>
56#include <ops/pio_window.h>
57#include <device/pio_window.h>
58#include <ddi.h>
59#include <pci_dev_iface.h>
60
61#include "pci.h"
62
63#define NAME "pciintel"
64
65#define CONF_ADDR_ENABLE (1 << 31)
66#define CONF_ADDR(bus, dev, fn, reg) \
67 ((bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
68
69/** Obtain PCI function soft-state from DDF function node */
70static pci_fun_t *pci_fun(ddf_fun_t *fnode)
71{
72 return ddf_fun_data_get(fnode);
73}
74
75/** Obtain PCI bus soft-state from DDF device node */
76#if 0
77static pci_bus_t *pci_bus(ddf_dev_t *dnode)
78{
79 return ddf_dev_data_get(dnode);
80}
81#endif
82
83/** Obtain PCI bus soft-state from function soft-state */
84static pci_bus_t *pci_bus_from_fun(pci_fun_t *fun)
85{
86 return fun->busptr;
87}
88
89/** Max is 47, align to something nice. */
90#define ID_MAX_STR_LEN 50
91
92static hw_resource_list_t *pciintel_get_resources(ddf_fun_t *fnode)
93{
94 pci_fun_t *fun = pci_fun(fnode);
95
96 if (fun == NULL)
97 return NULL;
98 return &fun->hw_resources;
99}
100
101static int pciintel_fun_owns_interrupt(pci_fun_t *fun, int irq)
102{
103 size_t i;
104 hw_resource_list_t *res = &fun->hw_resources;
105
106 for (i = 0; i < res->count; i++) {
107 if (res->resources[i].type == INTERRUPT &&
108 res->resources[i].res.interrupt.irq == irq) {
109 return true;
110 }
111 }
112
113 return false;
114}
115
116static int pciintel_enable_interrupt(ddf_fun_t *fnode, int irq)
117{
118 pci_fun_t *fun = pci_fun(fnode);
119
120 if (!pciintel_fun_owns_interrupt(fun, irq))
121 return EINVAL;
122
123 return irc_enable_interrupt(irq);
124}
125
126static int pciintel_disable_interrupt(ddf_fun_t *fnode, int irq)
127{
128 pci_fun_t *fun = pci_fun(fnode);
129
130 if (!pciintel_fun_owns_interrupt(fun, irq))
131 return EINVAL;
132
133 return irc_disable_interrupt(irq);
134}
135
136static int pciintel_clear_interrupt(ddf_fun_t *fnode, int irq)
137{
138 pci_fun_t *fun = pci_fun(fnode);
139
140 if (!pciintel_fun_owns_interrupt(fun, irq))
141 return EINVAL;
142
143 return irc_clear_interrupt(irq);
144}
145
146static pio_window_t *pciintel_get_pio_window(ddf_fun_t *fnode)
147{
148 pci_fun_t *fun = pci_fun(fnode);
149
150 if (fun == NULL)
151 return NULL;
152 return &fun->pio_window;
153}
154
155
156static int config_space_write_32(ddf_fun_t *fun, uint32_t address,
157 uint32_t data)
158{
159 if (address > 252)
160 return EINVAL;
161 pci_conf_write_32(pci_fun(fun), address, data);
162 return EOK;
163}
164
165static int config_space_write_16(
166 ddf_fun_t *fun, uint32_t address, uint16_t data)
167{
168 if (address > 254)
169 return EINVAL;
170 pci_conf_write_16(pci_fun(fun), address, data);
171 return EOK;
172}
173
174static int config_space_write_8(
175 ddf_fun_t *fun, uint32_t address, uint8_t data)
176{
177 if (address > 255)
178 return EINVAL;
179 pci_conf_write_8(pci_fun(fun), address, data);
180 return EOK;
181}
182
183static int config_space_read_32(
184 ddf_fun_t *fun, uint32_t address, uint32_t *data)
185{
186 if (address > 252)
187 return EINVAL;
188 *data = pci_conf_read_32(pci_fun(fun), address);
189 return EOK;
190}
191
192static int config_space_read_16(
193 ddf_fun_t *fun, uint32_t address, uint16_t *data)
194{
195 if (address > 254)
196 return EINVAL;
197 *data = pci_conf_read_16(pci_fun(fun), address);
198 return EOK;
199}
200
201static int config_space_read_8(
202 ddf_fun_t *fun, uint32_t address, uint8_t *data)
203{
204 if (address > 255)
205 return EINVAL;
206 *data = pci_conf_read_8(pci_fun(fun), address);
207 return EOK;
208}
209
210static hw_res_ops_t pciintel_hw_res_ops = {
211 .get_resource_list = &pciintel_get_resources,
212 .enable_interrupt = &pciintel_enable_interrupt,
213 .disable_interrupt = &pciintel_disable_interrupt,
214 .clear_interrupt = &pciintel_clear_interrupt,
215};
216
217static pio_window_ops_t pciintel_pio_window_ops = {
218 .get_pio_window = &pciintel_get_pio_window
219};
220
221static pci_dev_iface_t pci_dev_ops = {
222 .config_space_read_8 = &config_space_read_8,
223 .config_space_read_16 = &config_space_read_16,
224 .config_space_read_32 = &config_space_read_32,
225 .config_space_write_8 = &config_space_write_8,
226 .config_space_write_16 = &config_space_write_16,
227 .config_space_write_32 = &config_space_write_32
228};
229
230static ddf_dev_ops_t pci_fun_ops = {
231 .interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops,
232 .interfaces[PIO_WINDOW_DEV_IFACE] = &pciintel_pio_window_ops,
233 .interfaces[PCI_DEV_IFACE] = &pci_dev_ops
234};
235
236static int pci_dev_add(ddf_dev_t *);
237static int pci_fun_online(ddf_fun_t *);
238static int pci_fun_offline(ddf_fun_t *);
239
240/** PCI bus driver standard operations */
241static driver_ops_t pci_ops = {
242 .dev_add = &pci_dev_add,
243 .fun_online = &pci_fun_online,
244 .fun_offline = &pci_fun_offline,
245};
246
247/** PCI bus driver structure */
248static driver_t pci_driver = {
249 .name = NAME,
250 .driver_ops = &pci_ops
251};
252
253static void pci_conf_read(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
254{
255 const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
256 pci_bus_t *bus = pci_bus_from_fun(fun);
257 uint32_t val;
258
259 fibril_mutex_lock(&bus->conf_mutex);
260
261 if (bus->conf_addr_reg) {
262 pio_write_32(bus->conf_addr_reg,
263 host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
264 /*
265 * Always read full 32-bits from the PCI conf_data_port
266 * register and get the desired portion of it afterwards. Some
267 * architectures do not support shorter PIO reads offset from
268 * this register.
269 */
270 val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
271 } else {
272 val = uint32_t_le2host(pio_read_32(
273 &bus->conf_space[conf_addr / sizeof(ioport32_t)]));
274 }
275
276 switch (len) {
277 case 1:
278 *buf = (uint8_t) (val >> ((reg & 3) * 8));
279 break;
280 case 2:
281 *((uint16_t *) buf) = (uint16_t) (val >> ((reg & 3)) * 8);
282 break;
283 case 4:
284 *((uint32_t *) buf) = (uint32_t) val;
285 break;
286 }
287
288 fibril_mutex_unlock(&bus->conf_mutex);
289}
290
291static void pci_conf_write(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
292{
293 const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
294 pci_bus_t *bus = pci_bus_from_fun(fun);
295 uint32_t val = 0;
296
297 fibril_mutex_lock(&bus->conf_mutex);
298
299 /*
300 * Prepare to write full 32-bits to the PCI conf_data_port register.
301 * Some architectures do not support shorter PIO writes offset from this
302 * register.
303 */
304
305 if (len < 4) {
306 /*
307 * We have fewer than full 32-bits, so we need to read the
308 * missing bits first.
309 */
310 if (bus->conf_addr_reg) {
311 pio_write_32(bus->conf_addr_reg,
312 host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
313 val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
314 } else {
315 val = uint32_t_le2host(pio_read_32(
316 &bus->conf_space[conf_addr / sizeof(ioport32_t)]));
317 }
318 }
319
320 switch (len) {
321 case 1:
322 val &= ~(0xffU << ((reg & 3) * 8));
323 val |= *buf << ((reg & 3) * 8);
324 break;
325 case 2:
326 val &= ~(0xffffU << ((reg & 3) * 8));
327 val |= *((uint16_t *) buf) << ((reg & 3) * 8);
328 break;
329 case 4:
330 val = *((uint32_t *) buf);
331 break;
332 }
333
334 if (bus->conf_addr_reg) {
335 pio_write_32(bus->conf_addr_reg,
336 host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
337 pio_write_32(bus->conf_data_reg, host2uint32_t_le(val));
338 } else {
339 pio_write_32(&bus->conf_space[conf_addr / sizeof(ioport32_t)],
340 host2uint32_t_le(val));
341 }
342
343 fibril_mutex_unlock(&bus->conf_mutex);
344}
345
346uint8_t pci_conf_read_8(pci_fun_t *fun, int reg)
347{
348 uint8_t res;
349 pci_conf_read(fun, reg, &res, 1);
350 return res;
351}
352
353uint16_t pci_conf_read_16(pci_fun_t *fun, int reg)
354{
355 uint16_t res;
356 pci_conf_read(fun, reg, (uint8_t *) &res, 2);
357 return res;
358}
359
360uint32_t pci_conf_read_32(pci_fun_t *fun, int reg)
361{
362 uint32_t res;
363 pci_conf_read(fun, reg, (uint8_t *) &res, 4);
364 return res;
365}
366
367void pci_conf_write_8(pci_fun_t *fun, int reg, uint8_t val)
368{
369 pci_conf_write(fun, reg, (uint8_t *) &val, 1);
370}
371
372void pci_conf_write_16(pci_fun_t *fun, int reg, uint16_t val)
373{
374 pci_conf_write(fun, reg, (uint8_t *) &val, 2);
375}
376
377void pci_conf_write_32(pci_fun_t *fun, int reg, uint32_t val)
378{
379 pci_conf_write(fun, reg, (uint8_t *) &val, 4);
380}
381
382void pci_fun_create_match_ids(pci_fun_t *fun)
383{
384 int rc;
385 char match_id_str[ID_MAX_STR_LEN];
386
387 /* Vendor ID & Device ID, length(incl \0) 22 */
388 rc = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/ven=%04"
389 PRIx16 "&dev=%04" PRIx16, fun->vendor_id, fun->device_id);
390 if (rc < 0) {
391 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
392 str_error(rc));
393 }
394
395 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 90);
396 if (rc != EOK) {
397 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
398 }
399
400 /* Class, subclass, prog IF, revision, length(incl \0) 47 */
401 rc = snprintf(match_id_str, ID_MAX_STR_LEN,
402 "pci/class=%02x&subclass=%02x&progif=%02x&revision=%02x",
403 fun->class_code, fun->subclass_code, fun->prog_if, fun->revision);
404 if (rc < 0) {
405 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
406 str_error(rc));
407 }
408
409 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 70);
410 if (rc != EOK) {
411 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
412 }
413
414 /* Class, subclass, prog IF, length(incl \0) 35 */
415 rc = snprintf(match_id_str, ID_MAX_STR_LEN,
416 "pci/class=%02x&subclass=%02x&progif=%02x",
417 fun->class_code, fun->subclass_code, fun->prog_if);
418 if (rc < 0) {
419 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
420 str_error(rc));
421 }
422
423 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 60);
424 if (rc != EOK) {
425 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
426 }
427
428 /* Class, subclass, length(incl \0) 25 */
429 rc = snprintf(match_id_str, ID_MAX_STR_LEN,
430 "pci/class=%02x&subclass=%02x",
431 fun->class_code, fun->subclass_code);
432 if (rc < 0) {
433 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
434 str_error(rc));
435 }
436
437 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 50);
438 if (rc != EOK) {
439 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
440 }
441
442 /* Class, length(incl \0) 13 */
443 rc = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/class=%02x",
444 fun->class_code);
445 if (rc < 0) {
446 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
447 str_error(rc));
448 }
449
450 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 40);
451 if (rc != EOK) {
452 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
453 }
454
455 /* TODO add subsys ids, but those exist only in header type 0 */
456}
457
458void pci_add_range(pci_fun_t *fun, uint64_t range_addr, size_t range_size,
459 bool io)
460{
461 hw_resource_list_t *hw_res_list = &fun->hw_resources;
462 hw_resource_t *hw_resources = hw_res_list->resources;
463 size_t count = hw_res_list->count;
464
465 assert(hw_resources != NULL);
466 assert(count < PCI_MAX_HW_RES);
467
468 if (io) {
469 hw_resources[count].type = IO_RANGE;
470 hw_resources[count].res.io_range.address = range_addr;
471 hw_resources[count].res.io_range.size = range_size;
472 hw_resources[count].res.io_range.relative = true;
473 hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
474 } else {
475 hw_resources[count].type = MEM_RANGE;
476 hw_resources[count].res.mem_range.address = range_addr;
477 hw_resources[count].res.mem_range.size = range_size;
478 hw_resources[count].res.mem_range.relative = false;
479 hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
480 }
481
482 hw_res_list->count++;
483}
484
485/** Read the base address register (BAR) of the device and if it contains valid
486 * address add it to the devices hw resource list.
487 *
488 * @param fun PCI function
489 * @param addr The address of the BAR in the PCI configuration address space of
490 * the device
491 * @return The addr the address of the BAR which should be read next
492 */
493int pci_read_bar(pci_fun_t *fun, int addr)
494{
495 /* Value of the BAR */
496 uint32_t val;
497 uint32_t bar;
498 uint32_t mask;
499
500 /* IO space address */
501 bool io;
502 /* 64-bit wide address */
503 bool addrw64;
504
505 /* Size of the io or memory range specified by the BAR */
506 size_t range_size;
507 /* Beginning of the io or memory range specified by the BAR */
508 uint64_t range_addr;
509
510 /* Get the value of the BAR. */
511 val = pci_conf_read_32(fun, addr);
512
513#define IO_MASK (~0x3)
514#define MEM_MASK (~0xf)
515
516 io = (bool) (val & 1);
517 if (io) {
518 addrw64 = false;
519 mask = IO_MASK;
520 } else {
521 mask = MEM_MASK;
522 switch ((val >> 1) & 3) {
523 case 0:
524 addrw64 = false;
525 break;
526 case 2:
527 addrw64 = true;
528 break;
529 default:
530 /* reserved, go to the next BAR */
531 return addr + 4;
532 }
533 }
534
535 /* Get the address mask. */
536 pci_conf_write_32(fun, addr, 0xffffffff);
537 bar = pci_conf_read_32(fun, addr);
538
539 /*
540 * Unimplemented BARs read back as all 0's.
541 */
542 if (!bar)
543 return addr + (addrw64 ? 8 : 4);
544
545 mask &= bar;
546
547 /* Restore the original value. */
548 pci_conf_write_32(fun, addr, val);
549 val = pci_conf_read_32(fun, addr);
550
551 range_size = pci_bar_mask_to_size(mask);
552
553 if (addrw64) {
554 range_addr = ((uint64_t)pci_conf_read_32(fun, addr + 4) << 32) |
555 (val & 0xfffffff0);
556 } else {
557 range_addr = (val & 0xfffffff0);
558 }
559
560 if (range_addr != 0) {
561 ddf_msg(LVL_DEBUG, "Function %s : address = %" PRIx64
562 ", size = %x", ddf_fun_get_name(fun->fnode), range_addr,
563 (unsigned int) range_size);
564 }
565
566 pci_add_range(fun, range_addr, range_size, io);
567
568 if (addrw64)
569 return addr + 8;
570
571 return addr + 4;
572}
573
574void pci_add_interrupt(pci_fun_t *fun, int irq)
575{
576 hw_resource_list_t *hw_res_list = &fun->hw_resources;
577 hw_resource_t *hw_resources = hw_res_list->resources;
578 size_t count = hw_res_list->count;
579
580 assert(NULL != hw_resources);
581 assert(count < PCI_MAX_HW_RES);
582
583 hw_resources[count].type = INTERRUPT;
584 hw_resources[count].res.interrupt.irq = irq;
585
586 hw_res_list->count++;
587
588 ddf_msg(LVL_NOTE, "Function %s uses irq %x.", ddf_fun_get_name(fun->fnode), irq);
589}
590
591void pci_read_interrupt(pci_fun_t *fun)
592{
593 uint8_t irq = pci_conf_read_8(fun, PCI_BRIDGE_INT_LINE);
594 uint8_t pin = pci_conf_read_8(fun, PCI_BRIDGE_INT_PIN);
595
596 if (pin != 0 && irq != 0xff)
597 pci_add_interrupt(fun, irq);
598}
599
600/** Enumerate (recursively) and register the devices connected to a pci bus.
601 *
602 * @param bus Host-to-PCI bridge
603 * @param bus_num Bus number
604 */
605void pci_bus_scan(pci_bus_t *bus, int bus_num)
606{
607 pci_fun_t *fun;
608 int rc;
609
610 int child_bus = 0;
611 int dnum, fnum;
612 bool multi;
613 uint8_t header_type;
614
615 for (dnum = 0; dnum < 32; dnum++) {
616 multi = true;
617 for (fnum = 0; multi && fnum < 8; fnum++) {
618 fun = pci_fun_new(bus);
619
620 pci_fun_init(fun, bus_num, dnum, fnum);
621 if (fun->vendor_id == 0xffff) {
622 pci_fun_delete(fun);
623 /*
624 * The device is not present, go on scanning the
625 * bus.
626 */
627 if (fnum == 0)
628 break;
629 else
630 continue;
631 }
632
633 header_type = pci_conf_read_8(fun, PCI_HEADER_TYPE);
634 if (fnum == 0) {
635 /* Is the device multifunction? */
636 multi = header_type >> 7;
637 }
638 /* Clear the multifunction bit. */
639 header_type = header_type & 0x7F;
640
641 char *fun_name = pci_fun_create_name(fun);
642 if (fun_name == NULL) {
643 ddf_msg(LVL_ERROR, "Out of memory.");
644 pci_fun_delete(fun);
645 return;
646 }
647
648 rc = ddf_fun_set_name(fun->fnode, fun_name);
649 free(fun_name);
650 if (rc != EOK) {
651 ddf_msg(LVL_ERROR, "Failed setting function name.");
652 pci_fun_delete(fun);
653 return;
654 }
655
656 pci_alloc_resource_list(fun);
657 pci_read_bars(fun);
658 pci_read_interrupt(fun);
659
660 /* Propagate the PIO window to the function. */
661 fun->pio_window = bus->pio_win;
662
663 ddf_fun_set_ops(fun->fnode, &pci_fun_ops);
664
665 ddf_msg(LVL_DEBUG, "Adding new function %s.",
666 ddf_fun_get_name(fun->fnode));
667
668 pci_fun_create_match_ids(fun);
669
670 if (ddf_fun_bind(fun->fnode) != EOK) {
671 pci_clean_resource_list(fun);
672 pci_fun_delete(fun);
673 continue;
674 }
675
676 if (header_type == PCI_HEADER_TYPE_BRIDGE ||
677 header_type == PCI_HEADER_TYPE_CARDBUS) {
678 child_bus = pci_conf_read_8(fun,
679 PCI_BRIDGE_SEC_BUS_NUM);
680 ddf_msg(LVL_DEBUG, "Device is pci-to-pci "
681 "bridge, secondary bus number = %d.",
682 bus_num);
683 if (child_bus > bus_num)
684 pci_bus_scan(bus, child_bus);
685 }
686 }
687 }
688}
689
690static int pci_dev_add(ddf_dev_t *dnode)
691{
692 hw_resource_list_t hw_resources;
693 pci_bus_t *bus = NULL;
694 ddf_fun_t *ctl = NULL;
695 bool got_res = false;
696 async_sess_t *sess;
697 int rc;
698
699 ddf_msg(LVL_DEBUG, "pci_dev_add");
700
701 bus = ddf_dev_data_alloc(dnode, sizeof(pci_bus_t));
702 if (bus == NULL) {
703 ddf_msg(LVL_ERROR, "pci_dev_add allocation failed.");
704 rc = ENOMEM;
705 goto fail;
706 }
707 fibril_mutex_initialize(&bus->conf_mutex);
708
709 bus->dnode = dnode;
710
711 sess = ddf_dev_parent_sess_get(dnode);
712 if (sess == NULL) {
713 ddf_msg(LVL_ERROR, "pci_dev_add failed to connect to the "
714 "parent driver.");
715 rc = ENOENT;
716 goto fail;
717 }
718
719 rc = pio_window_get(sess, &bus->pio_win);
720 if (rc != EOK) {
721 ddf_msg(LVL_ERROR, "pci_dev_add failed to get PIO window "
722 "for the device.");
723 goto fail;
724 }
725
726 rc = hw_res_get_resource_list(sess, &hw_resources);
727 if (rc != EOK) {
728 ddf_msg(LVL_ERROR, "pci_dev_add failed to get hw resources "
729 "for the device.");
730 goto fail;
731 }
732 got_res = true;
733
734
735 assert(hw_resources.count >= 1);
736
737 if (hw_resources.count == 1) {
738 assert(hw_resources.resources[0].type == MEM_RANGE);
739
740 ddf_msg(LVL_DEBUG, "conf_addr_space = %" PRIx64 ".",
741 hw_resources.resources[0].res.mem_range.address);
742
743 if (pio_enable_resource(&bus->pio_win,
744 &hw_resources.resources[0],
745 (void **) &bus->conf_space)) {
746 ddf_msg(LVL_ERROR,
747 "Failed to map configuration space.");
748 rc = EADDRNOTAVAIL;
749 goto fail;
750 }
751
752 } else {
753 assert(hw_resources.resources[0].type == IO_RANGE);
754 assert(hw_resources.resources[0].res.io_range.size >= 4);
755
756 assert(hw_resources.resources[1].type == IO_RANGE);
757 assert(hw_resources.resources[1].res.io_range.size >= 4);
758
759 ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".",
760 hw_resources.resources[0].res.io_range.address);
761 ddf_msg(LVL_DEBUG, "data_addr = %" PRIx64 ".",
762 hw_resources.resources[1].res.io_range.address);
763
764 if (pio_enable_resource(&bus->pio_win,
765 &hw_resources.resources[0],
766 (void **) &bus->conf_addr_reg)) {
767 ddf_msg(LVL_ERROR,
768 "Failed to enable configuration ports.");
769 rc = EADDRNOTAVAIL;
770 goto fail;
771 }
772 if (pio_enable_resource(&bus->pio_win,
773 &hw_resources.resources[1],
774 (void **) &bus->conf_data_reg)) {
775 ddf_msg(LVL_ERROR,
776 "Failed to enable configuration ports.");
777 rc = EADDRNOTAVAIL;
778 goto fail;
779 }
780 }
781
782 /* Make the bus device more visible. It has no use yet. */
783 ddf_msg(LVL_DEBUG, "Adding a 'ctl' function");
784
785 ctl = ddf_fun_create(bus->dnode, fun_exposed, "ctl");
786 if (ctl == NULL) {
787 ddf_msg(LVL_ERROR, "Failed creating control function.");
788 rc = ENOMEM;
789 goto fail;
790 }
791
792 rc = ddf_fun_bind(ctl);
793 if (rc != EOK) {
794 ddf_msg(LVL_ERROR, "Failed binding control function.");
795 goto fail;
796 }
797
798 /* Enumerate functions. */
799 ddf_msg(LVL_DEBUG, "Scanning the bus");
800 pci_bus_scan(bus, 0);
801
802 hw_res_clean_resource_list(&hw_resources);
803
804 return EOK;
805
806fail:
807 if (got_res)
808 hw_res_clean_resource_list(&hw_resources);
809
810 if (ctl != NULL)
811 ddf_fun_destroy(ctl);
812
813 return rc;
814}
815
816static int pci_fun_online(ddf_fun_t *fun)
817{
818 ddf_msg(LVL_DEBUG, "pci_fun_online()");
819 return ddf_fun_online(fun);
820}
821
822static int pci_fun_offline(ddf_fun_t *fun)
823{
824 ddf_msg(LVL_DEBUG, "pci_fun_offline()");
825 return ddf_fun_offline(fun);
826}
827
828static void pciintel_init(void)
829{
830 ddf_log_init(NAME);
831}
832
833pci_fun_t *pci_fun_new(pci_bus_t *bus)
834{
835 pci_fun_t *fun;
836 ddf_fun_t *fnode;
837
838 fnode = ddf_fun_create(bus->dnode, fun_inner, NULL);
839 if (fnode == NULL)
840 return NULL;
841
842 fun = ddf_fun_data_alloc(fnode, sizeof(pci_fun_t));
843 if (fun == NULL)
844 return NULL;
845
846 fun->busptr = bus;
847 fun->fnode = fnode;
848 return fun;
849}
850
851void pci_fun_init(pci_fun_t *fun, int bus, int dev, int fn)
852{
853 fun->bus = bus;
854 fun->dev = dev;
855 fun->fn = fn;
856 fun->vendor_id = pci_conf_read_16(fun, PCI_VENDOR_ID);
857 fun->device_id = pci_conf_read_16(fun, PCI_DEVICE_ID);
858
859 /* Explicitly enable PCI bus mastering */
860 fun->command = pci_conf_read_16(fun, PCI_COMMAND) |
861 PCI_COMMAND_MASTER;
862 pci_conf_write_16(fun, PCI_COMMAND, fun->command);
863
864 fun->class_code = pci_conf_read_8(fun, PCI_BASE_CLASS);
865 fun->subclass_code = pci_conf_read_8(fun, PCI_SUB_CLASS);
866 fun->prog_if = pci_conf_read_8(fun, PCI_PROG_IF);
867 fun->revision = pci_conf_read_8(fun, PCI_REVISION_ID);
868}
869
870void pci_fun_delete(pci_fun_t *fun)
871{
872 hw_res_clean_resource_list(&fun->hw_resources);
873 if (fun->fnode != NULL)
874 ddf_fun_destroy(fun->fnode);
875}
876
877char *pci_fun_create_name(pci_fun_t *fun)
878{
879 char *name = NULL;
880
881 asprintf(&name, "%02x:%02x.%01x", fun->bus, fun->dev,
882 fun->fn);
883 return name;
884}
885
886bool pci_alloc_resource_list(pci_fun_t *fun)
887{
888 fun->hw_resources.resources = fun->resources;
889 return true;
890}
891
892void pci_clean_resource_list(pci_fun_t *fun)
893{
894 fun->hw_resources.resources = NULL;
895}
896
897/** Read the base address registers (BARs) of the function and add the addresses
898 * to its HW resource list.
899 *
900 * @param fun PCI function
901 */
902void pci_read_bars(pci_fun_t *fun)
903{
904 /*
905 * Position of the BAR in the PCI configuration address space of the
906 * device.
907 */
908 int addr = PCI_BASE_ADDR_0;
909
910 while (addr <= PCI_BASE_ADDR_5)
911 addr = pci_read_bar(fun, addr);
912}
913
914size_t pci_bar_mask_to_size(uint32_t mask)
915{
916 size_t size = mask & ~(mask - 1);
917 return size;
918}
919
920int main(int argc, char *argv[])
921{
922 printf(NAME ": HelenOS PCI bus driver (Intel method 1).\n");
923 pciintel_init();
924 return ddf_driver_main(&pci_driver);
925}
926
927/**
928 * @}
929 */
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